430 lines
15 KiB
Systemverilog
430 lines
15 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite to AXI4 adapter (write)
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*/
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module taxi_axil_axi_adapter_wr
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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/*
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* AXI4 master interface
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*/
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taxi_axi_if.wr_mst m_axi_wr
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);
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// extract parameters
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localparam AXIL_DATA_W = s_axil_wr.DATA_W;
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localparam ADDR_W = s_axil_wr.ADDR_W;
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localparam AXIL_STRB_W = s_axil_wr.STRB_W;
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localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axi_wr.AWUSER_EN;
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localparam AWUSER_W = s_axil_wr.AWUSER_W;
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localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axi_wr.WUSER_EN;
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localparam WUSER_W = s_axil_wr.WUSER_W;
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localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axi_wr.BUSER_EN;
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localparam BUSER_W = s_axil_wr.BUSER_W;
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localparam AXI_DATA_W = m_axi_wr.DATA_W;
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localparam AXI_STRB_W = m_axi_wr.STRB_W;
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localparam AXI_BURST_SIZE = $clog2(AXI_STRB_W);
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localparam S_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W);
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localparam M_ADDR_BIT_OFFSET = $clog2(AXI_STRB_W);
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localparam S_BYTE_LANES = AXIL_STRB_W;
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localparam M_BYTE_LANES = AXI_STRB_W;
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localparam S_BYTE_W = AXIL_DATA_W/S_BYTE_LANES;
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localparam M_BYTE_W = AXI_DATA_W/M_BYTE_LANES;
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localparam S_ADDR_MASK = {ADDR_W{1'b1}} << S_ADDR_BIT_OFFSET;
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localparam M_ADDR_MASK = {ADDR_W{1'b1}} << M_ADDR_BIT_OFFSET;
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// check configuration
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if (S_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
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$fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
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if (M_BYTE_W * AXI_STRB_W != AXI_DATA_W)
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$fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)");
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if (S_BYTE_W != M_BYTE_W)
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$fatal(0, "Error: byte size mismatch (instance %m)");
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if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES)
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$fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)");
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if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES)
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$fatal(0, "Error: AXI master interface byte lane count must be even power of two (instance %m)");
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if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
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// same width; bypass
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assign m_axi_wr.awid = '0;
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assign m_axi_wr.awaddr = s_axil_wr.awaddr;
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assign m_axi_wr.awlen = '0;
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assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE);
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assign m_axi_wr.awburst = 2'b01;
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assign m_axi_wr.awlock = 1'b0;
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assign m_axi_wr.awcache = 4'b0011;
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assign m_axi_wr.awprot = s_axil_wr.awprot;
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assign m_axi_wr.awqos = '0;
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assign m_axi_wr.awregion = '0;
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assign m_axi_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
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assign m_axi_wr.awvalid = s_axil_wr.awvalid;
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assign s_axil_wr.awready = m_axi_wr.awready;
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assign m_axi_wr.wdata = s_axil_wr.wdata;
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assign m_axi_wr.wstrb = s_axil_wr.wstrb;
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assign m_axi_wr.wlast = 1'b1;
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assign m_axi_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0;
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assign m_axi_wr.wvalid = s_axil_wr.wvalid;
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assign s_axil_wr.wready = m_axi_wr.wready;
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assign s_axil_wr.bresp = m_axi_wr.bresp;
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assign s_axil_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
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assign s_axil_wr.bvalid = m_axi_wr.bvalid;
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assign m_axi_wr.bready = s_axil_wr.bready;
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end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
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// output is wider; upsize
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localparam [0:0]
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STATE_IDLE = 1'd0,
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STATE_DATA = 1'd1;
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logic [0:0] state_reg = STATE_IDLE, state_next;
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logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
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logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
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logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
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logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
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logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
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logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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logic [AXI_DATA_W-1:0] m_axi_wdata_reg = '0, m_axi_wdata_next;
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logic [AXI_STRB_W-1:0] m_axi_wstrb_reg = '0, m_axi_wstrb_next;
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logic [WUSER_W-1:0] m_axi_wuser_reg = '0, m_axi_wuser_next;
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logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign m_axi_wr.awid = '0;
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assign m_axi_wr.awaddr = m_axi_awaddr_reg;
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assign m_axi_wr.awlen = '0;
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assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE);
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assign m_axi_wr.awburst = 2'b01;
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assign m_axi_wr.awlock = 1'b0;
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assign m_axi_wr.awcache = 4'b0011;
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assign m_axi_wr.awprot = m_axi_awprot_reg;
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assign m_axi_wr.awqos = '0;
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assign m_axi_wr.awregion = '0;
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assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
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assign m_axi_wr.awvalid = m_axi_awvalid_reg;
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assign m_axi_wr.wdata = m_axi_wdata_reg;
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assign m_axi_wr.wstrb = m_axi_wstrb_reg;
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assign m_axi_wr.wlast = '1;
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assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
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assign m_axi_wr.wvalid = m_axi_wvalid_reg;
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// B channel passthrough
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assign s_axil_wr.bresp = m_axi_wr.bresp;
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assign s_axil_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
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assign s_axil_wr.bvalid = m_axi_wr.bvalid;
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assign m_axi_wr.bready = s_axil_wr.bready;
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always_comb begin
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state_next = STATE_IDLE;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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m_axi_awaddr_next = m_axi_awaddr_reg;
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m_axi_awprot_next = m_axi_awprot_reg;
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m_axi_awuser_next = m_axi_awuser_reg;
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m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready;
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m_axi_wdata_next = m_axi_wdata_reg;
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m_axi_wstrb_next = m_axi_wstrb_reg;
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m_axi_wuser_next = m_axi_wuser_reg;
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m_axi_wvalid_next = m_axi_wvalid_reg && !m_axi_wr.wready;
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case (state_reg)
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STATE_IDLE: begin
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s_axil_awready_next = !m_axi_wr.awvalid;
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if (s_axil_wr.awready && s_axil_wr.awvalid) begin
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s_axil_awready_next = 1'b0;
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m_axi_awaddr_next = s_axil_wr.awaddr;
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m_axi_awprot_next = s_axil_wr.awprot;
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m_axi_awuser_next = s_axil_wr.awuser;
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m_axi_awvalid_next = 1'b1;
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s_axil_wready_next = !m_axi_wr.wvalid;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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s_axil_wready_next = !m_axi_wr.wvalid;
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if (s_axil_wr.wready && s_axil_wr.wvalid) begin
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s_axil_wready_next = 1'b0;
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m_axi_wdata_next = {(M_BYTE_LANES/S_BYTE_LANES){s_axil_wr.wdata}};
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m_axi_wstrb_next = '0;
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m_axi_wstrb_next[m_axi_awaddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * AXIL_STRB_W +: AXIL_STRB_W] = s_axil_wr.wstrb;
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m_axi_wuser_next = s_axil_wr.wuser;
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m_axi_wvalid_next = 1'b1;
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s_axil_awready_next = !m_axi_wr.awvalid;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_DATA;
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end
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end
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default: begin
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state_next = STATE_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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s_axil_awready_reg <= s_axil_awready_next;
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s_axil_wready_reg <= s_axil_wready_next;
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m_axi_awaddr_reg <= m_axi_awaddr_next;
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m_axi_awprot_reg <= m_axi_awprot_next;
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m_axi_awuser_reg <= m_axi_awuser_next;
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m_axi_awvalid_reg <= m_axi_awvalid_next;
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m_axi_wdata_reg <= m_axi_wdata_next;
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m_axi_wstrb_reg <= m_axi_wstrb_next;
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m_axi_wuser_reg <= m_axi_wuser_next;
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m_axi_wvalid_reg <= m_axi_wvalid_next;
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if (rst) begin
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state_reg <= STATE_IDLE;
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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m_axi_awvalid_reg <= 1'b0;
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m_axi_wvalid_reg <= 1'b0;
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end
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end
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end else begin : downsize
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// output is narrower; downsize
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// output bus is wider
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localparam DATA_W = AXIL_DATA_W;
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localparam STRB_W = AXIL_STRB_W;
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// required number of segments in wider bus
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localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
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localparam SEG_COUNT_W = $clog2(SEG_COUNT);
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// data width and keep width per segment
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localparam SEG_DATA_W = DATA_W / SEG_COUNT;
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localparam SEG_STRB_W = STRB_W / SEG_COUNT;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_DATA = 2'd1,
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STATE_RESP = 2'd3;
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logic [1:0] state_reg = STATE_IDLE, state_next;
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logic [DATA_W-1:0] data_reg = '0, data_next;
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logic [STRB_W-1:0] strb_reg = '0, strb_next;
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logic [SEG_COUNT_W-1:0] current_seg_reg = 0, current_seg_next;
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logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
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logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
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logic [1:0] s_axil_bresp_reg = '0, s_axil_bresp_next;
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logic [BUSER_W-1:0] s_axil_buser_reg = '0, s_axil_buser_next;
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logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
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logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
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logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
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logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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logic [AXI_DATA_W-1:0] m_axi_wdata_reg = '0, m_axi_wdata_next;
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logic [AXI_STRB_W-1:0] m_axi_wstrb_reg = '0, m_axi_wstrb_next;
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logic [WUSER_W-1:0] m_axi_wuser_reg = '0, m_axi_wuser_next;
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logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
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logic m_axi_bready_reg = 1'b0, m_axi_bready_next;
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign s_axil_wr.bresp = s_axil_bresp_reg;
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assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
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assign s_axil_wr.bvalid = s_axil_bvalid_reg;
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assign m_axi_wr.awid = '0;
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assign m_axi_wr.awaddr = m_axi_awaddr_reg;
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assign m_axi_wr.awlen = '0;
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assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE);
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assign m_axi_wr.awburst = 2'b01;
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assign m_axi_wr.awlock = 1'b0;
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assign m_axi_wr.awcache = 4'b0011;
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assign m_axi_wr.awprot = m_axi_awprot_reg;
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assign m_axi_wr.awqos = '0;
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assign m_axi_wr.awregion = '0;
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assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
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assign m_axi_wr.awvalid = m_axi_awvalid_reg;
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assign m_axi_wr.wdata = m_axi_wdata_reg;
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assign m_axi_wr.wstrb = m_axi_wstrb_reg;
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assign m_axi_wr.wlast = '1;
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assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
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assign m_axi_wr.wvalid = m_axi_wvalid_reg;
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assign m_axi_wr.bready = m_axi_bready_reg;
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always_comb begin
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state_next = STATE_IDLE;
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data_next = data_reg;
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strb_next = strb_reg;
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current_seg_next = current_seg_reg;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bresp_next = s_axil_bresp_reg;
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s_axil_buser_next = s_axil_buser_reg;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
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m_axi_awaddr_next = m_axi_awaddr_reg;
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m_axi_awprot_next = m_axi_awprot_reg;
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m_axi_awuser_next = m_axi_awuser_reg;
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m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready;
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m_axi_wdata_next = m_axi_wdata_reg;
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m_axi_wstrb_next = m_axi_wstrb_reg;
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m_axi_wuser_next = m_axi_wuser_reg;
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m_axi_wvalid_next = m_axi_wvalid_reg && !m_axi_wr.wready;
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m_axi_bready_next = 1'b0;
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// master output is narrower; may need several cycles
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case (state_reg)
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STATE_IDLE: begin
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s_axil_awready_next = !m_axi_wr.awvalid;
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current_seg_next = s_axil_wr.awaddr[M_ADDR_BIT_OFFSET +: SEG_COUNT_W];
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s_axil_bresp_next = 2'd0;
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if (s_axil_wr.awready && s_axil_wr.awvalid) begin
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s_axil_awready_next = 1'b0;
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m_axi_awaddr_next = s_axil_wr.awaddr;
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m_axi_awprot_next = s_axil_wr.awprot;
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m_axi_awuser_next = s_axil_wr.awuser;
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m_axi_awvalid_next = 1'b1;
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s_axil_wready_next = !m_axi_wr.wvalid;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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s_axil_wready_next = !m_axi_wr.wvalid;
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if (s_axil_wr.wready && s_axil_wr.wvalid) begin
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s_axil_wready_next = 1'b0;
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data_next = s_axil_wr.wdata;
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strb_next = s_axil_wr.wstrb;
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m_axi_wdata_next = data_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W];
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m_axi_wstrb_next = strb_next[current_seg_reg*SEG_STRB_W +: SEG_STRB_W];
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m_axi_wuser_next = s_axil_wr.wuser;
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m_axi_wvalid_next = 1'b1;
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m_axi_bready_next = !s_axil_wr.bvalid;
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current_seg_next = current_seg_reg + 1;
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state_next = STATE_RESP;
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end else begin
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state_next = STATE_DATA;
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end
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end
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STATE_RESP: begin
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m_axi_bready_next = !s_axil_wr.bvalid;
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if (m_axi_wr.bready && m_axi_wr.bvalid) begin
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m_axi_bready_next = 1'b0;
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m_axi_awaddr_next = (m_axi_awaddr_reg & M_ADDR_MASK) + SEG_STRB_W;
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m_axi_wdata_next = data_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W];
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m_axi_wstrb_next = strb_next[current_seg_reg*SEG_STRB_W +: SEG_STRB_W];
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s_axil_buser_next = m_axi_wr.buser;
|
|
current_seg_next = current_seg_reg + 1;
|
|
if (m_axi.bresp != 0) begin
|
|
s_axil_bresp_next = m_axi_wr.bresp;
|
|
end
|
|
if (current_seg_reg == 0) begin
|
|
s_axil_bvalid_next = 1'b1;
|
|
s_axil_awready_next = !m_axi_wr.awvalid;
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
m_axi_awvalid_next = 1'b1;
|
|
m_axi_wvalid_next = 1'b1;
|
|
state_next = STATE_RESP;
|
|
end
|
|
end else begin
|
|
state_next = STATE_RESP;
|
|
end
|
|
end
|
|
default: begin
|
|
state_next = STATE_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
data_reg <= data_next;
|
|
strb_reg <= strb_next;
|
|
|
|
current_seg_reg <= current_seg_next;
|
|
|
|
s_axil_awready_reg <= s_axil_awready_next;
|
|
s_axil_wready_reg <= s_axil_wready_next;
|
|
s_axil_bresp_reg <= s_axil_bresp_next;
|
|
s_axil_buser_reg <= s_axil_buser_next;
|
|
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
|
|
|
m_axi_awaddr_reg <= m_axi_awaddr_next;
|
|
m_axi_awprot_reg <= m_axi_awprot_next;
|
|
m_axi_awuser_reg <= m_axi_awuser_next;
|
|
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
|
m_axi_wdata_reg <= m_axi_wdata_next;
|
|
m_axi_wstrb_reg <= m_axi_wstrb_next;
|
|
m_axi_wuser_reg <= m_axi_wuser_next;
|
|
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
|
m_axi_bready_reg <= m_axi_bready_next;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
s_axil_awready_reg <= 1'b0;
|
|
s_axil_wready_reg <= 1'b0;
|
|
s_axil_bvalid_reg <= 1'b0;
|
|
|
|
m_axi_awvalid_reg <= 1'b0;
|
|
m_axi_wvalid_reg <= 1'b0;
|
|
m_axi_bready_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|