107 lines
2.4 KiB
Systemverilog
107 lines
2.4 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite interconnect
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*/
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module taxi_axil_interconnect_1s_wr #
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(
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Number of concurrent operations for each slave interface
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// 1 concatenated fields of 32 bits
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = '0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-lite slave interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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/*
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* AXI4-lite master interfaces
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*/
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taxi_axil_if.wr_mst m_axil_wr[M_COUNT]
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);
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taxi_axil_if #(
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.DATA_W(s_axil_wr.DATA_W),
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.ADDR_W(s_axil_wr.ADDR_W),
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.STRB_W(s_axil_wr.STRB_W),
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.AWUSER_EN(s_axil_wr.AWUSER_EN),
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.AWUSER_W(s_axil_wr.AWUSER_W),
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.WUSER_EN(s_axil_wr.WUSER_EN),
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.WUSER_W(s_axil_wr.WUSER_W),
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.BUSER_EN(s_axil_wr.BUSER_EN),
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.BUSER_W(s_axil_wr.BUSER_W),
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.ARUSER_EN(s_axil_wr.ARUSER_EN),
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.ARUSER_W(s_axil_wr.ARUSER_W),
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.RUSER_EN(s_axil_wr.RUSER_EN),
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.RUSER_W(s_axil_wr.RUSER_W)
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)
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s_axil_wr_int[1]();
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taxi_axil_tie_wr
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tie_inst (
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.s_axil_wr(s_axil_wr),
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.m_axil_wr(s_axil_wr_int[0])
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);
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taxi_axil_interconnect_wr #(
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.S_COUNT(1),
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.M_COUNT(M_COUNT),
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.ADDR_W(ADDR_W),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_SECURE(M_SECURE)
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)
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wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-lite slave interface
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*/
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.s_axil_wr(s_axil_wr_int),
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/*
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* AXI4-lite master interfaces
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*/
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.m_axil_wr(m_axil_wr)
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);
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endmodule
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`resetall
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