xfcp: Add taxi_xfcp_mod_apb.f

Signed-off-by: Alex Forencich <alex@alexforencich.com>

.github/workflows/regression-tests.yml

@@ -21,7 +21,7 @@ jobs:
     - name: Install Verilator
       uses: v0xnihili/install-verilator-action@main
       with:
-        version: v5.034
+        version: v5.038
 
     - name: Install Python dependencies
       run: |

.gitignore

@@ -5,3 +5,5 @@
 *.pyc
 *.vvp
 
+sim_build
+results.xml

README.md

@@ -26,11 +26,15 @@ To facilitate the dual-license model, contributions to the project can only be a
 
 *  APB
     *  SV interface for APB
+    *  Interconnect
+    *  Width converter
     *  Single-port RAM
     *  Dual-port RAM
 *  AXI
     *  SV interface for AXI
     *  AXI to AXI lite adapter
+    *  Crossbar
+    *  Interconnect
     *  Register slice
     *  Width converter
     *  Synchronous FIFO
@@ -39,6 +43,8 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  SV interface for AXI lite
     *  AXI lite to AXI adapter
     *  AXI lite to APB adapter
+    *  Crossbar
+    *  Interconnect
     *  Register slice
     *  Width converter
     *  Single-port RAM
@@ -87,7 +93,7 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  MII PHY interface
     *  GMII PHY interface
     *  RGMII PHY interface
-    *  10G/25G MAC/PHY/GT wrapper for UltraScale/UltraScale+
+    *  10G/25G MAC/PHY/GT wrapper for 7-series/UltraScale/UltraScale+
 *  General input/output
     *  Switch debouncer
     *  LED shift register driver
@@ -156,6 +162,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
 *  Alibaba AS02MC04 (Xilinx Kintex UltraScale+ XCKU3P)
 *  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
+*  Digilent NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
 *  HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
 *  HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
 *  HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
@@ -172,6 +179,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
 *  Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
+*  Xilinx VC709 (Xilinx Virtex 7 XC7V690T)
 *  Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
 *  Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
 *  Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)

src/apb/rtl/taxi_apb_adapter.sv

@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB width adapter
+ */
+module taxi_apb_adapter
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * APB slave interface
+     */
+    taxi_apb_if.slv    s_apb,
+
+    /*
+     * APB master interface
+     */
+    taxi_apb_if.mst    m_apb
+);
+
+// extract parameters
+localparam S_DATA_W = s_apb.DATA_W;
+localparam ADDR_W = s_apb.ADDR_W;
+localparam S_STRB_W = s_apb.STRB_W;
+localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb.PAUSER_EN;
+localparam PAUSER_W = s_apb.PAUSER_W;
+localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb.PWUSER_EN;
+localparam PWUSER_W = s_apb.PWUSER_W;
+localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb.PRUSER_EN;
+localparam PRUSER_W = s_apb.PRUSER_W;
+localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb.PBUSER_EN;
+localparam PBUSER_W = s_apb.PBUSER_W;
+
+localparam M_DATA_W = m_apb.DATA_W;
+localparam M_STRB_W = m_apb.STRB_W;
+
+localparam S_ADDR_BIT_OFFSET = $clog2(S_STRB_W);
+localparam M_ADDR_BIT_OFFSET = $clog2(M_STRB_W);
+localparam S_BYTE_LANES = S_STRB_W;
+localparam M_BYTE_LANES = M_STRB_W;
+localparam S_BYTE_W = S_DATA_W/S_BYTE_LANES;
+localparam M_BYTE_W = M_DATA_W/M_BYTE_LANES;
+localparam S_ADDR_MASK = {ADDR_W{1'b1}} << S_ADDR_BIT_OFFSET;
+localparam M_ADDR_MASK = {ADDR_W{1'b1}} << M_ADDR_BIT_OFFSET;
+
+// check configuration
+if (S_BYTE_W * S_STRB_W != S_DATA_W)
+    $fatal(0, "Error: APB slave interface data width not evenly divisible (instance %m)");
+
+if (M_BYTE_W * M_STRB_W != M_DATA_W)
+    $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)");
+
+if (S_BYTE_W != M_BYTE_W)
+    $fatal(0, "Error: byte size mismatch (instance %m)");
+
+if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES)
+    $fatal(0, "Error: APB slave interface byte lane count must be even power of two (instance %m)");
+
+if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES)
+    $fatal(0, "Error: APB master interface byte lane count must be even power of two (instance %m)");
+
+if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
+    // same width; bypass
+
+    assign m_apb.paddr = s_apb.paddr;
+    assign m_apb.pprot = s_apb.pprot;
+    assign m_apb.psel = s_apb.psel;
+    assign m_apb.penable = s_apb.penable;
+    assign m_apb.pwrite = s_apb.pwrite;
+    assign m_apb.pwdata = s_apb.pwdata;
+    assign m_apb.pstrb = s_apb.pstrb;
+    assign s_apb.pready = m_apb.pready;
+    assign s_apb.prdata = m_apb.prdata;
+    assign s_apb.pslverr = m_apb.pslverr;
+    assign m_apb.pauser = PAUSER_EN ? s_apb.pauser : '0;
+    assign m_apb.pwuser = PWUSER_EN ? s_apb.pwuser : '0;
+    assign s_apb.pruser = PRUSER_EN ? m_apb.pruser : '0;
+    assign s_apb.pbuser = PBUSER_EN ? m_apb.pbuser : '0;
+
+end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
+    // output is wider; upsize
+
+    localparam [0:0]
+        STATE_IDLE = 1'd0,
+        STATE_DATA = 1'd1;
+
+    logic [0:0] state_reg = STATE_IDLE, state_next;
+
+    logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
+    logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
+    logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
+    logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
+    logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
+
+    logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
+    logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
+    logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
+    logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
+    logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
+    logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
+    logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
+    logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
+    logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
+
+    assign s_apb.pready = s_apb_pready_reg;
+    assign s_apb.prdata = s_apb_prdata_reg;
+    assign s_apb.pslverr = s_apb_pslverr_reg;
+    assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+    assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+    assign m_apb.paddr = m_apb_paddr_reg;
+    assign m_apb.pprot = m_apb_pprot_reg;
+    assign m_apb.psel = m_apb_psel_reg;
+    assign m_apb.penable = m_apb_penable_reg;
+    assign m_apb.pwrite = m_apb_pwrite_reg;
+    assign m_apb.pwdata = m_apb_pwdata_reg;
+    assign m_apb.pstrb = m_apb_pstrb_reg;
+    assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+
+    always_comb begin
+        state_next = STATE_IDLE;
+
+        s_apb_pready_next = 1'b0;
+        s_apb_prdata_next = s_apb_prdata_reg;
+        s_apb_pslverr_next = s_apb_pslverr_reg;
+        s_apb_pruser_next = s_apb_pruser_reg;
+        s_apb_pbuser_next = s_apb_pbuser_reg;
+
+        m_apb_paddr_next = m_apb_paddr_reg;
+        m_apb_pprot_next = m_apb_pprot_reg;
+        m_apb_psel_next = 1'b0;
+        m_apb_penable_next = 1'b0;
+        m_apb_pwrite_next = m_apb_pwrite_reg;
+        m_apb_pwdata_next = m_apb_pwdata_reg;
+        m_apb_pstrb_next = m_apb_pstrb_reg;
+        m_apb_pauser_next = m_apb_pauser_reg;
+        m_apb_pwuser_next = m_apb_pwuser_reg;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                m_apb_paddr_next = s_apb.paddr;
+                m_apb_pprot_next = s_apb.pprot;
+                m_apb_pwrite_next = s_apb.pwrite;
+                m_apb_pwdata_next = {(M_BYTE_LANES/S_BYTE_LANES){s_apb.pwdata}};
+                m_apb_pstrb_next = '0;
+                m_apb_pstrb_next[s_apb.paddr[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_STRB_W +: S_STRB_W] = s_apb.pstrb;
+                m_apb_pauser_next = s_apb.pauser;
+                m_apb_pwuser_next = s_apb.pwuser;
+
+                if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
+                    m_apb_psel_next = 1'b1;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_apb_psel_next = 1'b1;
+                m_apb_penable_next = 1'b1;
+
+                s_apb_pready_next = 1'b0;
+                s_apb_prdata_next = m_apb.prdata[m_apb_paddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W];
+                s_apb_pslverr_next = m_apb.pslverr;
+                s_apb_pruser_next = m_apb.pruser;
+                s_apb_pbuser_next = m_apb.pbuser;
+
+                if (m_apb.psel && m_apb.penable && m_apb.pready) begin
+                    m_apb_psel_next = 1'b0;
+                    m_apb_penable_next = 1'b0;
+                    s_apb_pready_next = 1'b1;
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+
+    always_ff @(posedge clk) begin
+        state_reg <= state_next;
+
+        s_apb_pready_reg <= s_apb_pready_next;
+        s_apb_prdata_reg <= s_apb_prdata_next;
+        s_apb_pslverr_reg <= s_apb_pslverr_next;
+        s_apb_pruser_reg <= s_apb_pruser_next;
+        s_apb_pbuser_reg <= s_apb_pbuser_next;
+
+        m_apb_paddr_reg <= m_apb_paddr_next;
+        m_apb_pprot_reg <= m_apb_pprot_next;
+        m_apb_psel_reg <= m_apb_psel_next;
+        m_apb_penable_reg <= m_apb_penable_next;
+        m_apb_pwrite_reg <= m_apb_pwrite_next;
+        m_apb_pwdata_reg <= m_apb_pwdata_next;
+        m_apb_pstrb_reg <= m_apb_pstrb_next;
+        m_apb_pauser_reg <= m_apb_pauser_next;
+        m_apb_pwuser_reg <= m_apb_pwuser_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+
+            s_apb_pready_reg <= 1'b0;
+
+            m_apb_psel_reg <= 1'b0;
+            m_apb_penable_reg <= 1'b0;
+        end
+    end
+
+end else begin : downsize
+    // output is narrower; downsize
+
+    // output bus is wider
+    localparam DATA_W = S_DATA_W;
+    localparam STRB_W = S_STRB_W;
+    // required number of segments in wider bus
+    localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
+    localparam SEG_COUNT_W = $clog2(SEG_COUNT);
+    // data width and keep width per segment
+    localparam SEG_DATA_W = DATA_W / SEG_COUNT;
+    localparam SEG_STRB_W = STRB_W / SEG_COUNT;
+
+    localparam [0:0]
+        STATE_IDLE = 1'd0,
+        STATE_DATA = 1'd1;
+
+    logic [0:0] state_reg = STATE_IDLE, state_next;
+
+    logic [DATA_W-1:0] data_reg = '0, data_next;
+    logic [STRB_W-1:0] strb_reg = '0, strb_next;
+
+    logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
+
+    logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
+    logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
+    logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
+    logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
+    logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
+
+    logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
+    logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
+    logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
+    logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
+    logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
+    logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
+    logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
+    logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
+    logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
+
+    assign s_apb.pready = s_apb_pready_reg;
+    assign s_apb.prdata = s_apb_prdata_reg;
+    assign s_apb.pslverr = s_apb_pslverr_reg;
+    assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+    assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+    assign m_apb.paddr = m_apb_paddr_reg;
+    assign m_apb.pprot = m_apb_pprot_reg;
+    assign m_apb.psel = m_apb_psel_reg;
+    assign m_apb.penable = m_apb_penable_reg;
+    assign m_apb.pwrite = m_apb_pwrite_reg;
+    assign m_apb.pwdata = m_apb_pwdata_reg;
+    assign m_apb.pstrb = m_apb_pstrb_reg;
+    assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+
+    always_comb begin
+        state_next = STATE_IDLE;
+
+        data_next = data_reg;
+        strb_next = strb_reg;
+
+        current_seg_next = current_seg_reg;
+
+        s_apb_pready_next = 1'b0;
+        s_apb_prdata_next = s_apb_prdata_reg;
+        s_apb_pslverr_next = s_apb_pslverr_reg;
+        s_apb_pruser_next = s_apb_pruser_reg;
+        s_apb_pbuser_next = s_apb_pbuser_reg;
+
+        m_apb_paddr_next = m_apb_paddr_reg;
+        m_apb_pprot_next = m_apb_pprot_reg;
+        m_apb_psel_next = 1'b0;
+        m_apb_penable_next = 1'b0;
+        m_apb_pwrite_next = m_apb_pwrite_reg;
+        m_apb_pwdata_next = m_apb_pwdata_reg;
+        m_apb_pstrb_next = m_apb_pstrb_reg;
+        m_apb_pauser_next = m_apb_pauser_reg;
+        m_apb_pwuser_next = m_apb_pwuser_reg;
+
+        case (state_reg)
+            STATE_IDLE: begin
+                current_seg_next = s_apb.paddr[M_ADDR_BIT_OFFSET +: SEG_COUNT_W];
+
+                m_apb_paddr_next = s_apb.paddr;
+                m_apb_pprot_next = s_apb.pprot;
+                m_apb_pwrite_next = s_apb.pwrite;
+                data_next = s_apb.pwdata;
+                strb_next = s_apb.pstrb;
+                m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
+                m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
+                m_apb_pauser_next = s_apb.pauser;
+                m_apb_pwuser_next = s_apb.pwuser;
+
+                s_apb_pslverr_next = 1'b0;
+
+                if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
+                    m_apb_psel_next = 1'b1;
+                    state_next = STATE_DATA;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_DATA: begin
+                m_apb_psel_next = 1'b1;
+                m_apb_penable_next = 1'b1;
+
+                s_apb_pready_next = 1'b0;
+                s_apb_prdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_apb.prdata;
+                if (m_apb.pslverr) begin
+                    s_apb_pslverr_next = 1'b1;
+                end
+                s_apb_pruser_next = m_apb.pruser;
+                s_apb_pbuser_next = m_apb.pbuser;
+
+                if (m_apb.psel && m_apb.penable && m_apb.pready) begin
+                    m_apb_penable_next = 1'b0;
+                    current_seg_next = current_seg_reg + 1;
+                    m_apb_paddr_next = (m_apb_paddr_reg & M_ADDR_MASK) + SEG_STRB_W;
+                    m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
+                    m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
+                    if (current_seg_reg == SEG_COUNT_W'(SEG_COUNT-1)) begin
+                        m_apb_psel_next = 1'b0;
+                        s_apb_pready_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        state_next = STATE_DATA;
+                    end
+                end else begin
+                    state_next = STATE_DATA;
+                end
+            end
+        endcase
+    end
+
+    always_ff @(posedge clk) begin
+        state_reg <= state_next;
+
+        data_reg <= data_next;
+        strb_reg <= strb_next;
+
+        current_seg_reg <= current_seg_next;
+
+        s_apb_pready_reg <= s_apb_pready_next;
+        s_apb_prdata_reg <= s_apb_prdata_next;
+        s_apb_pslverr_reg <= s_apb_pslverr_next;
+        s_apb_pruser_reg <= s_apb_pruser_next;
+        s_apb_pbuser_reg <= s_apb_pbuser_next;
+
+        m_apb_paddr_reg <= m_apb_paddr_next;
+        m_apb_pprot_reg <= m_apb_pprot_next;
+        m_apb_psel_reg <= m_apb_psel_next;
+        m_apb_penable_reg <= m_apb_penable_next;
+        m_apb_pwrite_reg <= m_apb_pwrite_next;
+        m_apb_pwdata_reg <= m_apb_pwdata_next;
+        m_apb_pstrb_reg <= m_apb_pstrb_next;
+        m_apb_pauser_reg <= m_apb_pauser_next;
+        m_apb_pwuser_reg <= m_apb_pwuser_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+
+            s_apb_pready_reg <= 1'b0;
+
+            m_apb_psel_reg <= 1'b0;
+            m_apb_penable_reg <= 1'b0;
+        end
+    end
+
+end
+
+endmodule
+
+`resetall

src/apb/rtl/taxi_apb_interconnect.sv

@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB interconnect
+ */
+module taxi_apb_interconnect #
+(
+    // Number of downstream APB interfaces
+    parameter M_CNT = 4,
+    // Width of address decoder in bits
+    parameter ADDR_W = 16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_CNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_CNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_CNT bits
+    parameter M_SECURE = {M_CNT{1'b0}}
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * APB slave interface
+     */
+    taxi_apb_if.slv                 s_apb,
+
+    /*
+     * APB master interface
+     */
+    taxi_apb_if.mst                 m_apb[M_CNT]
+);
+
+// extract parameters
+localparam DATA_W = s_apb.DATA_W;
+localparam S_ADDR_W = s_apb.ADDR_W;
+localparam STRB_W = s_apb.STRB_W;
+localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb[0].PAUSER_EN;
+localparam PAUSER_W = s_apb.PAUSER_W;
+localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb[0].PWUSER_EN;
+localparam PWUSER_W = s_apb.PWUSER_W;
+localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb[0].PRUSER_EN;
+localparam PRUSER_W = s_apb.PRUSER_W;
+localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb[0].PBUSER_EN;
+localparam PBUSER_W = s_apb.PBUSER_W;
+
+localparam APB_M_ADDR_W = m_apb[0].ADDR_W;
+
+localparam CL_M_CNT = $clog2(M_CNT);
+localparam CL_M_CNT_INT = CL_M_CNT > 0 ? CL_M_CNT : 1;
+
+localparam [M_CNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_CNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_CNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_CNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_CNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_apb.ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_apb[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_apb[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for apb_interconnect instance %m");
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_CNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_CNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+logic [CL_M_CNT_INT-1:0] sel_reg = '0;
+logic act_reg = 1'b0;
+
+logic s_apb_pready_reg = 1'b0;
+logic [DATA_W-1:0] s_apb_prdata_reg = '0;
+logic s_apb_pslverr_reg = 1'b0;
+logic [PRUSER_W-1:0] s_apb_pruser_reg = '0;
+logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0;
+
+logic [ADDR_W-1:0] m_apb_paddr_reg = '0;
+logic [2:0] m_apb_pprot_reg = '0;
+logic [M_CNT-1:0] m_apb_psel_reg = '0;
+logic m_apb_penable_reg = 1'b0;
+logic m_apb_pwrite_reg = 1'b0;
+logic [DATA_W-1:0] m_apb_pwdata_reg = '0;
+logic [STRB_W-1:0] m_apb_pstrb_reg = '0;
+logic [PAUSER_W-1:0] m_apb_pauser_reg = '0;
+logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0;
+
+wire [M_CNT-1:0] m_apb_pready;
+wire [DATA_W-1:0] m_apb_prdata[M_CNT];
+wire m_apb_pslverr[M_CNT];
+wire [PRUSER_W-1:0] m_apb_pruser[M_CNT];
+wire [PBUSER_W-1:0] m_apb_pbuser[M_CNT];
+
+assign s_apb.pready = s_apb_pready_reg;
+assign s_apb.prdata = s_apb_prdata_reg;
+assign s_apb.pslverr = s_apb_pslverr_reg;
+assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
+assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
+
+for (genvar n = 0; n < M_CNT; n += 1) begin
+    assign m_apb[n].paddr = APB_M_ADDR_W'(m_apb_paddr_reg);
+    assign m_apb[n].pprot = m_apb_pprot_reg;
+    assign m_apb[n].psel = m_apb_psel_reg[n];
+    assign m_apb[n].penable = m_apb_penable_reg;
+    assign m_apb[n].pwrite = m_apb_pwrite_reg;
+    assign m_apb[n].pwdata = m_apb_pwdata_reg;
+    assign m_apb[n].pstrb = m_apb_pstrb_reg;
+    assign m_apb_pready[n] = m_apb[n].pready;
+    assign m_apb_prdata[n] = m_apb[n].prdata;
+    assign m_apb_pslverr[n] = m_apb[n].pslverr;
+    assign m_apb[n].pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
+    assign m_apb[n].pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
+    assign m_apb_pruser[n] = m_apb[n].pruser;
+    assign m_apb_pbuser[n] = m_apb[n].pbuser;
+end
+
+always_ff @(posedge clk) begin
+    s_apb_pready_reg <= 1'b0;
+    m_apb_penable_reg <= act_reg && s_apb.penable;
+
+    s_apb_prdata_reg <= m_apb_prdata[sel_reg];
+    s_apb_pslverr_reg <= m_apb_pslverr[sel_reg] | (m_apb_psel_reg == 0);
+    s_apb_pruser_reg <= m_apb_pruser[sel_reg];
+    s_apb_pbuser_reg <= m_apb_pbuser[sel_reg];
+
+    if ((m_apb_psel_reg & ~m_apb_pready) == 0) begin
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+        s_apb_pready_reg <= act_reg;
+        act_reg <= 1'b0;
+    end
+
+    if (!act_reg) begin
+        m_apb_paddr_reg <= s_apb.paddr;
+        m_apb_pprot_reg <= s_apb.pprot;
+        m_apb_pwrite_reg <= s_apb.pwrite;
+        m_apb_pwdata_reg <= s_apb.pwdata;
+        m_apb_pstrb_reg <= s_apb.pstrb;
+        m_apb_pauser_reg <= s_apb.pauser;
+        m_apb_pwuser_reg <= s_apb.pwuser;
+
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+
+        if (s_apb.psel && s_apb.penable && !s_apb_pready_reg) begin
+            act_reg <= 1'b1;
+            for (integer i = 0; i < M_CNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_apb.pprot[1]) && (s_apb.paddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        sel_reg <= CL_M_CNT_INT'(i);
+                        m_apb_psel_reg[i] <= 1'b1;
+                    end
+                end
+            end
+        end
+    end
+
+    if (rst) begin
+        act_reg <= 1'b0;
+        s_apb_pready_reg <= 1'b0;
+        m_apb_psel_reg <= '0;
+        m_apb_penable_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/apb/tb/taxi_apb_adapter/Makefile

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_apb_adapter
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_ADDR_W := 32
+export PARAM_S_DATA_W := 32
+export PARAM_S_STRB_W := $(shell expr $(PARAM_S_DATA_W) / 8 )
+export PARAM_M_DATA_W := 32
+export PARAM_M_STRB_W := $(shell expr $(PARAM_M_DATA_W) / 8 )
+export PARAM_PAUSER_EN := 0
+export PARAM_PAUSER_W := 1
+export PARAM_PWUSER_EN := 0
+export PARAM_PWUSER_W := 1
+export PARAM_PBUSER_EN := 0
+export PARAM_PBUSER_W := 1
+export PARAM_PRUSER_EN := 0
+export PARAM_PRUSER_W := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.py

@@ -0,0 +1,237 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import ApbBus, ApbMaster, ApbRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
+        self.apb_ram = ApbRam(ApbBus.from_entity(dut.m_apb), dut.clk, dut.rst, size=2**16)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.apb_master.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.apb_ram.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram.write(addr-128, b'\xaa'*(length+256))
+
+            await tb.apb_master.write(addr, test_data)
+
+            tb.log.debug("%s", tb.apb_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.apb_ram.read(addr, length) == test_data
+            assert tb.apb_ram.read(addr-1, 1) == b'\xaa'
+            assert tb.apb_ram.read(addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram.write(addr, test_data)
+
+            data = await tb.apb_master.read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length)
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.apb_master, k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("m_data_w", [8, 16, 32])
+@pytest.mark.parametrize("s_data_w", [8, 16, 32])
+def test_taxi_apb_adapter(request, s_data_w, m_data_w):
+    dut = "taxi_apb_adapter"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_apb_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['ADDR_W'] = 32
+    parameters['S_DATA_W'] = s_data_w
+    parameters['S_STRB_W'] = parameters['S_DATA_W'] // 8
+    parameters['M_DATA_W'] = m_data_w
+    parameters['M_STRB_W'] = parameters['M_DATA_W'] // 8
+    parameters["PAUSER_EN"] = 0
+    parameters["PAUSER_W"] = 1
+    parameters["PWUSER_EN"] = 0
+    parameters["PWUSER_W"] = 1
+    parameters["PRUSER_EN"] = 0
+    parameters["PRUSER_W"] = 1
+    parameters["PBUSER_EN"] = 0
+    parameters["PBUSER_W"] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB width adapter testbench
+ */
+module test_taxi_apb_adapter #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter ADDR_W = 32,
+    parameter S_DATA_W = 32,
+    parameter S_STRB_W = (S_DATA_W/8),
+    parameter M_DATA_W = 32,
+    parameter M_STRB_W = (M_DATA_W/8),
+    parameter logic PAUSER_EN = 1'b0,
+    parameter PAUSER_W = 1,
+    parameter logic PWUSER_EN = 1'b0,
+    parameter PWUSER_W = 1,
+    parameter logic PRUSER_EN = 1'b0,
+    parameter PRUSER_W = 1,
+    parameter logic PBUSER_EN = 1'b0,
+    parameter PBUSER_W = 1
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_apb_if #(
+    .DATA_W(S_DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(S_STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) s_apb();
+
+taxi_apb_if #(
+    .DATA_W(M_DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(M_STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) m_apb();
+
+taxi_apb_adapter
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * APB slave interface
+     */
+    .s_apb(s_apb),
+
+    /*
+     * APB master interface
+     */
+    .m_apb(m_apb)
+);
+
+endmodule
+
+`resetall

src/apb/tb/taxi_apb_interconnect/Makefile

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_apb_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_M_CNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_PAUSER_EN := 0
+export PARAM_PAUSER_W := 1
+export PARAM_PWUSER_EN := 0
+export PARAM_PWUSER_W := 1
+export PARAM_PBUSER_EN := 0
+export PARAM_PBUSER_W := 1
+export PARAM_PRUSER_EN := 0
+export PARAM_PRUSER_W := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.py

@@ -0,0 +1,259 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb
+import cocotb_test.simulator
+import pytest
+from cocotb.clock import Clock
+from cocotb.regression import TestFactory
+from cocotb.triggers import RisingEdge, Timer
+from cocotbext.axi import ApbBus, ApbMaster, ApbRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
+        self.apb_ram = [
+            ApbRam(ApbBus.from_entity(ch), dut.clk, dut.rst, size=2**16)
+            for ch in dut.m_apb
+        ]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.apb_master.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for ram in self.apb_ram:
+                ram.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+):
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes * 2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset + 0x1000
+            addr = ram_addr + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram[m].write(ram_addr - 128, b"\xaa" * (length + 256))
+
+            await tb.apb_master.write(addr, test_data)
+
+            tb.log.debug(
+                "%s",
+                tb.apb_ram[m].hexdump_str(
+                    (ram_addr & ~0xF) - 16,
+                    (((ram_addr & 0xF) + length - 1) & ~0xF) + 48,
+                ),
+            )
+
+            assert tb.apb_ram[m].read(ram_addr, length) == test_data
+            assert tb.apb_ram[m].read(ram_addr - 1, 1) == b"\xaa"
+            assert tb.apb_ram[m].read(ram_addr + length, 1) == b"\xaa"
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(
+    dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
+):
+    tb = TB(dut)
+
+    byte_lanes = tb.apb_master.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes * 2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset + 0x1000
+            addr = ram_addr + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.apb_ram[m].write(ram_addr, test_data)
+
+            data = await tb.apb_master.read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.apb_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset + random.randint(0, aperture - length) + m * 0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), "ns")
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), "ns")
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(
+            cocotb.start_soon(
+                worker(
+                    tb.apb_master,
+                    k * 0x1000,
+                    0x1000,
+                    count=16,
+                )
+            )
+        )
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, "top", None) is not None:
+    m_cnt = len(cocotb.top.m_apb)
+
+    for test in [run_test_write, run_test_read]:
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("m", range(min(m_cnt, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "rtl"))
+lib_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "lib"))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, "taxi", "src"))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == ".f":
+            with open(f, "r") as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_cnt", [1, 4])
+def test_taxi_apb_interconnect(request, m_cnt, data_w):
+    dut = "taxi_apb_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_apb_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters["M_CNT"] = m_cnt
+    parameters["DATA_W"] = data_w
+    parameters["ADDR_W"] = 32
+    parameters["STRB_W"] = parameters["DATA_W"] // 8
+    parameters["PAUSER_EN"] = 0
+    parameters["PAUSER_W"] = 1
+    parameters["PWUSER_EN"] = 0
+    parameters["PWUSER_W"] = 1
+    parameters["PRUSER_EN"] = 0
+    parameters["PRUSER_W"] = 1
+    parameters["PBUSER_EN"] = 0
+    parameters["PBUSER_W"] = 1
+
+    extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(
+        tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
+    )
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.sv

@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * APB interconnect testbench
+ */
+module test_taxi_apb_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter M_CNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic PAUSER_EN = 1'b0,
+    parameter PAUSER_W = 1,
+    parameter logic PWUSER_EN = 1'b0,
+    parameter PWUSER_W = 1,
+    parameter logic PRUSER_EN = 1'b0,
+    parameter PRUSER_W = 1,
+    parameter logic PBUSER_EN = 1'b0,
+    parameter PBUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
+    parameter M_SECURE = {M_CNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_apb_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .PAUSER_EN(PAUSER_EN),
+    .PAUSER_W(PAUSER_W),
+    .PWUSER_EN(PWUSER_EN),
+    .PWUSER_W(PWUSER_W),
+    .PRUSER_EN(PRUSER_EN),
+    .PRUSER_W(PRUSER_W),
+    .PBUSER_EN(PBUSER_EN),
+    .PBUSER_W(PBUSER_W)
+) s_apb(), m_apb[M_CNT]();
+
+taxi_apb_interconnect #(
+    .M_CNT(M_CNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * APB slave interface
+     */
+    .s_apb(s_apb),
+
+    /*
+     * APB master interface
+     */
+    .m_apb(m_apb)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar.f

@@ -0,0 +1,3 @@
+taxi_axi_crossbar.sv
+taxi_axi_crossbar_wr.f
+taxi_axi_crossbar_rd.f

src/axi/rtl/taxi_axi_crossbar.sv

@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar
+ */
+module taxi_axi_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT],
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+taxi_axi_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE (S_W_REG_TYPE),
+    .S_B_REG_TYPE (S_B_REG_TYPE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_wr(s_axi_wr),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_wr(m_axi_wr)
+);
+
+taxi_axi_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE (S_R_REG_TYPE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI slave interfaces
+     */
+    .s_axi_rd(s_axi_rd),
+
+    /*
+     * AXI master interfaces
+     */
+    .m_axi_rd(m_axi_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_addr.sv

@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar address decode and admission control
+ */
+module taxi_axi_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Select signal width
+    parameter SEL_W = $clog2(M_COUNT),
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // ID field width
+    parameter ID_W = 8,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs
+    parameter S_THREADS = 32'd2,
+    // Number of concurrent operations
+    parameter S_ACCEPT = 32'd16,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * Address input
+     */
+    input  wire logic [ID_W-1:0]    s_axi_aid,
+    input  wire logic [ADDR_W-1:0]  s_axi_aaddr,
+    input  wire logic [2:0]         s_axi_aprot,
+    input  wire logic [3:0]         s_axi_aqos,
+    input  wire logic               s_axi_avalid,
+    output wire logic               s_axi_aready,
+
+    /*
+     * Address output
+     */
+    output wire logic [3:0]         m_axi_aregion,
+    output wire logic [SEL_W-1:0]   m_select,
+    output wire logic               m_axi_avalid,
+    input  wire logic               m_axi_aready,
+
+    /*
+     * Write command output
+     */
+    output wire logic [SEL_W-1:0]   m_wc_select,
+    output wire logic               m_wc_decerr,
+    output wire logic               m_wc_valid,
+    input  wire logic               m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire logic               m_rc_decerr,
+    output wire logic               m_rc_valid,
+    input  wire logic               m_rc_ready,
+
+    /*
+     * Completion input
+     */
+    input  wire logic [ID_W-1:0]    s_cpl_id,
+    input  wire logic               s_cpl_valid
+);
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+localparam S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS;
+localparam CL_S_INT_THREADS = $clog2(S_INT_THREADS);
+localparam CL_S_ACCEPT = $clog2(S_ACCEPT);
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (M_REGIONS < 1 || M_REGIONS > 16)
+    $fatal(0, "Error: M_REGIONS must be between 1 and 16 (instance %m)");
+
+if (S_ACCEPT < 1)
+    $fatal(0, "Error: need at least 1 accept (instance %m)");
+
+if (S_THREADS < 1)
+    $fatal(0, "Error: need at least 1 thread (instance %m)");
+
+initial begin
+    if (S_THREADS > S_ACCEPT) begin
+        $warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)");
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < 12 || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+    end
+
+    $display("Addressing configuration for axi_crossbar_addr instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [0:0]
+    STATE_IDLE = 1'd0,
+    STATE_DECODE = 1'd1;
+
+logic [0:0] state_reg = STATE_IDLE, state_next;
+
+logic s_axi_aready_reg = 1'b0, s_axi_aready_next;
+
+logic [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;
+logic [SEL_W-1:0] m_select_reg = '0, m_select_next;
+logic m_axi_avalid_reg = 1'b0, m_axi_avalid_next;
+logic m_decerr_reg = 1'b0, m_decerr_next;
+logic m_wc_valid_reg = 1'b0, m_wc_valid_next;
+logic m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axi_aready = s_axi_aready_reg;
+
+assign m_axi_aregion = m_axi_aregion_reg;
+assign m_select = m_select_reg;
+assign m_axi_avalid = m_axi_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+logic match;
+logic trans_start;
+logic trans_complete;
+
+localparam TR_CNT_W = $clog2(S_ACCEPT+1);
+logic [TR_CNT_W-1:0] trans_count_reg = 0;
+wire trans_limit = trans_count_reg >= TR_CNT_W'(S_ACCEPT) && !trans_complete;
+
+// transfer ID thread tracking
+logic [ID_W-1:0] thread_id_reg[S_INT_THREADS-1:0];
+logic [SEL_W-1:0] thread_m_reg[S_INT_THREADS-1:0];
+logic [3:0] thread_region_reg[S_INT_THREADS-1:0];
+logic [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0];
+
+// TODO fix loop
+/* verilator lint_off UNOPTFLAT */
+wire [S_INT_THREADS-1:0] thread_active;
+wire [S_INT_THREADS-1:0] thread_match;
+wire [S_INT_THREADS-1:0] thread_match_dest;
+wire [S_INT_THREADS-1:0] thread_cpl_match;
+wire [S_INT_THREADS-1:0] thread_trans_start;
+wire [S_INT_THREADS-1:0] thread_trans_complete;
+
+for (genvar n = 0; n < S_INT_THREADS; n = n + 1) begin
+    initial begin
+        thread_count_reg[n] = '0;
+    end
+
+    assign thread_active[n] = thread_count_reg[n] != 0;
+    assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid;
+    assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next);
+    assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id;
+    assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && thread_match == 0 && (thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))) == 0)) && trans_start;
+    assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (thread_trans_start[n]) begin
+            thread_id_reg[n] <= s_axi_aid;
+            thread_m_reg[n] <= m_select_next;
+            thread_region_reg[n] <= m_axi_aregion_next;
+        end
+
+        if (thread_trans_start[n] && !thread_trans_complete[n]) begin
+            thread_count_reg[n] <= thread_count_reg[n] + 1;
+        end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin
+            thread_count_reg[n] <= thread_count_reg[n] - 1;
+        end
+
+        if (rst) begin
+            thread_count_reg[n] <= 0;
+        end
+    end
+end
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+    trans_start = 1'b0;
+    trans_complete = 1'b0;
+
+    s_axi_aready_next = 1'b0;
+
+    m_axi_aregion_next = m_axi_aregion_reg;
+    m_select_next = m_select_reg;
+    m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axi_aready_next = 1'b0;
+
+            if (s_axi_avalid && !s_axi_aready) begin
+                match = 1'b0;
+                for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                    for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_axi_aprot[1]) && M_CONNECT_INT[i][S] && (s_axi_aaddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                            m_select_next = SEL_W'(i);
+                            m_axi_aregion_next = 4'(j);
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    if (!trans_limit && (thread_match_dest != 0 || (!(&thread_active) && thread_match == 0))) begin
+                        // transaction limit not reached
+                        m_axi_avalid_next = 1'b1;
+                        m_decerr_next = 1'b0;
+                        m_wc_valid_next = WC_OUTPUT;
+                        m_rc_valid_next = 1'b0;
+                        trans_start = 1'b1;
+                        state_next = STATE_DECODE;
+                    end else begin
+                        // transaction limit reached; block in idle
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    // decode error
+                    m_axi_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axi_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+
+    // manage completions
+    trans_complete = s_cpl_valid;
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+    s_axi_aready_reg <= s_axi_aready_next;
+    m_axi_avalid_reg <= m_axi_avalid_next;
+    m_wc_valid_reg <= m_wc_valid_next;
+    m_rc_valid_reg <= m_rc_valid_next;
+
+    if (trans_start && !trans_complete) begin
+        trans_count_reg <= trans_count_reg + 1;
+    end else if (!trans_start && trans_complete) begin
+        trans_count_reg <= trans_count_reg - 1;
+    end
+
+    m_axi_aregion_reg <= m_axi_aregion_next;
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axi_aready_reg <= 1'b0;
+        m_axi_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+
+        trans_count_reg <= 0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_rd.f

@@ -0,0 +1,6 @@
+taxi_axi_crossbar_rd.sv
+taxi_axi_crossbar_addr.sv
+taxi_axi_register_rd.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_crossbar_rd.sv

@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (read)
+ */
+module taxi_axi_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_rd[0].DATA_W;
+localparam S_ADDR_W = s_axi_rd[0].ADDR_W;
+localparam STRB_W = s_axi_rd[0].STRB_W;
+localparam S_ID_W = s_axi_rd[0].ID_W;
+localparam M_ID_W = m_axi_rd[0].ID_W;
+localparam logic ARUSER_EN = s_axi_rd[0].ARUSER_EN && m_axi_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
+localparam RUSER_W = s_axi_rd[0].RUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+localparam M_COUNT_P1 = M_COUNT+1;
+localparam CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+localparam [S_COUNT-1:0][31:0] S_THREADS_INT = S_THREADS;
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axi_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_ID_W < S_ID_W+$clog2(S_COUNT))
+    $fatal(0, "Error: M_ID_W must be at least $clog2(S_COUNT) larger than S_ID_W (instance %m)");
+
+wire [S_ID_W-1:0]    int_s_axi_arid[S_COUNT];
+wire [ADDR_W-1:0]    int_s_axi_araddr[S_COUNT];
+wire [7:0]           int_s_axi_arlen[S_COUNT];
+wire [2:0]           int_s_axi_arsize[S_COUNT];
+wire [1:0]           int_s_axi_arburst[S_COUNT];
+wire                 int_s_axi_arlock[S_COUNT];
+wire [3:0]           int_s_axi_arcache[S_COUNT];
+wire [2:0]           int_s_axi_arprot[S_COUNT];
+wire [3:0]           int_s_axi_arqos[S_COUNT];
+wire [3:0]           int_s_axi_arregion[S_COUNT];
+wire [ARUSER_W-1:0]  int_s_axi_aruser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_arvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_arready[M_COUNT];
+
+wire [M_ID_W-1:0]    int_m_axi_rid[M_COUNT];
+wire [DATA_W-1:0]    int_m_axi_rdata[M_COUNT];
+wire [1:0]           int_m_axi_rresp[M_COUNT];
+wire                 int_m_axi_rlast[M_COUNT];
+wire [RUSER_W-1:0]   int_m_axi_ruser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axi_rvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axi_rready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(s_axi_rd[0].DATA_W),
+        .ADDR_W(s_axi_rd[0].ADDR_W),
+        .STRB_W(s_axi_rd[0].STRB_W),
+        .ID_W(s_axi_rd[0].ID_W),
+        .ARUSER_EN(s_axi_rd[0].ARUSER_EN),
+        .ARUSER_W(s_axi_rd[0].ARUSER_W),
+        .RUSER_EN(s_axi_rd[0].RUSER_EN),
+        .RUSER_W(s_axi_rd[0].RUSER_W)
+    ) int_axi();
+
+    // S side register
+    taxi_axi_register_rd #(
+        .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+        .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_rd(s_axi_rd[m]),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_rd(int_axi)
+    );
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axi_avalid;
+    wire m_axi_aready;
+
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    wire [S_ID_W-1:0] s_cpl_id;
+    wire s_cpl_valid;
+
+    taxi_axi_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .ID_W(S_ID_W),
+        .S_THREADS(S_THREADS_INT[m]),
+        .S_ACCEPT(S_ACCEPT_INT[m]),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(0)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axi_aid(int_axi.arid),
+        .s_axi_aaddr(int_axi.araddr),
+        .s_axi_aprot(int_axi.arprot),
+        .s_axi_aqos(int_axi.arqos),
+        .s_axi_avalid(int_axi.arvalid),
+        .s_axi_aready(int_axi.arready),
+
+        /*
+         * Address output
+         */
+        .m_axi_aregion(int_s_axi_arregion[m]),
+        .m_select(a_select),
+        .m_axi_avalid(m_axi_avalid),
+        .m_axi_aready(m_axi_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(),
+        .m_wc_decerr(),
+        .m_wc_valid(),
+        .m_wc_ready(1'b1),
+
+        /*
+         * Response command output
+         */
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready),
+
+        /*
+         * Completion input
+         */
+        .s_cpl_id(s_cpl_id),
+        .s_cpl_valid(s_cpl_valid)
+    );
+
+    assign int_s_axi_arid[m] = int_axi.arid;
+    assign int_s_axi_araddr[m] = int_axi.araddr;
+    assign int_s_axi_arlen[m] = int_axi.arlen;
+    assign int_s_axi_arsize[m] = int_axi.arsize;
+    assign int_s_axi_arburst[m] = int_axi.arburst;
+    assign int_s_axi_arlock[m] = int_axi.arlock;
+    assign int_s_axi_arcache[m] = int_axi.arcache;
+    assign int_s_axi_arprot[m] = int_axi.arprot;
+    assign int_s_axi_arqos[m] = int_axi.arqos;
+    assign int_s_axi_aruser[m] = int_axi.aruser;
+
+    always_comb begin
+        int_axi_arvalid[m] = '0;
+        int_axi_arvalid[m][a_select] = m_axi_avalid;
+    end
+    assign m_axi_aready = int_axi_arready[a_select][m];
+
+    // decode error handling
+    logic [S_ID_W-1:0]  decerr_m_axi_rid_reg = '0, decerr_m_axi_rid_next;
+    logic               decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;
+    logic               decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;
+    wire                decerr_m_axi_rready;
+
+    logic [7:0] decerr_len_reg = 8'd0, decerr_len_next;
+
+    assign m_rc_ready = !decerr_m_axi_rvalid_reg;
+
+    always_comb begin
+        decerr_len_next = decerr_len_reg;
+        decerr_m_axi_rid_next = decerr_m_axi_rid_reg;
+        decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;
+        decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;
+
+        if (decerr_m_axi_rvalid_reg) begin
+            if (decerr_m_axi_rready) begin
+                if (decerr_len_reg != 0) begin
+                    decerr_len_next = decerr_len_reg-1;
+                    decerr_m_axi_rlast_next = (decerr_len_next == 0);
+                    decerr_m_axi_rvalid_next = 1'b1;
+                end else begin
+                    decerr_m_axi_rvalid_next = 1'b0;
+                end
+            end
+        end else if (m_rc_valid && m_rc_ready) begin
+            decerr_len_next = int_axi.arlen;
+            decerr_m_axi_rid_next = int_axi.arid;
+            decerr_m_axi_rlast_next = (decerr_len_next == 0);
+            decerr_m_axi_rvalid_next = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;
+        decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;
+        decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;
+        decerr_len_reg <= decerr_len_next;
+
+        if (rst) begin
+            decerr_m_axi_rvalid_reg <= 1'b0;
+        end
+    end
+
+    // read response arbitration
+    wire [M_COUNT_P1-1:0] r_req;
+    wire [M_COUNT_P1-1:0] r_ack;
+    wire [M_COUNT_P1-1:0] r_grant;
+    wire r_grant_valid;
+    wire [CL_M_COUNT_P1-1:0] r_grant_index;
+
+    taxi_arbiter #(
+        .PORTS(M_COUNT_P1),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    r_arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(r_req),
+        .ack(r_ack),
+        .grant(r_grant),
+        .grant_valid(r_grant_valid),
+        .grant_index(r_grant_index)
+    );
+
+    // read response mux
+    always_comb begin
+        if (r_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1)) begin
+            int_axi.rid    = decerr_m_axi_rid_reg;
+            int_axi.rdata  = '0;
+            int_axi.rresp  = 2'b11;
+            int_axi.rlast  = decerr_m_axi_rlast_reg;
+            int_axi.ruser  = '0;
+            int_axi.rvalid = decerr_m_axi_rvalid_reg & r_grant_valid;
+        end else begin
+            int_axi.rid    = S_ID_W'(int_m_axi_rid[r_grant_index[CL_M_COUNT_INT-1:0]]);
+            int_axi.rdata  = int_m_axi_rdata[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rresp  = int_m_axi_rresp[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rlast  = int_m_axi_rlast[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.ruser  = int_m_axi_ruser[r_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.rvalid = int_axi_rvalid[r_grant_index[CL_M_COUNT_INT-1:0]][m] & r_grant_valid;
+        end
+    end
+
+    always_comb begin
+        int_axi_rready[m] = '0;
+        int_axi_rready[m][r_grant_index[CL_M_COUNT_INT-1:0]] = r_grant_valid && int_axi.rready;
+    end
+
+    assign decerr_m_axi_rready = (r_grant_valid && int_axi.rready) && (r_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1));
+
+    for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+        assign r_req[n] = int_axi_rvalid[n][m] && !r_grant[n];
+        assign r_ack[n] = r_grant_valid && int_axi_rvalid[n][m] && int_axi.rlast && int_axi.rready;
+    end
+
+    assign r_req[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];
+    assign r_ack[M_COUNT_P1-1] = r_grant_valid && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && int_axi.rready;
+
+    assign s_cpl_id = int_axi.rid;
+    assign s_cpl_valid = int_axi.rvalid && int_axi.rready && int_axi.rlast;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(m_axi_rd[0].DATA_W),
+        .ADDR_W(m_axi_rd[0].ADDR_W),
+        .STRB_W(m_axi_rd[0].STRB_W),
+        .ID_W(m_axi_rd[0].ID_W),
+        .ARUSER_EN(m_axi_rd[0].ARUSER_EN),
+        .ARUSER_W(m_axi_rd[0].ARUSER_W),
+        .RUSER_EN(m_axi_rd[0].RUSER_EN),
+        .RUSER_W(m_axi_rd[0].RUSER_W)
+    ) int_axi();
+
+    // in-flight transaction count
+    wire trans_start;
+    wire trans_complete;
+    localparam TR_CNT_W = $clog2(M_ISSUE_INT[n]+1);
+    logic [TR_CNT_W-1:0] trans_count_reg = '0;
+
+    wire trans_limit = trans_count_reg >= TR_CNT_W'(M_ISSUE_INT[n]) && !trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            trans_count_reg <= 0;
+        end else begin
+            if (trans_start && !trans_complete) begin
+                trans_count_reg <= trans_count_reg + 1;
+            end else if (!trans_start && trans_complete) begin
+                trans_count_reg <= trans_count_reg - 1;
+            end
+        end
+    end
+
+    // address arbitration
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    if (S_COUNT > 1) begin
+        assign int_axi.arid = {a_grant_index, int_s_axi_arid[a_grant_index]};
+    end else begin
+        assign int_axi.arid = int_s_axi_arid[a_grant_index];
+    end
+    assign int_axi.araddr   = AXI_M_ADDR_W'(int_s_axi_araddr[a_grant_index]);
+    assign int_axi.arlen    = int_s_axi_arlen[a_grant_index];
+    assign int_axi.arsize   = int_s_axi_arsize[a_grant_index];
+    assign int_axi.arburst  = int_s_axi_arburst[a_grant_index];
+    assign int_axi.arlock   = int_s_axi_arlock[a_grant_index];
+    assign int_axi.arcache  = int_s_axi_arcache[a_grant_index];
+    assign int_axi.arprot   = int_s_axi_arprot[a_grant_index];
+    assign int_axi.arqos    = int_s_axi_arqos[a_grant_index];
+    assign int_axi.arregion = int_s_axi_arregion[a_grant_index];
+    assign int_axi.aruser   = int_s_axi_aruser[a_grant_index];
+    assign int_axi.arvalid  = int_axi_arvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axi_arready[n] = '0;
+        int_axi_arready[n][a_grant_index] = a_grant_valid && int_axi.arready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axi_arvalid[m][n] && !a_grant_valid && !trans_limit;
+        assign a_ack[m] = a_grant[m] && int_axi_arvalid[m][n] && int_axi.arready;
+    end
+
+    assign trans_start = int_axi.arvalid && int_axi.arready && a_grant_valid;
+
+    // read response forwarding
+    wire [CL_S_COUNT_INT-1:0] r_select = CL_S_COUNT_INT'(int_axi.rid >> S_ID_W);
+
+    assign int_m_axi_rid[n]   = int_axi.rid;
+    assign int_m_axi_rdata[n] = int_axi.rdata;
+    assign int_m_axi_rresp[n] = int_axi.rresp;
+    assign int_m_axi_rlast[n] = int_axi.rlast;
+    assign int_m_axi_ruser[n] = int_axi.ruser;
+
+    always_comb begin
+        int_axi_rvalid[n] = '0;
+        int_axi_rvalid[n][r_select] = int_axi.rvalid;
+    end
+    assign int_axi.rready = int_axi_rready[r_select][n];
+
+    assign trans_complete = int_axi.rvalid && int_axi.rready && int_axi.rlast;
+
+    // M side register
+    taxi_axi_register_rd #(
+        .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+        .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_rd(int_axi),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_rd(m_axi_rd[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_crossbar_wr.f

@@ -0,0 +1,6 @@
+taxi_axi_crossbar_wr.sv
+taxi_axi_crossbar_addr.sv
+taxi_axi_register_wr.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_crossbar_wr.sv

@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar (write)
+ */
+module taxi_axi_crossbar_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent unique IDs for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_wr[0].DATA_W;
+localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
+localparam STRB_W = s_axi_wr[0].STRB_W;
+localparam S_ID_W = s_axi_wr[0].ID_W;
+localparam M_ID_W = m_axi_wr[0].ID_W;
+localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
+localparam WUSER_W = s_axi_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
+localparam BUSER_W = s_axi_wr[0].BUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+localparam M_COUNT_P1 = M_COUNT+1;
+localparam CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
+
+localparam [S_COUNT-1:0][31:0] S_THREADS_INT = S_THREADS;
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axi_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_ID_W < S_ID_W+$clog2(S_COUNT))
+    $fatal(0, "Error: M_ID_W must be at least $clog2(S_COUNT) larger than S_ID_W (instance %m)");
+
+wire [S_ID_W-1:0]    int_s_axi_awid[S_COUNT];
+wire [ADDR_W-1:0]    int_s_axi_awaddr[S_COUNT];
+wire [7:0]           int_s_axi_awlen[S_COUNT];
+wire [2:0]           int_s_axi_awsize[S_COUNT];
+wire [1:0]           int_s_axi_awburst[S_COUNT];
+wire                 int_s_axi_awlock[S_COUNT];
+wire [3:0]           int_s_axi_awcache[S_COUNT];
+wire [2:0]           int_s_axi_awprot[S_COUNT];
+wire [3:0]           int_s_axi_awqos[S_COUNT];
+wire [3:0]           int_s_axi_awregion[S_COUNT];
+wire [AWUSER_W-1:0]  int_s_axi_awuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_awvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_awready[M_COUNT];
+
+wire [DATA_W-1:0]    int_s_axi_wdata[S_COUNT];
+wire [STRB_W-1:0]    int_s_axi_wstrb[S_COUNT];
+wire                 int_s_axi_wlast[S_COUNT];
+wire [WUSER_W-1:0]   int_s_axi_wuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axi_wvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axi_wready[M_COUNT];
+
+wire [M_ID_W-1:0]    int_m_axi_bid[M_COUNT];
+wire [1:0]           int_m_axi_bresp[M_COUNT];
+wire [BUSER_W-1:0]   int_m_axi_buser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axi_bvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axi_bready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(s_axi_wr[0].DATA_W),
+        .ADDR_W(s_axi_wr[0].ADDR_W),
+        .STRB_W(s_axi_wr[0].STRB_W),
+        .ID_W(s_axi_wr[0].ID_W),
+        .AWUSER_EN(s_axi_wr[0].AWUSER_EN),
+        .AWUSER_W(s_axi_wr[0].AWUSER_W),
+        .WUSER_EN(s_axi_wr[0].WUSER_EN),
+        .WUSER_W(s_axi_wr[0].WUSER_W),
+        .BUSER_EN(s_axi_wr[0].BUSER_EN),
+        .BUSER_W(s_axi_wr[0].BUSER_W)
+    ) int_axi();
+
+    // S side register
+    taxi_axi_register_wr #(
+        .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+        .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+        .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_wr(s_axi_wr[m]),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_wr(int_axi)
+    );
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axi_avalid;
+    wire m_axi_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_wc_select;
+    wire m_wc_decerr;
+    wire m_wc_valid;
+    wire m_wc_ready;
+
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    wire [S_ID_W-1:0] s_cpl_id;
+    wire s_cpl_valid;
+
+    taxi_axi_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .ID_W(S_ID_W),
+        .S_THREADS(S_THREADS_INT[m]),
+        .S_ACCEPT(S_ACCEPT_INT[m]),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(1)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axi_aid(int_axi.awid),
+        .s_axi_aaddr(int_axi.awaddr),
+        .s_axi_aprot(int_axi.awprot),
+        .s_axi_aqos(int_axi.awqos),
+        .s_axi_avalid(int_axi.awvalid),
+        .s_axi_aready(int_axi.awready),
+
+        /*
+         * Address output
+         */
+        .m_axi_aregion(int_s_axi_awregion[m]),
+        .m_select(a_select),
+        .m_axi_avalid(m_axi_avalid),
+        .m_axi_aready(m_axi_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(m_wc_select),
+        .m_wc_decerr(m_wc_decerr),
+        .m_wc_valid(m_wc_valid),
+        .m_wc_ready(m_wc_ready),
+
+        /*
+         * Response command output
+         */
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready),
+
+        /*
+         * Completion input
+         */
+        .s_cpl_id(s_cpl_id),
+        .s_cpl_valid(s_cpl_valid)
+    );
+
+    assign int_s_axi_awid[m] = int_axi.awid;
+    assign int_s_axi_awaddr[m] = int_axi.awaddr;
+    assign int_s_axi_awlen[m] = int_axi.awlen;
+    assign int_s_axi_awsize[m] = int_axi.awsize;
+    assign int_s_axi_awburst[m] = int_axi.awburst;
+    assign int_s_axi_awlock[m] = int_axi.awlock;
+    assign int_s_axi_awcache[m] = int_axi.awcache;
+    assign int_s_axi_awprot[m] = int_axi.awprot;
+    assign int_s_axi_awqos[m] = int_axi.awqos;
+    assign int_s_axi_awuser[m] = int_axi.awuser;
+
+    always_comb begin
+        int_axi_awvalid[m] = '0;
+        int_axi_awvalid[m][a_select] = m_axi_avalid;
+    end
+    assign m_axi_aready = int_axi_awready[a_select][m];
+
+    // write command handling
+    logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_drop_reg = 1'b0, w_drop_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+
+    assign m_wc_ready = !w_select_valid_reg;
+
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_drop_next = w_drop_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+        w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+
+        if (m_wc_valid && !w_select_valid_reg) begin
+            w_select_next = m_wc_select;
+            w_drop_next = m_wc_decerr;
+            w_select_valid_next = m_wc_valid;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_reg <= w_select_next;
+        w_drop_reg <= w_drop_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+        end
+    end
+
+    // write data forwarding
+    assign int_s_axi_wdata[m] = int_axi.wdata;
+    assign int_s_axi_wstrb[m] = int_axi.wstrb;
+    assign int_s_axi_wlast[m] = int_axi.wlast;
+    assign int_s_axi_wuser[m] = int_axi.wuser;
+
+    always_comb begin
+        int_axi_wvalid[m] = '0;
+        int_axi_wvalid[m][w_select_reg] = int_axi.wvalid && w_select_valid_reg && !w_drop_reg;
+    end
+    assign int_axi.wready = int_axi_wready[w_select_reg][m] || w_drop_reg;
+
+    // decode error handling
+    logic [S_ID_W-1:0]  decerr_m_axi_bid_reg = '0, decerr_m_axi_bid_next;
+    logic               decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;
+    wire                decerr_m_axi_bready;
+
+    assign m_rc_ready = !decerr_m_axi_bvalid_reg;
+
+    always_comb begin
+        decerr_m_axi_bid_next = decerr_m_axi_bid_reg;
+        decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;
+
+        if (decerr_m_axi_bvalid_reg) begin
+            if (decerr_m_axi_bready) begin
+                decerr_m_axi_bvalid_next = 1'b0;
+            end
+        end else if (m_rc_valid && m_rc_ready) begin
+            decerr_m_axi_bid_next = int_s_axi_awid[m];
+            decerr_m_axi_bvalid_next = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            decerr_m_axi_bvalid_reg <= 1'b0;
+        end else begin
+            decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;
+        end
+
+        decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;
+    end
+
+    // write response arbitration
+    wire [M_COUNT_P1-1:0] b_req;
+    wire [M_COUNT_P1-1:0] b_ack;
+    wire [M_COUNT_P1-1:0] b_grant;
+    wire b_grant_valid;
+    wire [CL_M_COUNT_P1-1:0] b_grant_index;
+
+    taxi_arbiter #(
+        .PORTS(M_COUNT_P1),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    b_arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(b_req),
+        .ack(b_ack),
+        .grant(b_grant),
+        .grant_valid(b_grant_valid),
+        .grant_index(b_grant_index)
+    );
+
+    // write response mux
+    always_comb begin
+        if (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1)) begin
+            int_axi.bid    = decerr_m_axi_bid_reg;
+            int_axi.bresp  = 2'b11;
+            int_axi.buser  = '0;
+            int_axi.bvalid = decerr_m_axi_bvalid_reg & b_grant_valid;
+        end else begin
+            int_axi.bid    = S_ID_W'(int_m_axi_bid[b_grant_index[CL_M_COUNT_INT-1:0]]);
+            int_axi.bresp  = int_m_axi_bresp[b_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.buser  = int_m_axi_buser[b_grant_index[CL_M_COUNT_INT-1:0]];
+            int_axi.bvalid = int_axi_bvalid[b_grant_index[CL_M_COUNT_INT-1:0]][m] & b_grant_valid;
+        end
+    end
+
+    always_comb begin
+        int_axi_bready[m] = '0;
+        int_axi_bready[m][b_grant_index[CL_M_COUNT_INT-1:0]] = b_grant_valid && int_axi.bready;
+    end
+
+    assign decerr_m_axi_bready = (b_grant_valid && int_axi.bready) && (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1));
+
+    for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+        assign b_req[n] = int_axi_bvalid[n][m] && !b_grant[n];
+        assign b_ack[n] = b_grant[n] && int_axi_bvalid[n][m] && int_axi.bready;
+    end
+
+    assign b_req[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
+    assign b_ack[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && int_axi.bready;
+
+    assign s_cpl_id = int_axi.bid;
+    assign s_cpl_valid = int_axi.bvalid && int_axi.bready;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axi_if #(
+        .DATA_W(m_axi_wr[0].DATA_W),
+        .ADDR_W(m_axi_wr[0].ADDR_W),
+        .STRB_W(m_axi_wr[0].STRB_W),
+        .ID_W(m_axi_wr[0].ID_W),
+        .AWUSER_EN(m_axi_wr[0].AWUSER_EN),
+        .AWUSER_W(m_axi_wr[0].AWUSER_W),
+        .WUSER_EN(m_axi_wr[0].WUSER_EN),
+        .WUSER_W(m_axi_wr[0].WUSER_W),
+        .BUSER_EN(m_axi_wr[0].BUSER_EN),
+        .BUSER_W(m_axi_wr[0].BUSER_W)
+    ) int_axi();
+
+    // in-flight transaction count
+    wire trans_start;
+    wire trans_complete;
+    localparam TR_CNT_W = $clog2(M_ISSUE_INT[n]+1);
+    logic [TR_CNT_W-1:0] trans_count_reg = '0;
+
+    wire trans_limit = trans_count_reg >= TR_CNT_W'(M_ISSUE_INT[n]) && !trans_complete;
+
+    always_ff @(posedge clk) begin
+        if (trans_start && !trans_complete) begin
+            trans_count_reg <= trans_count_reg + 1;
+        end else if (!trans_start && trans_complete) begin
+            trans_count_reg <= trans_count_reg - 1;
+        end
+
+        if (rst) begin
+            trans_count_reg <= 0;
+        end
+    end
+
+    // address arbitration
+    logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+    logic w_select_new_reg = 1'b0, w_select_new_next;
+
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    if (S_COUNT > 1) begin
+        assign int_axi.awid = {a_grant_index, int_s_axi_awid[a_grant_index]};
+    end else begin
+        assign int_axi.awid = int_s_axi_awid[a_grant_index];
+    end
+    assign int_axi.awaddr   = AXI_M_ADDR_W'(int_s_axi_awaddr[a_grant_index]);
+    assign int_axi.awlen    = int_s_axi_awlen[a_grant_index];
+    assign int_axi.awsize   = int_s_axi_awsize[a_grant_index];
+    assign int_axi.awburst  = int_s_axi_awburst[a_grant_index];
+    assign int_axi.awlock   = int_s_axi_awlock[a_grant_index];
+    assign int_axi.awcache  = int_s_axi_awcache[a_grant_index];
+    assign int_axi.awprot   = int_s_axi_awprot[a_grant_index];
+    assign int_axi.awqos    = int_s_axi_awqos[a_grant_index];
+    assign int_axi.awregion = int_s_axi_awregion[a_grant_index];
+    assign int_axi.awuser   = int_s_axi_awuser[a_grant_index];
+    assign int_axi.awvalid  = int_axi_awvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axi_awready[n] = '0;
+        int_axi_awready[n][a_grant_index] = a_grant_valid && int_axi.awready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axi_awvalid[m][n] && !a_grant_valid && !trans_limit && !w_select_valid_next;
+        assign a_ack[m] = a_grant[m] && int_axi_awvalid[m][n] && int_axi.awready;
+    end
+
+    assign trans_start = int_axi.awvalid && int_axi.awready && a_grant_valid;
+
+    // write data mux
+    assign int_axi.wdata   = int_s_axi_wdata[w_select_reg];
+    assign int_axi.wstrb   = int_s_axi_wstrb[w_select_reg];
+    assign int_axi.wlast   = int_s_axi_wlast[w_select_reg];
+    assign int_axi.wuser   = int_s_axi_wuser[w_select_reg];
+    assign int_axi.wvalid  = int_axi_wvalid[w_select_reg][n] && w_select_valid_reg;
+
+    always_comb begin
+        int_axi_wready[n] = '0;
+        int_axi_wready[n][w_select_reg] = w_select_valid_reg && int_axi.wready;
+    end
+
+    // write data routing
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
+        w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0;
+
+        if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+            w_select_next = a_grant_index;
+            w_select_valid_next = a_grant_valid;
+            w_select_new_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_reg <= w_select_next;
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_new_reg <= w_select_new_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+            w_select_new_reg <= 1'b1;
+        end
+    end
+
+    // write response forwarding
+    wire [CL_S_COUNT_INT-1:0] b_select = CL_S_COUNT_INT'(int_axi.bid >> S_ID_W);
+
+    assign int_m_axi_bid[n] = int_axi.bid;
+    assign int_m_axi_bresp[n] = int_axi.bresp;
+    assign int_m_axi_buser[n] = int_axi.buser;
+
+    always_comb begin
+        int_axi_bvalid[n] = '0;
+        int_axi_bvalid[n][b_select] = int_axi.bvalid;
+    end
+    assign int_axi.bready = int_axi_bready[b_select][n];
+
+    assign trans_complete = int_axi.bvalid && int_axi.bready;
+
+    // M side register
+    taxi_axi_register_wr #(
+        .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+        .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+        .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4 slave interface
+         */
+        .s_axi_wr(int_axi),
+
+        /*
+         * AXI4 master interface
+         */
+        .m_axi_wr(m_axi_wr[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_fifo_rd.sv

@@ -61,20 +61,20 @@ if (m_axi_rd.DATA_W != DATA_W)
 if (m_axi_rd.STRB_W != STRB_W)
     $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
 
-reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
-reg [FIFO_AW:0] wr_addr_reg = '0;
-reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
-reg [FIFO_AW:0] rd_addr_reg = '0;
+logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
+logic [FIFO_AW:0] wr_addr_reg = '0;
+logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
+logic [FIFO_AW:0] rd_addr_reg = '0;
 
 (* ramstyle = "no_rw_check" *)
-reg [RWIDTH-1:0] mem[2**FIFO_AW];
-reg [RWIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+logic [RWIDTH-1:0] mem[2**FIFO_AW];
+logic [RWIDTH-1:0] mem_read_data_reg;
+logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
 
 wire [RWIDTH-1:0] m_axi_r;
 
-reg [RWIDTH-1:0] s_axi_r_reg;
-reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+logic [RWIDTH-1:0] s_axi_r_reg;
+logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
 
 // full when first MSB different but rest same
 wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -83,9 +83,9 @@ wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
 wire empty = wr_ptr_reg == rd_ptr_reg;
 
 // control signals
-reg write;
-reg read;
-reg store_output;
+logic write;
+logic read;
+logic store_output;
 
 assign m_axi_rd.rready = !full;
 
@@ -104,24 +104,24 @@ if (FIFO_DELAY) begin
         STATE_IDLE = 1'd0,
         STATE_WAIT = 1'd1;
 
-    reg [0:0] state_reg = STATE_IDLE, state_next;
+    logic [0:0] state_reg = STATE_IDLE, state_next;
 
-    reg [COUNT_W-1:0] count_reg = 0, count_next;
+    logic [COUNT_W-1:0] count_reg = 0, count_next;
 
-    reg [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next;
-    reg [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next;
-    reg [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next;
-    reg [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next;
-    reg [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next;
-    reg m_axi_arlock_reg = '0, m_axi_arlock_next;
-    reg [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next;
-    reg [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next;
-    reg [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next;
-    reg [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next;
-    reg [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next;
-    reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
+    logic [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next;
+    logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next;
+    logic [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next;
+    logic [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next;
+    logic [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next;
+    logic m_axi_arlock_reg = '0, m_axi_arlock_next;
+    logic [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next;
+    logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next;
+    logic [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next;
+    logic [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next;
+    logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next;
+    logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
 
-    reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+    logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
 
     assign m_axi_rd.arid = m_axi_arid_reg;
     assign m_axi_rd.araddr = m_axi_araddr_reg;

src/axi/rtl/taxi_axi_fifo_wr.sv

@@ -62,20 +62,20 @@ if (m_axi_wr.DATA_W != DATA_W)
 if (m_axi_wr.STRB_W != STRB_W)
     $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
 
-reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
-reg [FIFO_AW:0] wr_addr_reg = '0;
-reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
-reg [FIFO_AW:0] rd_addr_reg = '0;
+logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
+logic [FIFO_AW:0] wr_addr_reg = '0;
+logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
+logic [FIFO_AW:0] rd_addr_reg = '0;
 
 (* ramstyle = "no_rw_check" *)
-reg [WWIDTH-1:0] mem[2**FIFO_AW];
-reg [WWIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+logic [WWIDTH-1:0] mem[2**FIFO_AW];
+logic [WWIDTH-1:0] mem_read_data_reg;
+logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
 
 wire [WWIDTH-1:0] s_axi_w;
 
-reg [WWIDTH-1:0] m_axi_w_reg;
-reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
+logic [WWIDTH-1:0] m_axi_w_reg;
+logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
 
 // full when first MSB different but rest same
 wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -86,9 +86,9 @@ wire empty = wr_ptr_reg == rd_ptr_reg;
 wire hold;
 
 // control signals
-reg write;
-reg read;
-reg store_output;
+logic write;
+logic read;
+logic store_output;
 
 assign s_axi_wr.wready = !full && !hold;
 assign s_axi_w[DATA_W-1:0] = s_axi_wr.wdata;
@@ -104,25 +104,25 @@ if (FIFO_DELAY) begin
         STATE_TRANSFER_IN = 2'd1,
         STATE_TRANSFER_OUT = 2'd2;
 
-    reg [1:0] state_reg = STATE_IDLE, state_next;
+    logic [1:0] state_reg = STATE_IDLE, state_next;
 
-    reg hold_reg = 1'b1, hold_next;
-    reg [8:0] count_reg = 9'd0, count_next;
+    logic hold_reg = 1'b1, hold_next;
+    logic [8:0] count_reg = 9'd0, count_next;
 
-    reg [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next;
-    reg [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
-    reg [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next;
-    reg [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next;
-    reg [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next;
-    reg m_axi_awlock_reg = '0, m_axi_awlock_next;
-    reg [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next;
-    reg [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
-    reg [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next;
-    reg [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next;
-    reg [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
-    reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
+    logic [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next;
+    logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
+    logic [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next;
+    logic [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next;
+    logic [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next;
+    logic m_axi_awlock_reg = '0, m_axi_awlock_next;
+    logic [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next;
+    logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
+    logic [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next;
+    logic [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next;
+    logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
+    logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
 
-    reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+    logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
 
     assign m_axi_wr.awid = m_axi_awid_reg;
     assign m_axi_wr.awaddr = m_axi_awaddr_reg;

src/axi/rtl/taxi_axi_interconnect.f

@@ -0,0 +1,6 @@
+taxi_axi_interconnect.sv
+taxi_axi_interconnect_rd.sv
+taxi_axi_interconnect_wr.sv
+taxi_axi_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axi_interconnect.sv

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT],
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+taxi_axi_interconnect_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interfaces
+     */
+    .s_axi_wr(s_axi_wr),
+
+    /*
+     * AXI4 master interfaces
+     */
+    .m_axi_wr(m_axi_wr)
+);
+
+taxi_axi_interconnect_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_SECURE(M_SECURE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interfaces
+     */
+    .s_axi_rd(s_axi_rd),
+
+    /*
+     * AXI4 master interfaces
+     */
+    .m_axi_rd(m_axi_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_interconnect_rd.sv

@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.rd_slv  s_axi_rd[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.rd_mst  m_axi_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_rd[0].DATA_W;
+localparam S_ADDR_W = s_axi_rd[0].ADDR_W;
+localparam STRB_W = s_axi_rd[0].STRB_W;
+localparam S_ID_W = s_axi_rd[0].ID_W;
+localparam M_ID_W = m_axi_rd.ID_W;
+localparam logic ARUSER_EN = s_axi_rd[0].ARUSER_EN && m_axi_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axi_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axi_rd[0].RUSER_EN && m_axi_rd[0].RUSER_EN;
+localparam RUSER_W = s_axi_rd[0].RUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axi_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+if (M_REGIONS < 1 || M_REGIONS > 16)
+    $fatal(0, "Error: M_REGIONS must be between 1 and 16 (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axi_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_READ = 3'd2,
+    STATE_READ_DROP = 3'd3,
+    STATE_WAIT_IDLE = 3'd4;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next;
+logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next;
+logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
+logic [7:0] axi_len_reg = 8'd0, axi_len_next;
+logic [2:0] axi_size_reg = 3'd0, axi_size_next;
+logic [1:0] axi_burst_reg = 2'd0, axi_burst_next;
+logic axi_lock_reg = 1'b0, axi_lock_next;
+logic [3:0] axi_cache_reg = 4'd0, axi_cache_next;
+logic [2:0] axi_prot_reg = 3'b000, axi_prot_next;
+logic [3:0] axi_qos_reg = 4'd0, axi_qos_next;
+logic [3:0] axi_region_reg = 4'd0, axi_region_next;
+logic [ARUSER_W-1:0] axi_aruser_reg = '0, axi_aruser_next;
+
+logic [S_COUNT-1:0] s_axi_arready_reg = '0, s_axi_arready_next;
+
+logic [M_COUNT-1:0] m_axi_arvalid_reg = '0, m_axi_arvalid_next;
+logic [M_COUNT-1:0] m_axi_rready_reg = '0, m_axi_rready_next;
+
+// internal datapath
+logic  [S_ID_W-1:0]   s_axi_rid_int;
+logic  [DATA_W-1:0]   s_axi_rdata_int;
+logic  [1:0]          s_axi_rresp_int;
+logic                 s_axi_rlast_int;
+logic  [RUSER_W-1:0]  s_axi_ruser_int;
+logic  [S_COUNT-1:0]  s_axi_rvalid_int;
+logic                 s_axi_rready_int_reg = 1'b0;
+wire                  s_axi_rready_int_early;
+
+// unpack interface array
+wire [S_ID_W-1:0]    s_axi_arid[S_COUNT];
+wire [ADDR_W-1:0]    s_axi_araddr[S_COUNT];
+wire [7:0]           s_axi_arlen[S_COUNT];
+wire [2:0]           s_axi_arsize[S_COUNT];
+wire [1:0]           s_axi_arburst[S_COUNT];
+wire                 s_axi_arlock[S_COUNT];
+wire [3:0]           s_axi_arcache[S_COUNT];
+wire [2:0]           s_axi_prot[S_COUNT];
+wire [3:0]           s_axi_arqos[S_COUNT];
+wire [ARUSER_W-1:0]  s_axi_aruser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_arvalid;
+
+wire [M_COUNT-1:0]   m_axi_arready;
+wire [M_ID_W-1:0]    m_axi_rid[M_COUNT];
+wire [DATA_W-1:0]    m_axi_rdata[M_COUNT];
+wire [1:0]           m_axi_rresp[M_COUNT];
+wire                 m_axi_rlast[M_COUNT];
+wire [RUSER_W-1:0]   m_axi_ruser[M_COUNT];
+wire [M_COUNT-1:0]   m_axi_rvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_arid[n] = s_axi_rd[n].arid;
+    assign s_axi_araddr[n] = s_axi_rd[n].araddr;
+    assign s_axi_arlen[n] = s_axi_rd[n].arlen;
+    assign s_axi_arsize[n] = s_axi_rd[n].arsize;
+    assign s_axi_arburst[n] = s_axi_rd[n].arburst;
+    assign s_axi_arlock[n] = s_axi_rd[n].arlock;
+    assign s_axi_arcache[n] = s_axi_rd[n].arcache;
+    assign s_axi_prot[n] = s_axi_rd[n].arprot;
+    assign s_axi_arqos[n] = s_axi_rd[n].arqos;
+    assign s_axi_aruser[n] = s_axi_rd[n].aruser;
+    assign s_axi_arvalid[n] = s_axi_rd[n].arvalid;
+    assign s_axi_rd[n].arready = s_axi_arready_reg[n];
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_rd[n].arid = axi_id_reg;
+    assign m_axi_rd[n].araddr = AXI_M_ADDR_W'(axi_addr_reg);
+    assign m_axi_rd[n].arlen = axi_len_reg;
+    assign m_axi_rd[n].arsize = axi_size_reg;
+    assign m_axi_rd[n].arburst = axi_burst_reg;
+    assign m_axi_rd[n].arlock = axi_lock_reg;
+    assign m_axi_rd[n].arcache = axi_cache_reg;
+    assign m_axi_rd[n].arprot = axi_prot_reg;
+    assign m_axi_rd[n].arqos = axi_qos_reg;
+    assign m_axi_rd[n].aruser = ARUSER_EN ? axi_aruser_reg : '0;
+    assign m_axi_rd[n].arvalid = m_axi_arvalid_reg[n];
+    assign m_axi_arready[n] = m_axi_rd[n].arready;
+    assign m_axi_rid[n] = m_axi_rd[n].rid;
+    assign m_axi_rdata[n] = m_axi_rd[n].rdata;
+    assign m_axi_rresp[n] = m_axi_rd[n].rresp;
+    assign m_axi_rlast[n] = m_axi_rd[n].rlast;
+    assign m_axi_ruser[n] = m_axi_rd[n].ruser;
+    assign m_axi_rvalid[n] = m_axi_rd[n].rvalid;
+    assign m_axi_rd[n].rready = m_axi_rready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [S_ID_W-1:0]    current_s_axi_arid    = s_axi_arid[s_select];
+wire [ADDR_W-1:0]    current_s_axi_araddr  = s_axi_araddr[s_select];
+wire [7:0]           current_s_axi_arlen   = s_axi_arlen[s_select];
+wire [2:0]           current_s_axi_arsize  = s_axi_arsize[s_select];
+wire [1:0]           current_s_axi_arburst = s_axi_arburst[s_select];
+wire                 current_s_axi_arlock  = s_axi_arlock[s_select];
+wire [3:0]           current_s_axi_arcache = s_axi_arcache[s_select];
+wire [2:0]           current_s_axi_prot    = s_axi_prot[s_select];
+wire [3:0]           current_s_axi_arqos   = s_axi_arqos[s_select];
+wire [ARUSER_W-1:0]  current_s_axi_aruser  = s_axi_aruser[s_select];
+wire                 current_s_axi_arvalid = s_axi_arvalid[s_select];
+wire                 current_s_axi_rready  = s_axi_rready[s_select];
+
+// master side mux
+wire                 current_m_axi_arready = m_axi_arready[m_select_reg];
+wire [M_ID_W-1:0]    current_m_axi_rid     = m_axi_rid[m_select_reg];
+wire [DATA_W-1:0]    current_m_axi_rdata   = m_axi_rdata[m_select_reg];
+wire [1:0]           current_m_axi_rresp   = m_axi_rresp[m_select_reg];
+wire                 current_m_axi_rlast   = m_axi_rlast[m_select_reg];
+wire [RUSER_W-1:0]   current_m_axi_ruser   = m_axi_ruser[m_select_reg];
+wire                 current_m_axi_rvalid  = m_axi_rvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+// req generation
+assign req = s_axi_arvalid;
+assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axi_id_next = axi_id_reg;
+    axi_addr_next = axi_addr_reg;
+    axi_addr_valid_next = axi_addr_valid_reg;
+    axi_len_next = axi_len_reg;
+    axi_size_next = axi_size_reg;
+    axi_burst_next = axi_burst_reg;
+    axi_lock_next = axi_lock_reg;
+    axi_cache_next = axi_cache_reg;
+    axi_prot_next = axi_prot_reg;
+    axi_qos_next = axi_qos_reg;
+    axi_region_next = axi_region_reg;
+    axi_aruser_next = axi_aruser_reg;
+
+    s_axi_arready_next = '0;
+
+    m_axi_arvalid_next = m_axi_arvalid_reg & ~m_axi_arready;
+    m_axi_rready_next = '0;
+
+    s_axi_rid_int = axi_id_reg;
+    s_axi_rdata_int = current_m_axi_rdata;
+    s_axi_rresp_int = current_m_axi_rresp;
+    s_axi_rlast_int = current_m_axi_rlast;
+    s_axi_ruser_int = current_m_axi_ruser;
+    s_axi_rvalid_int = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+
+            axi_addr_valid_next = 1'b1;
+            axi_id_next = current_s_axi_arid;
+            axi_addr_next = current_s_axi_araddr;
+            axi_len_next = current_s_axi_arlen;
+            axi_size_next = current_s_axi_arsize;
+            axi_burst_next = current_s_axi_arburst;
+            axi_lock_next = current_s_axi_arlock;
+            axi_cache_next = current_s_axi_arcache;
+            axi_prot_next = current_s_axi_prot;
+            axi_qos_next = current_s_axi_arqos;
+            axi_aruser_next = current_s_axi_aruser;
+
+            if (grant_valid) begin
+                s_axi_arready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            if (match) begin
+                m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
+                state_next = STATE_READ;
+            end else begin
+                // no match; return decode error
+                state_next = STATE_READ_DROP;
+            end
+        end
+        STATE_READ: begin
+            // read state; store and forward read response
+            m_axi_rready_next[m_select_reg] = s_axi_rready_int_early;
+
+            if (axi_addr_valid_reg) begin
+                m_axi_arvalid_next[m_select_reg] = 1'b1;
+            end
+            axi_addr_valid_next = 1'b0;
+
+            s_axi_rid_int = axi_id_reg;
+            s_axi_rdata_int = current_m_axi_rdata;
+            s_axi_rresp_int = current_m_axi_rresp;
+            s_axi_rlast_int = current_m_axi_rlast;
+            s_axi_ruser_int = current_m_axi_ruser;
+
+            if (m_axi_rready_reg != 0 && current_m_axi_rvalid) begin
+                s_axi_rvalid_int[s_select] = 1'b1;
+
+                if (current_m_axi_rlast) begin
+                    m_axi_rready_next[m_select_reg] = 1'b0;
+                    state_next = STATE_WAIT_IDLE;
+                end else begin
+                    state_next = STATE_READ;
+                end
+            end else begin
+                state_next = STATE_READ;
+            end
+        end
+        STATE_READ_DROP: begin
+            // read drop state; generate decode error read response
+
+            s_axi_rid_int = axi_id_reg;
+            s_axi_rdata_int = '0;
+            s_axi_rresp_int = 2'b11;
+            s_axi_rlast_int = axi_len_reg == 0;
+            s_axi_ruser_int = '0;
+            s_axi_rvalid_int[s_select] = 1'b1;
+
+            if (s_axi_rready_int_reg) begin
+                axi_len_next = axi_len_reg - 1;
+                if (axi_len_reg == 0) begin
+                    state_next = STATE_WAIT_IDLE;
+                end else begin
+                    state_next = STATE_READ_DROP;
+                end
+            end else begin
+                state_next = STATE_READ_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait untl grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    s_axi_arready_reg <= s_axi_arready_next;
+
+    m_axi_arvalid_reg <= m_axi_arvalid_next;
+    m_axi_rready_reg <= m_axi_rready_next;
+
+    m_select_reg <= m_select_next;
+    axi_id_reg <= axi_id_next;
+    axi_addr_reg <= axi_addr_next;
+    axi_addr_valid_reg <= axi_addr_valid_next;
+    axi_len_reg <= axi_len_next;
+    axi_size_reg <= axi_size_next;
+    axi_burst_reg <= axi_burst_next;
+    axi_lock_reg <= axi_lock_next;
+    axi_cache_reg <= axi_cache_next;
+    axi_prot_reg <= axi_prot_next;
+    axi_qos_reg <= axi_qos_next;
+    axi_region_reg <= axi_region_next;
+    axi_aruser_reg <= axi_aruser_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_arready_reg <= '0;
+
+        m_axi_arvalid_reg <= '0;
+        m_axi_rready_reg <= '0;
+    end
+end
+
+// output datapath logic (R channel)
+logic [S_ID_W-1:0]  s_axi_rid_reg    = '0;
+logic [DATA_W-1:0]  s_axi_rdata_reg  = '0;
+logic [1:0]         s_axi_rresp_reg  = 2'd0;
+logic               s_axi_rlast_reg  = 1'b0;
+logic [RUSER_W-1:0] s_axi_ruser_reg  = 1'b0;
+logic [S_COUNT-1:0] s_axi_rvalid_reg = '0, s_axi_rvalid_next;
+
+logic [S_ID_W-1:0]  temp_s_axi_rid_reg    = '0;
+logic [DATA_W-1:0]  temp_s_axi_rdata_reg  = '0;
+logic [1:0]         temp_s_axi_rresp_reg  = 2'd0;
+logic               temp_s_axi_rlast_reg  = 1'b0;
+logic [RUSER_W-1:0] temp_s_axi_ruser_reg  = 1'b0;
+logic [S_COUNT-1:0] temp_s_axi_rvalid_reg = '0, temp_s_axi_rvalid_next;
+
+// datapath control
+logic store_axi_r_int_to_output;
+logic store_axi_r_int_to_temp;
+logic store_axi_r_temp_to_output;
+
+wire [S_COUNT-1:0] s_axi_rready;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_rd[n].rid = s_axi_rid_reg;
+    assign s_axi_rd[n].rdata = s_axi_rdata_reg;
+    assign s_axi_rd[n].rresp = s_axi_rresp_reg;
+    assign s_axi_rd[n].rlast = s_axi_rlast_reg;
+    assign s_axi_rd[n].ruser = RUSER_EN ? s_axi_ruser_reg : '0;
+    assign s_axi_rd[n].rvalid = s_axi_rvalid_reg[n];
+    assign s_axi_rready[n] = s_axi_rd[n].rready;
+end
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign s_axi_rready_int_early = (s_axi_rready & s_axi_rvalid_reg) != 0 || (temp_s_axi_rvalid_reg == 0 && (s_axi_rvalid_reg == 0 || s_axi_rvalid_int == 0));
+
+always_comb begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+    temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+
+    store_axi_r_int_to_output = 1'b0;
+    store_axi_r_int_to_temp = 1'b0;
+    store_axi_r_temp_to_output = 1'b0;
+
+    if (s_axi_rready_int_reg) begin
+        // input is ready
+        if ((s_axi_rready & s_axi_rvalid_reg) != 0 || s_axi_rvalid_reg == 0) begin
+            // output is ready or currently not valid, transfer data to output
+            s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_s_axi_rvalid_next = s_axi_rvalid_int;
+            store_axi_r_int_to_temp = 1'b1;
+        end
+    end else if ((s_axi_rready & s_axi_rvalid_reg) != 0) begin
+        // input is not ready, but output is ready
+        s_axi_rvalid_next = temp_s_axi_rvalid_reg;
+        temp_s_axi_rvalid_next = '0;
+        store_axi_r_temp_to_output = 1'b1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    s_axi_rvalid_reg <= s_axi_rvalid_next;
+    s_axi_rready_int_reg <= s_axi_rready_int_early;
+    temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
+
+    // datapath
+    if (store_axi_r_int_to_output) begin
+        s_axi_rid_reg <= s_axi_rid_int;
+        s_axi_rdata_reg <= s_axi_rdata_int;
+        s_axi_rresp_reg <= s_axi_rresp_int;
+        s_axi_rlast_reg <= s_axi_rlast_int;
+        s_axi_ruser_reg <= s_axi_ruser_int;
+    end else if (store_axi_r_temp_to_output) begin
+        s_axi_rid_reg <= temp_s_axi_rid_reg;
+        s_axi_rdata_reg <= temp_s_axi_rdata_reg;
+        s_axi_rresp_reg <= temp_s_axi_rresp_reg;
+        s_axi_rlast_reg <= temp_s_axi_rlast_reg;
+        s_axi_ruser_reg <= temp_s_axi_ruser_reg;
+    end
+
+    if (store_axi_r_int_to_temp) begin
+        temp_s_axi_rid_reg <= s_axi_rid_int;
+        temp_s_axi_rdata_reg <= s_axi_rdata_int;
+        temp_s_axi_rresp_reg <= s_axi_rresp_int;
+        temp_s_axi_rlast_reg <= s_axi_rlast_int;
+        temp_s_axi_ruser_reg <= s_axi_ruser_int;
+    end
+
+    if (rst) begin
+        s_axi_rvalid_reg <= '0;
+        s_axi_rready_int_reg <= 1'b0;
+        temp_s_axi_rvalid_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axi_interconnect_wr.sv

@@ -0,0 +1,668 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect
+ */
+module taxi_axi_interconnect_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = 0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic   clk,
+    input  wire logic   rst,
+
+    /*
+     * AXI4 slave interfaces
+     */
+    taxi_axi_if.wr_slv  s_axi_wr[S_COUNT],
+
+    /*
+     * AXI4 master interfaces
+     */
+    taxi_axi_if.wr_mst  m_axi_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axi_wr[0].DATA_W;
+localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
+localparam STRB_W = s_axi_wr[0].STRB_W;
+localparam S_ID_W = s_axi_wr[0].ID_W;
+localparam M_ID_W = m_axi_wr[0].ID_W;
+localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
+localparam WUSER_W = s_axi_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
+localparam BUSER_W = s_axi_wr[0].BUSER_W;
+
+localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axi_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axi_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    if (M_REGIONS < 1 || M_REGIONS > 16) begin
+        $error("Error: M_REGIONS must be between 1 and 16 (instance %m)");
+        $finish;
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axi_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_WRITE = 3'd2,
+    STATE_WRITE_RESP = 3'd3,
+    STATE_WRITE_DROP = 3'd4,
+    STATE_WAIT_IDLE = 3'd5;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next;
+logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next;
+logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
+logic [7:0] axi_len_reg = 8'd0, axi_len_next;
+logic [2:0] axi_size_reg = 3'd0, axi_size_next;
+logic [1:0] axi_burst_reg = 2'd0, axi_burst_next;
+logic axi_lock_reg = 1'b0, axi_lock_next;
+logic [3:0] axi_cache_reg = 4'd0, axi_cache_next;
+logic [2:0] axi_prot_reg = 3'b000, axi_prot_next;
+logic [3:0] axi_qos_reg = 4'd0, axi_qos_next;
+logic [3:0] axi_region_reg = 4'd0, axi_region_next;
+logic [AWUSER_W-1:0] axi_awuser_reg = '0, axi_awuser_next;
+logic [1:0] axi_bresp_reg = 2'b00, axi_bresp_next;
+logic [BUSER_W-1:0] axi_buser_reg = '0, axi_buser_next;
+
+logic [S_COUNT-1:0] s_axi_awready_reg = '0, s_axi_awready_next;
+logic [S_COUNT-1:0] s_axi_wready_reg = '0, s_axi_wready_next;
+logic [S_COUNT-1:0] s_axi_bvalid_reg = '0, s_axi_bvalid_next;
+
+logic [M_COUNT-1:0] m_axi_awvalid_reg = '0, m_axi_awvalid_next;
+logic [M_COUNT-1:0] m_axi_bready_reg = '0, m_axi_bready_next;
+
+// internal datapath
+logic  [DATA_W-1:0]   m_axi_wdata_int;
+logic  [STRB_W-1:0]   m_axi_wstrb_int;
+logic                 m_axi_wlast_int;
+logic  [WUSER_W-1:0]  m_axi_wuser_int;
+logic  [M_COUNT-1:0]  m_axi_wvalid_int;
+logic                 m_axi_wready_int_reg = 1'b0;
+wire                  m_axi_wready_int_early;
+
+// unpack interface array
+wire [S_ID_W-1:0]    s_axi_awid[S_COUNT];
+wire [ADDR_W-1:0]    s_axi_addr[S_COUNT];
+wire [7:0]           s_axi_awlen[S_COUNT];
+wire [2:0]           s_axi_awsize[S_COUNT];
+wire [1:0]           s_axi_awburst[S_COUNT];
+wire                 s_axi_awlock[S_COUNT];
+wire [3:0]           s_axi_awcache[S_COUNT];
+wire [2:0]           s_axi_awprot[S_COUNT];
+wire [3:0]           s_axi_awqos[S_COUNT];
+wire [AWUSER_W-1:0]  s_axi_awuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_awvalid;
+wire [DATA_W-1:0]    s_axi_wdata[S_COUNT];
+wire [STRB_W-1:0]    s_axi_wstrb[S_COUNT];
+wire                 s_axi_wlast[S_COUNT];
+wire [WUSER_W-1:0]   s_axi_wuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axi_wvalid;
+wire [S_COUNT-1:0]   s_axi_bready;
+
+wire [M_COUNT-1:0]   m_axi_awready;
+wire [M_ID_W-1:0]    m_axi_bid[M_COUNT];
+wire [1:0]           m_axi_bresp[M_COUNT];
+wire [BUSER_W-1:0]   m_axi_buser[M_COUNT];
+wire [M_COUNT-1:0]   m_axi_bvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axi_awid[n] = s_axi_wr[n].awid;
+    assign s_axi_addr[n] = s_axi_wr[n].awaddr;
+    assign s_axi_awlen[n] = s_axi_wr[n].awlen;
+    assign s_axi_awsize[n] = s_axi_wr[n].awsize;
+    assign s_axi_awburst[n] = s_axi_wr[n].awburst;
+    assign s_axi_awlock[n] = s_axi_wr[n].awlock;
+    assign s_axi_awcache[n] = s_axi_wr[n].awcache;
+    assign s_axi_awprot[n] = s_axi_wr[n].awprot;
+    assign s_axi_awqos[n] = s_axi_wr[n].awqos;
+    assign s_axi_awuser[n] = s_axi_wr[n].awuser;
+    assign s_axi_awvalid[n] = s_axi_wr[n].awvalid;
+    assign s_axi_wr[n].awready = s_axi_awready_reg[n];
+    assign s_axi_wdata[n] = s_axi_wr[n].wdata;
+    assign s_axi_wstrb[n] = s_axi_wr[n].wstrb;
+    assign s_axi_wlast[n] = s_axi_wr[n].wlast;
+    assign s_axi_wuser[n] = s_axi_wr[n].wuser;
+    assign s_axi_wvalid[n] = s_axi_wr[n].wvalid;
+    assign s_axi_wr[n].wready = s_axi_wready_reg[n];
+    assign s_axi_wr[n].bid = axi_id_reg;
+    assign s_axi_wr[n].bresp = axi_bresp_reg;
+    assign s_axi_wr[n].buser = BUSER_EN ? axi_buser_reg : '0;
+    assign s_axi_wr[n].bvalid = s_axi_bvalid_reg[n];
+    assign s_axi_bready[n] = s_axi_wr[n].bready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_wr[n].awid = axi_id_reg;
+    assign m_axi_wr[n].awaddr = AXI_M_ADDR_W'(axi_addr_reg);
+    assign m_axi_wr[n].awlen = axi_len_reg;
+    assign m_axi_wr[n].awsize = axi_size_reg;
+    assign m_axi_wr[n].awburst = axi_burst_reg;
+    assign m_axi_wr[n].awlock = axi_lock_reg;
+    assign m_axi_wr[n].awcache = axi_cache_reg;
+    assign m_axi_wr[n].awprot = axi_prot_reg;
+    assign m_axi_wr[n].awqos = axi_qos_reg;
+    assign m_axi_wr[n].awuser = AWUSER_EN ? axi_awuser_reg : '0;
+    assign m_axi_wr[n].awvalid = m_axi_awvalid_reg[n];
+    assign m_axi_awready[n] = m_axi_wr[n].awready;
+    assign m_axi_bid[n] = m_axi_wr[n].bid;
+    assign m_axi_bresp[n] = m_axi_wr[n].bresp;
+    assign m_axi_buser[n] = m_axi_wr[n].buser;
+    assign m_axi_bvalid[n] = m_axi_wr[n].bvalid;
+    assign m_axi_wr[n].bready = m_axi_bready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [S_ID_W-1:0]    current_s_axi_awid    = s_axi_awid[s_select];
+wire [ADDR_W-1:0]    current_s_axi_addr    = s_axi_addr[s_select];
+wire [7:0]           current_s_axi_awlen   = s_axi_awlen[s_select];
+wire [2:0]           current_s_axi_awsize  = s_axi_awsize[s_select];
+wire [1:0]           current_s_axi_awburst = s_axi_awburst[s_select];
+wire                 current_s_axi_awlock  = s_axi_awlock[s_select];
+wire [3:0]           current_s_axi_awcache = s_axi_awcache[s_select];
+wire [2:0]           current_s_axi_awprot  = s_axi_awprot[s_select];
+wire [3:0]           current_s_axi_awqos   = s_axi_awqos[s_select];
+wire [AWUSER_W-1:0]  current_s_axi_awuser  = s_axi_awuser[s_select];
+wire                 current_s_axi_awvalid = s_axi_awvalid[s_select];
+wire [DATA_W-1:0]    current_s_axi_wdata   = s_axi_wdata[s_select];
+wire [STRB_W-1:0]    current_s_axi_wstrb   = s_axi_wstrb[s_select];
+wire                 current_s_axi_wlast   = s_axi_wlast[s_select];
+wire [WUSER_W-1:0]   current_s_axi_wuser   = s_axi_wuser[s_select];
+wire                 current_s_axi_wvalid  = s_axi_wvalid[s_select];
+wire                 current_s_axi_bready  = s_axi_bready[s_select];
+
+// master side mux
+wire                 current_m_axi_awready = m_axi_awready[m_select_reg];
+wire                 current_m_axi_wready  = m_axi_wready[m_select_reg];
+wire [M_ID_W-1:0]    current_m_axi_bid     = m_axi_bid[m_select_reg];
+wire [1:0]           current_m_axi_bresp   = m_axi_bresp[m_select_reg];
+wire [BUSER_W-1:0]   current_m_axi_buser   = m_axi_buser[m_select_reg];
+wire                 current_m_axi_bvalid  = m_axi_bvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+assign req = s_axi_awvalid;
+assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axi_id_next = axi_id_reg;
+    axi_addr_next = axi_addr_reg;
+    axi_addr_valid_next = axi_addr_valid_reg;
+    axi_len_next = axi_len_reg;
+    axi_size_next = axi_size_reg;
+    axi_burst_next = axi_burst_reg;
+    axi_lock_next = axi_lock_reg;
+    axi_cache_next = axi_cache_reg;
+    axi_prot_next = axi_prot_reg;
+    axi_qos_next = axi_qos_reg;
+    axi_region_next = axi_region_reg;
+    axi_awuser_next = axi_awuser_reg;
+    axi_bresp_next = axi_bresp_reg;
+    axi_buser_next = axi_buser_reg;
+
+    s_axi_awready_next = '0;
+    s_axi_wready_next = '0;
+    s_axi_bvalid_next = s_axi_bvalid_reg & ~s_axi_bready;
+
+    m_axi_awvalid_next = m_axi_awvalid_reg & ~m_axi_awready;
+    m_axi_bready_next = '0;
+
+    m_axi_wdata_int = current_s_axi_wdata;
+    m_axi_wstrb_int = current_s_axi_wstrb;
+    m_axi_wlast_int = current_s_axi_wlast;
+    m_axi_wuser_int = current_s_axi_wuser;
+    m_axi_wvalid_int = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+
+            axi_addr_valid_next = 1'b1;
+            axi_id_next = current_s_axi_awid;
+            axi_addr_next = current_s_axi_addr;
+            axi_len_next = current_s_axi_awlen;
+            axi_size_next = current_s_axi_awsize;
+            axi_burst_next = current_s_axi_awburst;
+            axi_lock_next = current_s_axi_awlock;
+            axi_cache_next = current_s_axi_awcache;
+            axi_prot_next = current_s_axi_awprot;
+            axi_qos_next = current_s_axi_awqos;
+            axi_awuser_next = current_s_axi_awuser;
+
+            if (grant_valid) begin
+                s_axi_awready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            axi_bresp_next = 2'b11;
+
+            if (match) begin
+                s_axi_wready_next[s_select] = m_axi_wready_int_early;
+                state_next = STATE_WRITE;
+            end else begin
+                // no match; return decode error
+                s_axi_wready_next[s_select] = 1'b1;
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WRITE: begin
+            // write state; store and forward write data
+            s_axi_wready_next[s_select] = m_axi_wready_int_early;
+
+            if (axi_addr_valid_reg) begin
+                m_axi_awvalid_next[m_select_reg] = 1'b1;
+            end
+            axi_addr_valid_next = 1'b0;
+
+            m_axi_wdata_int = current_s_axi_wdata;
+            m_axi_wstrb_int = current_s_axi_wstrb;
+            m_axi_wlast_int = current_s_axi_wlast;
+            m_axi_wuser_int = current_s_axi_wuser;
+
+            if (s_axi_wready_reg != 0 && current_s_axi_wvalid) begin
+                m_axi_wvalid_int[m_select_reg] = 1'b1;
+
+                if (current_s_axi_wlast) begin
+                    s_axi_wready_next[s_select] = 1'b0;
+                    m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
+                    state_next = STATE_WRITE_RESP;
+                end else begin
+                    state_next = STATE_WRITE;
+                end
+            end else begin
+                state_next = STATE_WRITE;
+            end
+        end
+        STATE_WRITE_RESP: begin
+            // write response state; store and forward write response
+            m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0;
+
+            if (m_axi_bready_reg != 0 && current_m_axi_bvalid) begin
+                m_axi_bready_next[m_select_reg] = 1'b0;
+                axi_bresp_next = current_m_axi_bresp;
+                s_axi_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_RESP;
+            end
+        end
+        STATE_WRITE_DROP: begin
+            // write drop state; drop write data
+            s_axi_wready_next[s_select] = 1'b1;
+
+            axi_addr_valid_next = 1'b0;
+
+            if (s_axi_wready_reg != 0 && current_s_axi_wvalid && current_s_axi_wlast) begin
+                s_axi_wready_next[s_select] = 1'b0;
+                s_axi_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait untl grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    s_axi_awready_reg <= s_axi_awready_next;
+    s_axi_wready_reg <= s_axi_wready_next;
+    s_axi_bvalid_reg <= s_axi_bvalid_next;
+
+    m_axi_awvalid_reg <= m_axi_awvalid_next;
+    m_axi_bready_reg <= m_axi_bready_next;
+
+    m_select_reg <= m_select_next;
+    axi_id_reg <= axi_id_next;
+    axi_addr_reg <= axi_addr_next;
+    axi_addr_valid_reg <= axi_addr_valid_next;
+    axi_len_reg <= axi_len_next;
+    axi_size_reg <= axi_size_next;
+    axi_burst_reg <= axi_burst_next;
+    axi_lock_reg <= axi_lock_next;
+    axi_cache_reg <= axi_cache_next;
+    axi_prot_reg <= axi_prot_next;
+    axi_qos_reg <= axi_qos_next;
+    axi_region_reg <= axi_region_next;
+    axi_awuser_reg <= axi_awuser_next;
+    axi_bresp_reg <= axi_bresp_next;
+    axi_buser_reg <= axi_buser_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axi_awready_reg <= '0;
+        s_axi_wready_reg <= '0;
+        s_axi_bvalid_reg <= '0;
+
+        m_axi_awvalid_reg <= '0;
+        m_axi_bready_reg <= '0;
+    end
+end
+
+// output datapath logic (W channel)
+logic [DATA_W-1:0]  m_axi_wdata_reg  = '0;
+logic [STRB_W-1:0]  m_axi_wstrb_reg  = '0;
+logic               m_axi_wlast_reg  = 1'b0;
+logic [WUSER_W-1:0] m_axi_wuser_reg  = 1'b0;
+logic [M_COUNT-1:0] m_axi_wvalid_reg = '0, m_axi_wvalid_next;
+
+logic [DATA_W-1:0]  temp_m_axi_wdata_reg  = '0;
+logic [STRB_W-1:0]  temp_m_axi_wstrb_reg  = '0;
+logic               temp_m_axi_wlast_reg  = 1'b0;
+logic [WUSER_W-1:0] temp_m_axi_wuser_reg  = 1'b0;
+logic [M_COUNT-1:0] temp_m_axi_wvalid_reg = '0, temp_m_axi_wvalid_next;
+
+// datapath control
+logic store_axi_w_int_to_output;
+logic store_axi_w_int_to_temp;
+logic store_axi_w_temp_to_output;
+
+wire [M_COUNT-1:0] m_axi_wready;
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axi_wr[n].wdata = m_axi_wdata_reg;
+    assign m_axi_wr[n].wstrb = m_axi_wstrb_reg;
+    assign m_axi_wr[n].wlast = m_axi_wlast_reg;
+    assign m_axi_wr[n].wuser = WUSER_EN ? m_axi_wuser_reg : '0;
+    assign m_axi_wr[n].wvalid = m_axi_wvalid_reg[n];
+    assign m_axi_wready[n] = m_axi_wr[n].wready;
+end
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axi_wready_int_early = (m_axi_wready & m_axi_wvalid_reg) != 0 || (temp_m_axi_wvalid_reg == 0 && (m_axi_wvalid_reg == 0 || m_axi_wvalid_int == 0));
+
+always_comb begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;
+    temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+
+    store_axi_w_int_to_output = 1'b0;
+    store_axi_w_int_to_temp = 1'b0;
+    store_axi_w_temp_to_output = 1'b0;
+
+    if (m_axi_wready_int_reg) begin
+        // input is ready
+        if ((m_axi_wready & m_axi_wvalid_reg) != 0 || m_axi_wvalid_reg == 0) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axi_wvalid_next = m_axi_wvalid_int;
+            store_axi_w_int_to_temp = 1'b1;
+        end
+    end else if ((m_axi_wready & m_axi_wvalid_reg) != 0) begin
+        // input is not ready, but output is ready
+        m_axi_wvalid_next = temp_m_axi_wvalid_reg;
+        temp_m_axi_wvalid_next = '0;
+        store_axi_w_temp_to_output = 1'b1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    m_axi_wvalid_reg <= m_axi_wvalid_next;
+    m_axi_wready_int_reg <= m_axi_wready_int_early;
+    temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
+
+    // datapath
+    if (store_axi_w_int_to_output) begin
+        m_axi_wdata_reg <= m_axi_wdata_int;
+        m_axi_wstrb_reg <= m_axi_wstrb_int;
+        m_axi_wlast_reg <= m_axi_wlast_int;
+        m_axi_wuser_reg <= m_axi_wuser_int;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end
+
+    if (store_axi_w_int_to_temp) begin
+        temp_m_axi_wdata_reg <= m_axi_wdata_int;
+        temp_m_axi_wstrb_reg <= m_axi_wstrb_int;
+        temp_m_axi_wlast_reg <= m_axi_wlast_int;
+        temp_m_axi_wuser_reg <= m_axi_wuser_int;
+    end
+
+    if (rst) begin
+        m_axi_wvalid_reg <= '0;
+        m_axi_wready_int_reg <= 1'b0;
+        temp_m_axi_wvalid_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_apb_adapter.sv

@@ -73,7 +73,7 @@ if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
     $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
 
 if (APB_BYTE_W * APB_STRB_W != APB_DATA_W)
-    $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)");
+    $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)");
 
 if (AXIL_BYTE_W != APB_BYTE_W)
     $fatal(0, "Error: byte size mismatch (instance %m)");
@@ -248,7 +248,7 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
         endcase
     end
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         state_reg <= state_next;
 
         last_read_reg <= last_read_next;
@@ -447,7 +447,7 @@ end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
         endcase
     end
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         state_reg <= state_next;
 
         last_read_reg <= last_read_next;

src/axi/rtl/taxi_axil_crossbar.f

@@ -0,0 +1,3 @@
+taxi_axil_crossbar.sv
+taxi_axil_crossbar_wr.f
+taxi_axil_crossbar_rd.f

src/axi/rtl/taxi_axil_crossbar.sv

@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar
+ */
+module taxi_axil_crossbar #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT],
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+taxi_axil_crossbar_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI lite slave interfaces
+     */
+    .s_axil_wr(s_axil_wr),
+
+    /*
+     * AXI lite master interfaces
+     */
+    .m_axil_wr(m_axil_wr)
+);
+
+taxi_axil_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI lite slave interfaces
+     */
+    .s_axil_rd(s_axil_rd),
+
+    /*
+     * AXI lite master interfaces
+     */
+    .m_axil_rd(m_axil_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_addr.sv

@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar address decode and admission control
+ */
+module taxi_axil_crossbar_addr #
+(
+    // Slave interface index
+    parameter S = 0,
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Select signal width
+    parameter SEL_W = $clog2(M_COUNT),
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Address width in bits for address decoding
+    parameter STRB_W = 4,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Enable write command output
+    parameter WC_OUTPUT = 0
+)
+(
+    input  wire logic               clk,
+    input  wire logic               rst,
+
+    /*
+     * Address input
+     */
+    input  wire logic [ADDR_W-1:0]  s_axil_aaddr,
+    input  wire logic [2:0]         s_axil_aprot,
+    input  wire logic               s_axil_avalid,
+    output wire logic               s_axil_aready,
+
+    /*
+     * Select output
+     */
+    output wire logic [SEL_W-1:0]   m_select,
+    output wire logic               m_axil_avalid,
+    input  wire logic               m_axil_aready,
+
+    /*
+     * Write command output
+     */
+    output wire logic [SEL_W-1:0]   m_wc_select,
+    output wire logic               m_wc_decerr,
+    output wire logic               m_wc_valid,
+    input  wire logic               m_wc_ready,
+
+    /*
+     * Reply command output
+     */
+    output wire logic [SEL_W-1:0]   m_rc_select,
+    output wire logic               m_rc_decerr,
+    output wire logic               m_rc_valid,
+    input  wire logic               m_rc_ready
+);
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (M_REGIONS < 1)
+    $fatal(0, "Error: M_REGIONS must be at least 1 (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_crossbar_addr instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [0:0]
+    STATE_IDLE = 1'd0,
+    STATE_DECODE = 1'd1;
+
+logic [0:0] state_reg = STATE_IDLE, state_next;
+
+logic s_axil_aready_reg = 1'b0, s_axil_aready_next;
+
+logic [SEL_W-1:0] m_select_reg = '0, m_select_next;
+logic m_axil_avalid_reg = 1'b0, m_axil_avalid_next;
+logic m_decerr_reg = 1'b0, m_decerr_next;
+logic m_wc_valid_reg = 1'b0, m_wc_valid_next;
+logic m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axil_aready = s_axil_aready_reg;
+
+assign m_select = m_select_reg;
+assign m_axil_avalid = m_axil_avalid_reg;
+
+assign m_wc_select = m_select_reg;
+assign m_wc_decerr = m_decerr_reg;
+assign m_wc_valid = m_wc_valid_reg;
+
+assign m_rc_select = m_select_reg;
+assign m_rc_decerr = m_decerr_reg;
+assign m_rc_valid = m_rc_valid_reg;
+
+logic match;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    s_axil_aready_next = 1'b0;
+
+    m_select_next = m_select_reg;
+    m_axil_avalid_next = m_axil_avalid_reg && !m_axil_aready;
+    m_decerr_next = m_decerr_reg;
+    m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;
+    m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state, store values
+            s_axil_aready_next = 1'b0;
+
+            if (s_axil_avalid && !s_axil_aready) begin
+                match = 1'b0;
+                for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                    for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                        if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_axil_aprot[1]) && M_CONNECT_INT[i][S] && (s_axil_aaddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                            m_select_next = SEL_W'(i);
+                            match = 1'b1;
+                        end
+                    end
+                end
+
+                if (match) begin
+                    // address decode successful
+                    m_axil_avalid_next = 1'b1;
+                    m_decerr_next = 1'b0;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end else begin
+                    // decode error
+                    m_axil_avalid_next = 1'b0;
+                    m_decerr_next = 1'b1;
+                    m_wc_valid_next = WC_OUTPUT;
+                    m_rc_valid_next = 1'b1;
+                    state_next = STATE_DECODE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            if (!m_axil_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin
+                s_axil_aready_next = 1'b1;
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_DECODE;
+            end
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+    s_axil_aready_reg <= s_axil_aready_next;
+    m_axil_avalid_reg <= m_axil_avalid_next;
+    m_wc_valid_reg <= m_wc_valid_next;
+    m_rc_valid_reg <= m_rc_valid_next;
+
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        s_axil_aready_reg <= 1'b0;
+        m_axil_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_rd.f

@@ -0,0 +1,6 @@
+taxi_axil_crossbar_rd.sv
+taxi_axil_crossbar_addr.sv
+taxi_axil_register_rd.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_crossbar_rd.sv

@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar (read)
+ */
+module taxi_axil_crossbar_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AR channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface R channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    // Master interface AR channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface R channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_rd[0].DATA_W;
+localparam S_ADDR_W = s_axil_rd[0].ADDR_W;
+localparam STRB_W = s_axil_rd[0].STRB_W;
+localparam logic ARUSER_EN = s_axil_rd[0].ARUSER_EN && m_axil_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
+localparam RUSER_W = s_axil_rd[0].RUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axil_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+wire [ADDR_W-1:0]    int_s_axil_araddr[S_COUNT];
+wire [2:0]           int_s_axil_arprot[S_COUNT];
+wire [ARUSER_W-1:0]  int_s_axil_aruser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_arvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_arready[M_COUNT];
+
+wire [DATA_W-1:0]    int_m_axil_rdata[M_COUNT];
+wire [1:0]           int_m_axil_rresp[M_COUNT];
+wire [RUSER_W-1:0]   int_m_axil_ruser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axil_rvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axil_rready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(s_axil_rd[0].DATA_W),
+        .ADDR_W(s_axil_rd[0].ADDR_W),
+        .STRB_W(s_axil_rd[0].STRB_W),
+        .ARUSER_EN(s_axil_rd[0].ARUSER_EN),
+        .ARUSER_W(s_axil_rd[0].ARUSER_W),
+        .RUSER_EN(s_axil_rd[0].RUSER_EN),
+        .RUSER_W(s_axil_rd[0].RUSER_W)
+    ) int_axil();
+
+    // S side register
+    taxi_axil_register_rd #(
+        .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
+        .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_rd(s_axil_rd[m]),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_rd(int_axil)
+    );
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = 0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = 0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic fifo_decerr[2**FIFO_AW];
+
+    wire [CL_M_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_decerr;
+    wire fifo_wr_en;
+
+    logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = 0;
+    logic fifo_rd_decerr_reg = 0;
+    logic fifo_rd_valid_reg = 0;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    integer i;
+
+    initial begin
+        for (i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = 0;
+            fifo_decerr[i] = 0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+
+        fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+        if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+            fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_valid_reg <= 1'b1;
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= 0;
+            fifo_rd_ptr_reg <= 0;
+            fifo_rd_valid_reg <= 1'b0;
+        end
+    end
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axil_avalid;
+    wire m_axil_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_rc_select;
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    taxi_axil_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .STRB_W(STRB_W),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(0)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axil_aaddr(int_axil.araddr),
+        .s_axil_aprot(int_axil.arprot),
+        .s_axil_avalid(int_axil.arvalid),
+        .s_axil_aready(int_axil.arready),
+
+        /*
+         * Address output
+         */
+        .m_select(a_select),
+        .m_axil_avalid(m_axil_avalid),
+        .m_axil_aready(m_axil_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(),
+        .m_wc_decerr(),
+        .m_wc_valid(),
+        .m_wc_ready(1'b1),
+
+        /*
+         * Response command output
+         */
+        .m_rc_select(m_rc_select),
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready)
+    );
+
+    assign int_s_axil_araddr[m] = int_axil.araddr;
+    assign int_s_axil_arprot[m] = int_axil.arprot;
+    assign int_s_axil_aruser[m] = int_axil.aruser;
+
+    always_comb begin
+        int_axil_arvalid[m] = '0;
+        int_axil_arvalid[m][a_select] = m_axil_avalid;
+    end
+    assign m_axil_aready = int_axil_arready[a_select][m];
+
+    // response handling
+    assign fifo_wr_select = m_rc_select;
+    assign fifo_wr_decerr = m_rc_decerr;
+    assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg;
+    assign m_rc_ready = !fifo_half_full_reg;
+
+    // write response handling
+    wire [CL_M_COUNT_INT-1:0] r_select = M_COUNT > 1 ? fifo_rd_select_reg : '0;
+    wire r_decerr = fifo_rd_decerr_reg;
+    wire r_valid = fifo_rd_valid_reg;
+
+    // read response mux
+    assign int_axil.rdata  = r_decerr ? '0 : int_m_axil_rdata[r_select];
+    assign int_axil.rresp  = r_decerr ? 2'b11 : int_m_axil_rresp[r_select];
+    assign int_axil.ruser  = r_decerr ? '0 : int_m_axil_ruser[r_select];
+    assign int_axil.rvalid = (r_decerr ? 1'b1 : int_axil_rvalid[r_select][m]) && r_valid;
+
+    always_comb begin
+        int_axil_rready[m] = '0;
+        int_axil_rready[m][r_select] = r_valid && int_axil.rready;
+    end
+
+    assign fifo_rd_en = int_axil.rvalid && int_axil.rready && r_valid;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(m_axil_rd[0].DATA_W),
+        .ADDR_W(m_axil_rd[0].ADDR_W),
+        .STRB_W(m_axil_rd[0].STRB_W),
+        .ARUSER_EN(m_axil_rd[0].ARUSER_EN),
+        .ARUSER_W(m_axil_rd[0].ARUSER_W),
+        .RUSER_EN(m_axil_rd[0].RUSER_EN),
+        .RUSER_W(m_axil_rd[0].RUSER_W)
+    ) int_axil();
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    wire [CL_S_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_en;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+        if (fifo_rd_en) begin
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+        end
+    end
+
+    // address arbitration
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    assign int_axil.araddr   = AXIL_M_ADDR_W'(int_s_axil_araddr[a_grant_index]);
+    assign int_axil.arprot   = int_s_axil_arprot[a_grant_index];
+    assign int_axil.aruser   = int_s_axil_aruser[a_grant_index];
+    assign int_axil.arvalid  = int_axil_arvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axil_arready[n] = '0;
+        int_axil_arready[n][a_grant_index] = a_grant_valid && int_axil.arready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axil_arvalid[m][n] && !a_grant_valid && !fifo_half_full_reg;
+        assign a_ack[m] = a_grant[m] && int_axil_arvalid[m][n] && int_axil.arready;
+    end
+
+    assign fifo_wr_select = a_grant_index;
+    assign fifo_wr_en = int_axil.arvalid && int_axil.arready && a_grant_valid;
+
+    // read response forwarding
+    wire [CL_S_COUNT_INT-1:0] r_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0;
+
+    assign int_m_axil_rdata[n] = int_axil.rdata;
+    assign int_m_axil_rresp[n] = int_axil.rresp;
+    assign int_m_axil_ruser[n] = int_axil.ruser;
+
+    always_comb begin
+        int_axil_rvalid[n] = '0;
+        int_axil_rvalid[n][r_select] = int_axil.rvalid;
+    end
+    assign int_axil.rready = int_axil_rready[r_select][n];
+
+    assign fifo_rd_en = int_axil.rvalid && int_axil.rready;
+
+    // M side register
+    taxi_axil_register_rd #(
+        .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+        .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_rd(int_axil),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_rd(m_axil_rd[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_crossbar_wr.f

@@ -0,0 +1,6 @@
+taxi_axil_crossbar_wr.sv
+taxi_axil_crossbar_addr.sv
+taxi_axil_register_wr.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_crossbar_wr.sv

@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite crossbar (write)
+ */
+module taxi_axil_crossbar_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    parameter M_ISSUE = {M_COUNT{32'd16}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    // Slave interface AW channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface W channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    // Slave interface B channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    // Master interface AW channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    // Master interface W channel register type (output)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    // Master interface B channel register type (input)
+    // 0 to bypass, 1 for simple buffer, 2 for skid buffer
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_wr[0].DATA_W;
+localparam S_ADDR_W = s_axil_wr[0].ADDR_W;
+localparam STRB_W = s_axil_wr[0].STRB_W;
+localparam logic AWUSER_EN = s_axil_wr[0].AWUSER_EN && m_axil_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axil_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axil_wr[0].WUSER_EN && m_axil_wr[0].WUSER_EN;
+localparam WUSER_W = s_axil_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
+localparam BUSER_W = s_axil_wr[0].BUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
+localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
+
+// check configuration
+if (s_axil_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+wire [ADDR_W-1:0]    int_s_axil_awaddr[S_COUNT];
+wire [2:0]           int_s_axil_awprot[S_COUNT];
+wire [AWUSER_W-1:0]  int_s_axil_awuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_awvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_awready[M_COUNT];
+
+wire [DATA_W-1:0]    int_s_axil_wdata[S_COUNT];
+wire [STRB_W-1:0]    int_s_axil_wstrb[S_COUNT];
+wire [WUSER_W-1:0]   int_s_axil_wuser[S_COUNT];
+
+logic [M_COUNT-1:0]  int_axil_wvalid[S_COUNT];
+logic [S_COUNT-1:0]  int_axil_wready[M_COUNT];
+
+wire [1:0]           int_m_axil_bresp[M_COUNT];
+wire [BUSER_W-1:0]   int_m_axil_buser[M_COUNT];
+
+logic [S_COUNT-1:0]  int_axil_bvalid[M_COUNT];
+logic [M_COUNT-1:0]  int_axil_bready[S_COUNT];
+
+for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(s_axil_wr[0].DATA_W),
+        .ADDR_W(s_axil_wr[0].ADDR_W),
+        .STRB_W(s_axil_wr[0].STRB_W),
+        .AWUSER_EN(s_axil_wr[0].AWUSER_EN),
+        .AWUSER_W(s_axil_wr[0].AWUSER_W),
+        .WUSER_EN(s_axil_wr[0].WUSER_EN),
+        .WUSER_W(s_axil_wr[0].WUSER_W),
+        .BUSER_EN(s_axil_wr[0].BUSER_EN),
+        .BUSER_W(s_axil_wr[0].BUSER_W)
+    ) int_axil();
+
+    // S side register
+    taxi_axil_register_wr #(
+        .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+        .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+        .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_wr(s_axil_wr[m]),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_wr(int_axil)
+    );
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic fifo_decerr[2**FIFO_AW];
+
+    wire [CL_M_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_decerr;
+    wire fifo_wr_en;
+
+    logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = '0;
+    logic fifo_rd_decerr_reg = 1'b0;
+    logic fifo_rd_valid_reg = 1'b0;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+            fifo_decerr[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+
+        fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en;
+
+        if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin
+            fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]];
+            fifo_rd_valid_reg <= 1'b1;
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+            fifo_rd_valid_reg <= 1'b0;
+        end
+    end
+
+    // address decode and admission control
+    wire [CL_M_COUNT_INT-1:0] a_select;
+
+    wire m_axil_avalid;
+    wire m_axil_aready;
+
+    wire [CL_M_COUNT_INT-1:0] m_wc_select;
+    wire m_wc_decerr;
+    wire m_wc_valid;
+    wire m_wc_ready;
+
+    wire [CL_M_COUNT_INT-1:0] m_rc_select;
+    wire m_rc_decerr;
+    wire m_rc_valid;
+    wire m_rc_ready;
+
+    taxi_axil_crossbar_addr #(
+        .S(m),
+        .S_COUNT(S_COUNT),
+        .M_COUNT(M_COUNT),
+        .SEL_W(CL_M_COUNT_INT),
+        .ADDR_W(ADDR_W),
+        .STRB_W(STRB_W),
+        .M_REGIONS(M_REGIONS),
+        .M_BASE_ADDR(M_BASE_ADDR),
+        .M_ADDR_W(M_ADDR_W),
+        .M_CONNECT(M_CONNECT),
+        .M_SECURE(M_SECURE),
+        .WC_OUTPUT(1)
+    )
+    addr_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * Address input
+         */
+        .s_axil_aaddr(int_axil.awaddr),
+        .s_axil_aprot(int_axil.awprot),
+        .s_axil_avalid(int_axil.awvalid),
+        .s_axil_aready(int_axil.awready),
+
+        /*
+         * Address output
+         */
+        .m_select(a_select),
+        .m_axil_avalid(m_axil_avalid),
+        .m_axil_aready(m_axil_aready),
+
+        /*
+         * Write command output
+         */
+        .m_wc_select(m_wc_select),
+        .m_wc_decerr(m_wc_decerr),
+        .m_wc_valid(m_wc_valid),
+        .m_wc_ready(m_wc_ready),
+
+        /*
+         * Response command output
+         */
+        .m_rc_select(m_rc_select),
+        .m_rc_decerr(m_rc_decerr),
+        .m_rc_valid(m_rc_valid),
+        .m_rc_ready(m_rc_ready)
+    );
+
+    assign int_s_axil_awaddr[m] = int_axil.awaddr;
+    assign int_s_axil_awprot[m] = int_axil.awprot;
+    assign int_s_axil_awuser[m] = int_axil.awuser;
+
+    always_comb begin
+        int_axil_awvalid[m] = '0;
+        int_axil_awvalid[m][a_select] = m_axil_avalid;
+    end
+    assign m_axil_aready = int_axil_awready[a_select][m];
+
+    // write command handling
+    logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_drop_reg = 1'b0, w_drop_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+
+    assign m_wc_ready = !w_select_valid_reg;
+
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_drop_next = w_drop_reg && !(int_axil.wvalid && int_axil.wready);
+        w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready);
+
+        if (m_wc_valid && !w_select_valid_reg) begin
+            w_select_next = m_wc_select;
+            w_drop_next = m_wc_decerr;
+            w_select_valid_next = m_wc_valid;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_reg <= w_select_next;
+        w_drop_reg <= w_drop_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+        end
+    end
+
+    // write data forwarding
+    assign int_s_axil_wdata[m] = int_axil.wdata;
+    assign int_s_axil_wstrb[m] = int_axil.wstrb;
+    assign int_s_axil_wuser[m] = int_axil.wuser;
+
+    always_comb begin
+        int_axil_wvalid[m] = '0;
+        int_axil_wvalid[m][w_select_reg] = int_axil.wvalid && w_select_valid_reg && !w_drop_reg;
+    end
+    assign int_axil.wready = int_axil_wready[w_select_reg][m] || w_drop_reg;
+
+    // response handling
+    assign fifo_wr_select = m_rc_select;
+    assign fifo_wr_decerr = m_rc_decerr;
+    assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg;
+    assign m_rc_ready = !fifo_half_full_reg;
+
+    // write response handling
+    wire [CL_M_COUNT_INT-1:0] b_select = M_COUNT > 1 ? fifo_rd_select_reg : '0;
+    wire b_decerr = fifo_rd_decerr_reg;
+    wire b_valid = fifo_rd_valid_reg;
+
+    // write response mux
+    assign int_axil.bresp = b_decerr ? 2'b11 : int_m_axil_bresp[b_select];
+    assign int_axil.buser = b_decerr ? '0 : int_m_axil_buser[b_select];
+    assign int_axil.bvalid = (b_decerr ? 1'b1 : int_axil_bvalid[b_select][m]) && b_valid;
+
+    always_comb begin
+        int_axil_bready[m] = '0;
+        int_axil_bready[m][b_select] = b_valid && int_axil.bready;
+    end
+
+    assign fifo_rd_en = int_axil.bvalid && int_axil.bready && b_valid;
+
+end // s_ifaces
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+
+    taxi_axil_if #(
+        .DATA_W(m_axil_wr[0].DATA_W),
+        .ADDR_W(m_axil_wr[0].ADDR_W),
+        .STRB_W(m_axil_wr[0].STRB_W),
+        .AWUSER_EN(m_axil_wr[0].AWUSER_EN),
+        .AWUSER_W(m_axil_wr[0].AWUSER_W),
+        .WUSER_EN(m_axil_wr[0].WUSER_EN),
+        .WUSER_W(m_axil_wr[0].WUSER_W),
+        .BUSER_EN(m_axil_wr[0].BUSER_EN),
+        .BUSER_W(m_axil_wr[0].BUSER_W)
+    ) int_axil();
+
+    // response routing FIFO
+    localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1;
+
+    logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
+    logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
+
+    (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+    logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW];
+    wire [CL_S_COUNT_INT-1:0] fifo_wr_select;
+    wire fifo_wr_en;
+    wire fifo_rd_en;
+    logic fifo_half_full_reg = 1'b0;
+
+    wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg;
+
+    initial begin
+        for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
+            fifo_select[i] = '0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (fifo_wr_en) begin
+            fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select;
+            fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1;
+        end
+        if (fifo_rd_en) begin
+            fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1;
+        end
+
+        fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
+
+        if (rst) begin
+            fifo_wr_ptr_reg <= '0;
+            fifo_rd_ptr_reg <= '0;
+        end
+    end
+
+    // address arbitration
+    logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
+    logic w_select_valid_reg = 1'b0, w_select_valid_next;
+    logic w_select_new_reg = 1'b0, w_select_new_next;
+
+    wire [S_COUNT-1:0] a_req;
+    wire [S_COUNT-1:0] a_ack;
+    wire [S_COUNT-1:0] a_grant;
+    wire a_grant_valid;
+    wire [CL_S_COUNT_INT-1:0] a_grant_index;
+
+    if (S_COUNT > 1) begin : arb
+
+        taxi_arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .LSB_HIGH_PRIO(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .req(a_req),
+            .ack(a_ack),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_index(a_grant_index)
+        );
+
+    end else begin
+
+        logic grant_valid_reg = 1'b0;
+
+        always @(posedge clk) begin
+            if (a_req) begin
+                grant_valid_reg <= 1'b1;
+            end
+
+            if (a_ack || rst) begin
+                grant_valid_reg <= 1'b0;
+            end
+        end
+
+        assign a_grant_valid = grant_valid_reg;
+        assign a_grant = grant_valid_reg;
+        assign a_grant_index = '0;
+
+    end
+
+    // address mux
+    assign int_axil.awaddr   = AXIL_M_ADDR_W'(int_s_axil_awaddr[a_grant_index]);
+    assign int_axil.awprot   = int_s_axil_awprot[a_grant_index];
+    assign int_axil.awuser   = int_s_axil_awuser[a_grant_index];
+    assign int_axil.awvalid  = int_axil_awvalid[a_grant_index][n] && a_grant_valid;
+
+    always_comb begin
+        int_axil_awready[n] = '0;
+        int_axil_awready[n][a_grant_index] = a_grant_valid && int_axil.awready;
+    end
+
+    for (genvar m = 0; m < S_COUNT; m = m + 1) begin
+        assign a_req[m] = int_axil_awvalid[m][n] && !a_grant_valid && !fifo_half_full_reg && !w_select_valid_next;
+        assign a_ack[m] = a_grant[m] && int_axil_awvalid[m][n] && int_axil.awready;
+    end
+
+    assign fifo_wr_select = a_grant_index;
+    assign fifo_wr_en = int_axil.awvalid && int_axil.awready && a_grant_valid;
+
+    // write data mux
+    assign int_axil.wdata   = int_s_axil_wdata[w_select_reg];
+    assign int_axil.wstrb   = int_s_axil_wstrb[w_select_reg];
+    assign int_axil.wuser   = int_s_axil_wuser[w_select_reg];
+    assign int_axil.wvalid  = int_axil_wvalid[w_select_reg][n] && w_select_valid_reg;
+
+    always_comb begin
+        int_axil_wready[n] = '0;
+        int_axil_wready[n][w_select_reg] = w_select_valid_reg && int_axil.wready;
+    end
+
+    // write data routing
+    always_comb begin
+        w_select_next = w_select_reg;
+        w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready);
+        w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0;
+
+        if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+            w_select_next = a_grant_index;
+            w_select_valid_next = a_grant_valid;
+            w_select_new_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        w_select_reg <= w_select_next;
+        w_select_valid_reg <= w_select_valid_next;
+        w_select_new_reg <= w_select_new_next;
+
+        if (rst) begin
+            w_select_valid_reg <= 1'b0;
+            w_select_new_reg <= 1'b1;
+        end
+    end
+
+    // write response forwarding
+    wire [CL_S_COUNT_INT-1:0] b_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0;
+
+    assign int_m_axil_bresp[n] = int_axil.bresp;
+    assign int_m_axil_buser[n] = int_axil.buser;
+
+    always_comb begin
+        int_axil_bvalid[n] = '0;
+        int_axil_bvalid[n][b_select] = int_axil.bvalid;
+    end
+    assign int_axil.bready = int_axil_bready[b_select][n];
+
+    assign fifo_rd_en = int_axil.bvalid && int_axil.bready;
+
+    // M side register
+    taxi_axil_register_wr #(
+        .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+        .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+        .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+    )
+    reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * AXI4-Lite slave interface
+         */
+        .s_axil_wr(int_axil),
+
+        /*
+         * AXI4-Lite master interface
+         */
+        .m_axil_wr(m_axil_wr[n])
+    );
+
+end // m_ifaces
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect.f

@@ -0,0 +1,6 @@
+taxi_axil_interconnect.sv
+taxi_axil_interconnect_rd.sv
+taxi_axil_interconnect_wr.sv
+taxi_axil_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axi/rtl/taxi_axil_interconnect.sv

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect
+ */
+module taxi_axil_interconnect #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Number of concurrent operations for each slave interface
+    // S_COUNT concatenated fields of 32 bits
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Number of concurrent operations for each master interface
+    // M_COUNT concatenated fields of 32 bits
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT],
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+taxi_axil_interconnect_wr #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    .s_axil_wr(s_axil_wr),
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    .m_axil_wr(m_axil_wr)
+);
+
+taxi_axil_interconnect_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT(M_CONNECT_RD),
+    .M_SECURE(M_SECURE)
+)
+rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    .s_axil_rd(s_axil_rd),
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    .m_axil_rd(m_axil_rd)
+);
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect_rd.sv

@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect (read)
+ */
+module taxi_axil_interconnect_rd #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Read connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.rd_slv  s_axil_rd[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.rd_mst  m_axil_rd[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_rd[0].DATA_W;
+localparam S_ADDR_W = s_axil_rd[0].ADDR_W;
+localparam STRB_W = s_axil_rd[0].STRB_W;
+localparam logic ARUSER_EN = s_axil_rd[0].ARUSER_EN && m_axil_rd[0].ARUSER_EN;
+localparam ARUSER_W = s_axil_rd[0].ARUSER_W;
+localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN;
+localparam RUSER_W = s_axil_rd[0].RUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_rd[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axil_rd[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_rd[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_DECODE = 2'd1,
+    STATE_READ = 2'd2,
+    STATE_WAIT_IDLE = 2'd3;
+
+logic [1:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [ADDR_W-1:0] axil_araddr_reg = '0, axil_araddr_next;
+logic axil_araddr_valid_reg = 1'b0, axil_araddr_valid_next;
+logic [2:0] axil_arprot_reg = 3'b000, axil_arprot_next;
+logic [ARUSER_W-1:0] axil_aruser_reg = '0, axil_aruser_next;
+logic [DATA_W-1:0] axil_rdata_reg = '0, axil_rdata_next;
+logic [1:0] axil_rresp_reg = 2'b00, axil_rresp_next;
+logic [RUSER_W-1:0] axil_ruser_reg = '0, axil_ruser_next;
+
+logic [S_COUNT-1:0] s_axil_arready_reg = '0, s_axil_arready_next;
+logic [S_COUNT-1:0] s_axil_rvalid_reg = '0, s_axil_rvalid_next;
+
+logic [M_COUNT-1:0] m_axil_arvalid_reg = '0, m_axil_arvalid_next;
+logic [M_COUNT-1:0] m_axil_rready_reg = '0, m_axil_rready_next;
+
+// unpack interface array
+wire [ADDR_W-1:0]    s_axil_araddr[S_COUNT];
+wire [2:0]           s_axil_arprot[S_COUNT];
+wire [ARUSER_W-1:0]  s_axil_aruser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_arvalid;
+wire [S_COUNT-1:0]   s_axil_rready;
+
+wire [M_COUNT-1:0]   m_axil_arready;
+wire [DATA_W-1:0]    m_axil_rdata[M_COUNT];
+wire [1:0]           m_axil_rresp[M_COUNT];
+wire [RUSER_W-1:0]   m_axil_ruser[M_COUNT];
+wire [M_COUNT-1:0]   m_axil_rvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axil_araddr[n] = s_axil_rd[n].araddr;
+    assign s_axil_arprot[n] = s_axil_rd[n].arprot;
+    assign s_axil_aruser[n] = s_axil_rd[n].aruser;
+    assign s_axil_arvalid[n] = s_axil_rd[n].arvalid;
+    assign s_axil_rd[n].arready = s_axil_arready_reg[n];
+    assign s_axil_rd[n].rdata = axil_rdata_reg;
+    assign s_axil_rd[n].rresp = axil_rresp_reg;
+    assign s_axil_rd[n].ruser = RUSER_EN ? axil_ruser_reg : '0;
+    assign s_axil_rd[n].rvalid = s_axil_rvalid_reg[n];
+    assign s_axil_rready[n] = s_axil_rd[n].rready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axil_rd[n].araddr = AXIL_M_ADDR_W'(axil_araddr_reg);
+    assign m_axil_rd[n].arprot = axil_arprot_reg;
+    assign m_axil_rd[n].aruser = ARUSER_EN ? axil_aruser_reg : '0;
+    assign m_axil_rd[n].arvalid = m_axil_arvalid_reg[n];
+    assign m_axil_arready[n] = m_axil_rd[n].arready;
+    assign m_axil_rdata[n] = m_axil_rd[n].rdata;
+    assign m_axil_rresp[n] = m_axil_rd[n].rresp;
+    assign m_axil_ruser[n] = m_axil_rd[n].ruser;
+    assign m_axil_rvalid[n] = m_axil_rd[n].rvalid;
+    assign m_axil_rd[n].rready = m_axil_rready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [ADDR_W-1:0]    current_s_axil_araddr  = s_axil_araddr[s_select];
+wire [2:0]           current_s_axil_arprot  = s_axil_arprot[s_select];
+wire [ARUSER_W-1:0]  current_s_axil_aruser  = s_axil_aruser[s_select];
+wire                 current_s_axil_arvalid = s_axil_arvalid[s_select];
+wire                 current_s_axil_rready  = s_axil_rready[s_select];
+
+// master side mux
+wire                 current_m_axil_arready = m_axil_arready[m_select_reg];
+wire [DATA_W-1:0]    current_m_axil_rdata   = m_axil_rdata[m_select_reg];
+wire [1:0]           current_m_axil_rresp   = m_axil_rresp[m_select_reg];
+wire [RUSER_W-1:0]   current_m_axil_ruser   = m_axil_ruser[m_select_reg];
+wire                 current_m_axil_rvalid  = m_axil_rvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+// req generation
+assign req = s_axil_arvalid;
+assign ack = grant & s_axil_rvalid_reg & s_axil_rready;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axil_araddr_next = axil_araddr_reg;
+    axil_araddr_valid_next = axil_araddr_valid_reg;
+    axil_arprot_next = axil_arprot_reg;
+    axil_aruser_next = axil_aruser_reg;
+    axil_rdata_next = axil_rdata_reg;
+    axil_rresp_next = axil_rresp_reg;
+    axil_ruser_next = axil_ruser_reg;
+
+    s_axil_arready_next = '0;
+    s_axil_rvalid_next = s_axil_rvalid_reg & ~s_axil_rready;
+
+    m_axil_arvalid_next = m_axil_arvalid_reg & ~m_axil_arready;
+    m_axil_rready_next = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+            axil_araddr_valid_next = 1'b1;
+            axil_araddr_next = current_s_axil_araddr;
+            axil_arprot_next = current_s_axil_arprot;
+            axil_aruser_next = current_s_axil_aruser;
+
+            if (grant_valid) begin
+                s_axil_arready_next[s_select] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axil_arprot_reg[1]) && M_CONNECT_INT[i][s_select] && (axil_araddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            axil_rdata_next = '0;
+            axil_rresp_next = 2'b11;
+
+            if (match) begin
+                m_axil_rready_next[m_select_next] = 1'b1;
+                state_next = STATE_READ;
+            end else begin
+                // no match; return decode error
+                s_axil_rvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        STATE_READ: begin
+            // read state; store and forward read response
+            m_axil_rready_next[m_select_reg] = 1'b1;
+
+            if (axil_araddr_valid_reg) begin
+                m_axil_arvalid_next[m_select_reg] = 1'b1;
+            end
+            axil_araddr_valid_next = 1'b0;
+
+            if (m_axil_rready_reg != 0 && current_m_axil_rvalid) begin
+                m_axil_rready_next[m_select_reg] = 1'b0;
+                axil_rdata_next = current_m_axil_rdata;
+                axil_rresp_next = current_m_axil_rresp;
+                axil_ruser_next = current_m_axil_ruser;
+                s_axil_rvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_READ;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait until grant valid is deasserted
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_select_reg <= m_select_next;
+
+    axil_araddr_reg <= axil_araddr_next;
+    axil_araddr_valid_reg <= axil_araddr_valid_next;
+    axil_arprot_reg <= axil_arprot_next;
+    axil_aruser_reg <= axil_aruser_next;
+    axil_rdata_reg <= axil_rdata_next;
+    axil_rresp_reg <= axil_rresp_next;
+    axil_ruser_reg <= axil_ruser_next;
+
+    s_axil_arready_reg <= s_axil_arready_next;
+    s_axil_rvalid_reg <= s_axil_rvalid_next;
+
+    m_axil_arvalid_reg <= m_axil_arvalid_next;
+    m_axil_rready_reg <= m_axil_rready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axil_arready_reg <= '0;
+        s_axil_rvalid_reg <= '0;
+
+        m_axil_arvalid_reg <= '0;
+        m_axil_rready_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/rtl/taxi_axil_interconnect_wr.sv

@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite interconnect (write)
+ */
+module taxi_axil_interconnect_wr #
+(
+    // Number of AXI inputs (slave interfaces)
+    parameter S_COUNT = 4,
+    // Number of AXI outputs (master interfaces)
+    parameter M_COUNT = 4,
+    // Address width in bits for address decoding
+    parameter ADDR_W = 32,
+    // Number of regions per master interface
+    parameter M_REGIONS = 1,
+    // TODO fix parametrization once verilator issue 5890 is fixed
+    // Master interface base addresses
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
+    // set to zero for default addressing based on M_ADDR_W
+    parameter M_BASE_ADDR = '0,
+    // Master interface address widths
+    // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    // Write connections between interfaces
+    // M_COUNT concatenated fields of S_COUNT bits
+    parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
+    // Secure master (fail operations based on awprot/arprot)
+    // M_COUNT bits
+    parameter M_SECURE = {M_COUNT{1'b0}}
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-lite slave interfaces
+     */
+    taxi_axil_if.wr_slv  s_axil_wr[S_COUNT],
+
+    /*
+     * AXI4-lite master interfaces
+     */
+    taxi_axil_if.wr_mst  m_axil_wr[M_COUNT]
+);
+
+// extract parameters
+localparam DATA_W = s_axil_wr[0].DATA_W;
+localparam S_ADDR_W = s_axil_wr[0].ADDR_W;
+localparam STRB_W = s_axil_wr[0].STRB_W;
+localparam logic AWUSER_EN = s_axil_wr[0].AWUSER_EN && m_axil_wr[0].AWUSER_EN;
+localparam AWUSER_W = s_axil_wr[0].AWUSER_W;
+localparam logic WUSER_EN = s_axil_wr[0].WUSER_EN && m_axil_wr[0].WUSER_EN;
+localparam WUSER_W = s_axil_wr[0].WUSER_W;
+localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN;
+localparam BUSER_W = s_axil_wr[0].BUSER_W;
+
+localparam AXIL_M_ADDR_W = m_axil_wr[0].ADDR_W;
+
+localparam CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
+localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
+
+localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
+localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
+localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
+
+// default address computation
+function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
+    logic [ADDR_W-1:0] base;
+    integer width;
+    logic [ADDR_W-1:0] size;
+    logic [ADDR_W-1:0] mask;
+    begin
+        calcBaseAddrs = '0;
+        base = '0;
+        for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+            width = M_ADDR_W_INT[i];
+            mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
+            size = mask + 1;
+            if (width > 0) begin
+                if ((base & mask) != 0) begin
+                    base = base + size - (base & mask); // align
+                end
+                calcBaseAddrs[i] = base;
+                base = base + size; // increment
+            end
+        end
+    end
+endfunction
+
+localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
+
+// check configuration
+if (s_axil_wr[0].ADDR_W != ADDR_W)
+    $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_wr[0].STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+initial begin
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        /* verilator lint_off UNSIGNED */
+        if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
+            $error("Error: address width out of range (instance %m)");
+            $finish;
+        end
+        /* verilator lint_on UNSIGNED */
+    end
+
+    $display("Addressing configuration for axil_interconnect instance %m");
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if (M_ADDR_W_INT[i] != 0) begin
+            $display("%2d (%2d): %x / %02d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i],
+                M_ADDR_W_INT[i],
+                M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end
+    end
+
+    for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
+                if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
+                        && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i],
+                        M_ADDR_W_INT[i],
+                        M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
+                        M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j],
+                        M_ADDR_W_INT[j],
+                        M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
+                        M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end
+        end
+    end
+end
+
+localparam logic [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1,
+    STATE_WRITE = 3'd2,
+    STATE_WRITE_RESP = 3'd3,
+    STATE_WRITE_DROP = 3'd4,
+    STATE_WAIT_IDLE = 3'd5;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+logic match;
+
+logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
+logic [ADDR_W-1:0] axil_awaddr_reg = '0, axil_awaddr_next;
+logic axil_awaddr_valid_reg = 1'b0, axil_awaddr_valid_next;
+logic [2:0] axil_awprot_reg = 3'b000, axil_awprot_next;
+logic [AWUSER_W-1:0] axil_awuser_reg = '0, axil_awuser_next;
+logic [DATA_W-1:0] axil_wdata_reg = '0, axil_wdata_next;
+logic [STRB_W-1:0] axil_wstrb_reg = '0, axil_wstrb_next;
+logic [WUSER_W-1:0] axil_wuser_reg = '0, axil_wuser_next;
+logic [1:0] axil_bresp_reg = 2'b00, axil_bresp_next;
+logic [BUSER_W-1:0] axil_buser_reg = '0, axil_buser_next;
+
+logic [S_COUNT-1:0] s_axil_awready_reg = '0, s_axil_awready_next;
+logic [S_COUNT-1:0] s_axil_wready_reg = '0, s_axil_wready_next;
+logic [S_COUNT-1:0] s_axil_bvalid_reg = '0, s_axil_bvalid_next;
+
+logic [M_COUNT-1:0] m_axil_awvalid_reg = '0, m_axil_awvalid_next;
+logic [M_COUNT-1:0] m_axil_wvalid_reg = '0, m_axil_wvalid_next;
+logic [M_COUNT-1:0] m_axil_bready_reg = '0, m_axil_bready_next;
+
+// unpack interface array
+wire [ADDR_W-1:0]    s_axil_awaddr[S_COUNT];
+wire [2:0]           s_axil_awprot[S_COUNT];
+wire [AWUSER_W-1:0]  s_axil_awuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_awvalid;
+wire [DATA_W-1:0]    s_axil_wdata[S_COUNT];
+wire [STRB_W-1:0]    s_axil_wstrb[S_COUNT];
+wire [WUSER_W-1:0]   s_axil_wuser[S_COUNT];
+wire [S_COUNT-1:0]   s_axil_wvalid;
+wire [S_COUNT-1:0]   s_axil_bready;
+
+wire [M_COUNT-1:0]   m_axil_awready;
+wire [M_COUNT-1:0]   m_axil_wready;
+wire [1:0]           m_axil_bresp[M_COUNT];
+wire [BUSER_W-1:0]   m_axil_buser[M_COUNT];
+wire [M_COUNT-1:0]   m_axil_bvalid;
+
+for (genvar n = 0; n < S_COUNT; n = n + 1) begin
+    assign s_axil_awaddr[n] = s_axil_wr[n].awaddr;
+    assign s_axil_awprot[n] = s_axil_wr[n].awprot;
+    assign s_axil_awuser[n] = s_axil_wr[n].awuser;
+    assign s_axil_awvalid[n] = s_axil_wr[n].awvalid;
+    assign s_axil_wr[n].awready = s_axil_awready_reg[n];
+    assign s_axil_wdata[n] = s_axil_wr[n].wdata;
+    assign s_axil_wstrb[n] = s_axil_wr[n].wstrb;
+    assign s_axil_wuser[n] = s_axil_wr[n].wuser;
+    assign s_axil_wvalid[n] = s_axil_wr[n].wvalid;
+    assign s_axil_wr[n].wready = s_axil_wready_reg[n];
+    assign s_axil_wr[n].bresp = axil_bresp_reg;
+    assign s_axil_wr[n].buser = BUSER_EN ? axil_buser_reg : '0;
+    assign s_axil_wr[n].bvalid = s_axil_bvalid_reg[n];
+    assign s_axil_bready[n] = s_axil_wr[n].bready;
+end
+
+for (genvar n = 0; n < M_COUNT; n = n + 1) begin
+    assign m_axil_wr[n].awaddr = AXIL_M_ADDR_W'(axil_awaddr_reg);
+    assign m_axil_wr[n].awprot = axil_awprot_reg;
+    assign m_axil_wr[n].awuser = AWUSER_EN ? axil_awuser_reg : '0;
+    assign m_axil_wr[n].awvalid = m_axil_awvalid_reg[n];
+    assign m_axil_awready[n] = m_axil_wr[n].awready;
+    assign m_axil_wr[n].wdata = axil_wdata_reg;
+    assign m_axil_wr[n].wstrb = axil_wstrb_reg;
+    assign m_axil_wr[n].wuser = AWUSER_EN ? axil_wuser_reg : '0;
+    assign m_axil_wr[n].wvalid = m_axil_wvalid_reg[n];
+    assign m_axil_wready[n] = m_axil_wr[n].wready;
+    assign m_axil_bresp[n] = m_axil_wr[n].bresp;
+    assign m_axil_buser[n] = m_axil_wr[n].buser;
+    assign m_axil_bvalid[n] = m_axil_wr[n].bvalid;
+    assign m_axil_wr[n].bready = m_axil_bready_reg[n];
+end
+
+// slave side mux
+wire [CL_S_COUNT_INT-1:0] s_select;
+
+wire [ADDR_W-1:0]    current_s_axil_awaddr  = s_axil_awaddr[s_select];
+wire [2:0]           current_s_axil_awprot  = s_axil_awprot[s_select];
+wire [AWUSER_W-1:0]  current_s_axil_awuser  = s_axil_awuser[s_select];
+wire                 current_s_axil_awvalid = s_axil_awvalid[s_select];
+wire [DATA_W-1:0]    current_s_axil_wdata   = s_axil_wdata[s_select];
+wire [STRB_W-1:0]    current_s_axil_wstrb   = s_axil_wstrb[s_select];
+wire [WUSER_W-1:0]   current_s_axil_wuser   = s_axil_wuser[s_select];
+wire                 current_s_axil_wvalid  = s_axil_wvalid[s_select];
+wire                 current_s_axil_bready  = s_axil_bready[s_select];
+
+// master side mux
+wire                 current_m_axil_awready = m_axil_awready[m_select_reg];
+wire                 current_m_axil_wready  = m_axil_wready[m_select_reg];
+wire [1:0]           current_m_axil_bresp   = m_axil_bresp[m_select_reg];
+wire [BUSER_W-1:0]   current_m_axil_buser   = m_axil_buser[m_select_reg];
+wire                 current_m_axil_bvalid  = m_axil_bvalid[m_select_reg];
+
+// arbiter instance
+wire [S_COUNT-1:0] req;
+wire [S_COUNT-1:0] ack;
+wire [S_COUNT-1:0] grant;
+wire grant_valid;
+wire [CL_S_COUNT_INT-1:0] grant_index;
+
+assign s_select = grant_index;
+
+if (S_COUNT > 1) begin : arb
+
+    taxi_arbiter #(
+        .PORTS(S_COUNT),
+        .ARB_ROUND_ROBIN(1),
+        .ARB_BLOCK(1),
+        .ARB_BLOCK_ACK(1),
+        .LSB_HIGH_PRIO(1)
+    )
+    arb_inst (
+        .clk(clk),
+        .rst(rst),
+        .req(req),
+        .ack(ack),
+        .grant(grant),
+        .grant_valid(grant_valid),
+        .grant_index(grant_index)
+    );
+
+end else begin
+
+    logic grant_valid_reg = 1'b0;
+
+    always @(posedge clk) begin
+        if (req) begin
+            grant_valid_reg <= 1'b1;
+        end
+
+        if (ack || rst) begin
+            grant_valid_reg <= 1'b0;
+        end
+    end
+
+    assign grant_valid = grant_valid_reg;
+    assign grant = '1;
+    assign grant_index = '0;
+
+end
+
+assign req = s_axil_awvalid;
+assign ack = grant & s_axil_bvalid_reg & s_axil_bready;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    match = 1'b0;
+
+    m_select_next = m_select_reg;
+    axil_awaddr_next = axil_awaddr_reg;
+    axil_awaddr_valid_next = axil_awaddr_valid_reg;
+    axil_awprot_next = axil_awprot_reg;
+    axil_awuser_next = axil_awuser_reg;
+    axil_wdata_next = axil_wdata_reg;
+    axil_wstrb_next = axil_wstrb_reg;
+    axil_wuser_next = axil_wuser_reg;
+    axil_bresp_next = axil_bresp_reg;
+    axil_buser_next = axil_buser_reg;
+
+    s_axil_awready_next = '0;
+    s_axil_wready_next = '0;
+    s_axil_bvalid_next = s_axil_bvalid_reg & ~s_axil_bready;
+
+    m_axil_awvalid_next = m_axil_awvalid_reg & ~m_axil_awready;
+    m_axil_wvalid_next = m_axil_wvalid_reg & ~m_axil_wready;
+    m_axil_bready_next = '0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state; wait for arbitration
+            axil_awaddr_valid_next = 1'b1;
+            axil_awaddr_next = current_s_axil_awaddr;
+            axil_awprot_next = current_s_axil_awprot;
+            axil_awuser_next = current_s_axil_awuser;
+
+            if (grant_valid) begin
+                s_axil_awready_next[grant_index] = 1'b1;
+                state_next = STATE_DECODE;
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_DECODE: begin
+            // decode state; determine master interface
+
+            match = 1'b0;
+            for (integer i = 0; i < M_COUNT; i = i + 1) begin
+                for (integer j = 0; j < M_REGIONS; j = j + 1) begin
+                    if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axil_awprot_reg[1]) && M_CONNECT_INT[i][s_select] && (axil_awaddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
+                        m_select_next = CL_M_COUNT_INT'(i);
+                        match = 1'b1;
+                    end
+                end
+            end
+
+            s_axil_wready_next[s_select] = 1'b1;
+
+            if (match) begin
+                state_next = STATE_WRITE;
+            end else begin
+                // no match; return decode error
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WRITE: begin
+            // write state; store and forward write data
+            s_axil_wready_next[s_select] = 1'b1;
+
+            if (axil_awaddr_valid_reg) begin
+                m_axil_awvalid_next[m_select_reg] = 1'b1;
+            end
+            axil_awaddr_valid_next = 1'b0;
+
+            axil_wdata_next = current_s_axil_wdata;
+            axil_wstrb_next = current_s_axil_wstrb;
+            axil_wuser_next = current_s_axil_wuser;
+
+            if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
+                s_axil_wready_next[s_select] = 1'b0;
+                m_axil_wvalid_next[m_select_reg] = 1'b1;
+                m_axil_bready_next[m_select_reg] = 1'b1;
+                state_next = STATE_WRITE_RESP;
+            end else begin
+                state_next = STATE_WRITE;
+            end
+        end
+        STATE_WRITE_RESP: begin
+            // write response state; store and forward write response
+            m_axil_bready_next[m_select_reg] = 1'b1;
+
+            axil_bresp_next = current_m_axil_bresp;
+            axil_buser_next = current_m_axil_buser;
+
+            if (m_axil_bready_reg != 0 && current_m_axil_bvalid) begin
+                m_axil_bready_next[m_select_reg] = 1'b0;
+                s_axil_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_RESP;
+            end
+        end
+        STATE_WRITE_DROP: begin
+            // write drop state; drop write data
+            s_axil_wready_next[s_select] = 1'b1;
+
+            axil_awaddr_valid_next = 1'b0;
+
+            axil_bresp_next = 2'b11;
+            axil_buser_next = '0;
+
+            if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
+                s_axil_wready_next[s_select] = 1'b0;
+                s_axil_bvalid_next[s_select] = 1'b1;
+                state_next = STATE_WAIT_IDLE;
+            end else begin
+                state_next = STATE_WRITE_DROP;
+            end
+        end
+        STATE_WAIT_IDLE: begin
+            // wait for idle state; wait until grant valid is deasserted
+
+            if (grant_valid == 0 || ack != 0) begin
+                state_next = STATE_IDLE;
+            end else begin
+                state_next = STATE_WAIT_IDLE;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_select_reg <= m_select_next;
+
+    axil_awaddr_reg <= axil_awaddr_next;
+    axil_awaddr_valid_reg <= axil_awaddr_valid_next;
+    axil_awprot_reg <= axil_awprot_next;
+    axil_awuser_reg <= axil_awuser_next;
+    axil_wdata_reg <= axil_wdata_next;
+    axil_wstrb_reg <= axil_wstrb_next;
+    axil_wuser_reg <= axil_wuser_next;
+    axil_bresp_reg <= axil_bresp_next;
+    axil_buser_reg <= axil_buser_next;
+
+    s_axil_awready_reg <= s_axil_awready_next;
+    s_axil_wready_reg <= s_axil_wready_next;
+    s_axil_bvalid_reg <= s_axil_bvalid_next;
+
+    m_axil_awvalid_reg <= m_axil_awvalid_next;
+    m_axil_wvalid_reg <= m_axil_wvalid_next;
+    m_axil_bready_reg <= m_axil_bready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axil_awready_reg <= '0;
+        s_axil_wready_reg <= '0;
+        s_axil_bvalid_reg <= '0;
+
+        m_axil_awvalid_reg <= '0;
+        m_axil_wvalid_reg <= '0;
+        m_axil_bready_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axi_crossbar/Makefile

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axi_crossbar
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_S_ID_W := 8
+export PARAM_M_ID_W := $(shell expr $(PARAM_S_ID_W) + 2 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.py

@@ -0,0 +1,281 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axi_master = [AxiMaster(AxiBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axi]
+        self.axi_ram = [AxiRam(AxiBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axi]
+
+        for ram in self.axi_ram:
+            # prevent X propagation from screwing things up - "anything but X!"
+            # (X on bid and rid can propagate X to ready/valid)
+            ram.write_if.b_channel.bus.bid.setimmediatevalue(0)
+            ram.read_if.r_channel.bus.rid.setimmediatevalue(0)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axi_master[s].write(addr, test_data, size=size)
+
+            tb.log.debug("%s", tb.axi_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axi_ram[m].read(ram_addr, length) == test_data
+            assert tb.axi_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axi_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axi_master[s].read(addr, length, size=size)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axi_ram))
+            length = random.randint(1, min(512, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axi)
+    m_count = len(cocotb.top.m_axi)
+
+    data_w = len(cocotb.top.s_axi[0].wdata)
+    byte_lanes = data_w // 8
+    max_burst_size = (byte_lanes-1).bit_length()
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        # factory.add_option("size", [None]+list(range(max_burst_size)))
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axi_crossbar(request, s_count, m_count, data_w):
+    dut = "taxi_axi_crossbar"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['S_ID_W'] = 8
+    parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.sv

@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 crossbar testbench
+ */
+module test_taxi_axi_crossbar #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter S_ID_W = 8,
+    parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter S_THREADS = {S_COUNT{32'd2}},
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(S_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axi[S_COUNT]();
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(M_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axi[M_COUNT]();
+
+taxi_axi_crossbar #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE),
+    .M_AW_REG_TYPE(M_AW_REG_TYPE),
+    .M_W_REG_TYPE(M_W_REG_TYPE),
+    .M_B_REG_TYPE(M_B_REG_TYPE),
+    .M_AR_REG_TYPE(M_AR_REG_TYPE),
+    .M_R_REG_TYPE(M_R_REG_TYPE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interface
+     */
+    .s_axi_wr(s_axi),
+    .s_axi_rd(s_axi),
+
+    /*
+     * AXI4 master interface
+     */
+    .m_axi_wr(m_axi),
+    .m_axi_rd(m_axi)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axi_interconnect/Makefile

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axi_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_S_ID_W := 8
+export PARAM_M_ID_W := $(shell expr $(PARAM_S_ID_W) + 2 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.py

@@ -0,0 +1,275 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axi_master = [AxiMaster(AxiBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axi]
+        self.axi_ram = [AxiRam(AxiBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axi]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axi_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axi_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axi_master[s].write(addr, test_data, size=size)
+
+            tb.log.debug("%s", tb.axi_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axi_ram[m].read(ram_addr, length) == test_data
+            assert tb.axi_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axi_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master[s].write_if.byte_lanes
+    max_burst_size = tb.axi_master[s].write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axi_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axi_master[s].read(addr, length, size=size)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axi_ram))
+            length = random.randint(1, min(512, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axi)
+    m_count = len(cocotb.top.m_axi)
+
+    data_w = len(cocotb.top.s_axi[0].wdata)
+    byte_lanes = data_w // 8
+    max_burst_size = (byte_lanes-1).bit_length()
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        # factory.add_option("size", [None]+list(range(max_burst_size)))
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axi_interconnect(request, s_count, m_count, data_w):
+    dut = "taxi_axi_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['S_ID_W'] = 8
+    parameters['M_ID_W'] = parameters['S_ID_W']
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 interconnect testbench
+ */
+module test_taxi_axi_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter S_ID_W = 8,
+    parameter M_ID_W = S_ID_W,
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_SECURE = {M_COUNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(S_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axi[S_COUNT]();
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .ID_W(M_ID_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axi[M_COUNT]();
+
+taxi_axi_interconnect #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4 slave interface
+     */
+    .s_axi_wr(s_axi),
+    .s_axi_rd(s_axi),
+
+    /*
+     * AXI4 master interface
+     */
+    .m_axi_wr(m_axi),
+    .m_axi_rd(m_axi)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axil_crossbar/Makefile

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axil_crossbar
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.py

@@ -0,0 +1,260 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axil_master = [AxiLiteMaster(AxiLiteBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axil]
+        self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axil_master[s].write(addr, test_data)
+
+            tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram[m].read(ram_addr, length) == test_data
+            assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axil_master[s].read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axil_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axil)
+    m_count = len(cocotb.top.m_axil)
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axil_crossbar(request, s_count, m_count, data_w):
+    dut = "taxi_axil_crossbar"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv

@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-lite crossbar testbench
+ */
+module test_taxi_axil_crossbar #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter S_ACCEPT = {S_COUNT{32'd16}},
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_ISSUE = {M_COUNT{32'd4}},
+    parameter M_SECURE = {M_COUNT{1'b0}},
+    parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
+    parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
+    parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
+    parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
+    parameter M_B_REG_TYPE = {M_COUNT{2'd0}},
+    parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
+    parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axil[S_COUNT]();
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axil[M_COUNT]();
+
+taxi_axil_crossbar #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AW_REG_TYPE(S_AW_REG_TYPE),
+    .S_W_REG_TYPE(S_W_REG_TYPE),
+    .S_B_REG_TYPE(S_B_REG_TYPE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE(S_R_REG_TYPE),
+    .M_AW_REG_TYPE(M_AW_REG_TYPE),
+    .M_W_REG_TYPE(M_W_REG_TYPE),
+    .M_B_REG_TYPE(M_B_REG_TYPE),
+    .M_AR_REG_TYPE(M_AR_REG_TYPE),
+    .M_R_REG_TYPE(M_R_REG_TYPE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interface
+     */
+    .s_axil_wr(s_axil),
+    .s_axil_rd(s_axil),
+
+    /*
+     * AXI4-lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall

src/axi/tb/taxi_axil_interconnect/Makefile

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axil_interconnect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_COUNT := 4
+export PARAM_M_COUNT := 4
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_M_REGIONS := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-WIDTH
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.py

@@ -0,0 +1,260 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axil_master = [AxiLiteMaster(AxiLiteBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axil]
+        self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil]
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.aw_channel.set_pause_generator(generator())
+                master.write_if.w_channel.set_pause_generator(generator())
+                master.read_if.ar_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.b_channel.set_pause_generator(generator())
+                ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            for master in self.axil_master:
+                master.write_if.b_channel.set_pause_generator(generator())
+                master.read_if.r_channel.set_pause_generator(generator())
+            for ram in self.axil_ram:
+                ram.write_if.aw_channel.set_pause_generator(generator())
+                ram.write_if.w_channel.set_pause_generator(generator())
+                ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256))
+
+            await tb.axil_master[s].write(addr, test_data)
+
+            tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram[m].read(ram_addr, length) == test_data
+            assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa'
+            assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master[s].write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            ram_addr = offset+0x1000
+            addr = ram_addr + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram[m].write(ram_addr, test_data)
+
+            data = await tb.axil_master[s].read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            m = random.randrange(len(tb.axil_ram))
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length) + m*0x1000000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if getattr(cocotb, 'top', None) is not None:
+
+    s_count = len(cocotb.top.s_axil)
+    m_count = len(cocotb.top.m_axil)
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("s", range(min(s_count, 2)))
+        factory.add_option("m", range(min(m_count, 2)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+@pytest.mark.parametrize("m_count", [1, 4])
+@pytest.mark.parametrize("s_count", [1, 4])
+def test_taxi_axil_interconnect(request, s_count, m_count, data_w):
+    dut = "taxi_axil_interconnect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_COUNT'] = s_count
+    parameters['M_COUNT'] = m_count
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['M_REGIONS'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.sv

@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-lite interconnect testbench
+ */
+module test_taxi_axil_interconnect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_COUNT = 4,
+    parameter M_COUNT = 4,
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter STRB_W = (DATA_W/8),
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter M_REGIONS = 1,
+    parameter M_BASE_ADDR = '0,
+    parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
+    parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}},
+    parameter M_SECURE = {M_COUNT{1'b0}}
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axil[S_COUNT]();
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .STRB_W(STRB_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) m_axil[M_COUNT]();
+
+taxi_axil_interconnect #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .ADDR_W(ADDR_W),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_W(M_ADDR_W),
+    .M_CONNECT_RD(M_CONNECT_RD),
+    .M_CONNECT_WR(M_CONNECT_WR),
+    .M_SECURE(M_SECURE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-lite slave interface
+     */
+    .s_axil_wr(s_axil),
+    .s_axil_rd(s_axil),
+
+    /*
+     * AXI4-lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall

src/axis/rtl/taxi_axis_async_fifo.sv

@@ -142,6 +142,12 @@ if (m_axis.DATA_W != DATA_W)
 if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
     $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
 
+if (DROP_BAD_FRAME && !s_axis.USER_EN)
+    $fatal(0, "Error: DROP_BAD_FRAME set requires s_axis.USER_EN (instance %m)");
+
+if (MARK_WHEN_FULL && !m_axis.USER_EN)
+    $fatal(0, "Error: MARK_WHEN_FULL set requires m_axis.USER_EN (instance %m)");
+
 localparam KEEP_OFFSET = DATA_W;
 localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
 localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
@@ -645,7 +651,7 @@ always_ff @(posedge m_clk) begin
             mem_rd_valid_pipe_reg[0] <= 1'b1;
             rd_ptr_temp = rd_ptr_reg + 1;
             rd_ptr_reg <= rd_ptr_temp;
-            rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
+            rd_ptr_gray_reg <= bin2gray(rd_ptr_temp);;
         end
     end
 

src/axis/rtl/taxi_axis_broadcast.sv

@@ -105,7 +105,7 @@ end
 // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
 wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid));
 
-always @* begin
+always_comb begin
     // transfer sink ready state to source
     m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
     temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
@@ -133,7 +133,7 @@ always @* begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     s_axis_tready_reg <= s_axis_tready_early;
     m_axis_tvalid_reg <= m_axis_tvalid_next;
     temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;

src/axis/rtl/taxi_axis_cobs_encode.sv

@@ -141,7 +141,7 @@ data_fifo_inst (
     .status_good_frame()
 );
 
-always @* begin
+always_comb begin
     input_state_next = INPUT_STATE_IDLE;
 
     input_count_next = input_count_reg;
@@ -304,7 +304,7 @@ always @* begin
     endcase
 end
 
-always @* begin
+always_comb begin
     output_state_next = OUTPUT_STATE_IDLE;
 
     output_count_next = output_count_reg;
@@ -365,7 +365,7 @@ always @* begin
     endcase
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     input_state_reg <= input_state_next;
     output_state_reg <= output_state_next;
 
@@ -380,20 +380,20 @@ always @(posedge clk) begin
 end
 
 // output datapath logic
-reg [7:0] m_axis_tdata_reg = 8'd0;
-reg       m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
-reg       m_axis_tlast_reg = 1'b0;
-reg       m_axis_tuser_reg = 1'b0;
+logic [7:0] m_axis_tdata_reg = 8'd0;
+logic       m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+logic       m_axis_tlast_reg = 1'b0;
+logic       m_axis_tuser_reg = 1'b0;
 
-reg [7:0] temp_m_axis_tdata_reg = 8'd0;
-reg       temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
-reg       temp_m_axis_tlast_reg = 1'b0;
-reg       temp_m_axis_tuser_reg = 1'b0;
+logic [7:0] temp_m_axis_tdata_reg = 8'd0;
+logic       temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+logic       temp_m_axis_tlast_reg = 1'b0;
+logic       temp_m_axis_tuser_reg = 1'b0;
 
 // datapath control
-reg store_axis_int_to_output;
-reg store_axis_int_to_temp;
-reg store_axis_temp_to_output;
+logic store_axis_int_to_output;
+logic store_axis_int_to_temp;
+logic store_axis_temp_to_output;
 
 assign m_axis.tdata = m_axis_tdata_reg;
 assign m_axis.tkeep = 1'b1;
@@ -407,7 +407,7 @@ assign m_axis.tuser = m_axis_tuser_reg;
 // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
 assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
 
-always @* begin
+always_comb begin
     // transfer sink ready state to source
     m_axis_tvalid_next = m_axis_tvalid_reg;
     temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
@@ -435,7 +435,7 @@ always @* begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     m_axis_tvalid_reg <= m_axis_tvalid_next;
     m_axis_tready_int_reg <= m_axis_tready_int_early;
     temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;

src/axis/rtl/taxi_axis_concat.sv

@@ -123,7 +123,7 @@ end else begin
     // destripe
     logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
 
-    reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
+    logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
 
     assign s_axis_tready = s_axis_tready_reg;
 

src/axis/rtl/taxi_axis_fifo.sv

@@ -130,6 +130,12 @@ if (m_axis.DATA_W != DATA_W)
 if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
     $fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
 
+if (DROP_BAD_FRAME && !s_axis.USER_EN)
+    $fatal(0, "Error: DROP_BAD_FRAME set requires s_axis.USER_EN (instance %m)");
+
+if (MARK_WHEN_FULL && !m_axis.USER_EN)
+    $fatal(0, "Error: MARK_WHEN_FULL set requires m_axis.USER_EN (instance %m)");
+
 localparam KEEP_OFFSET = DATA_W;
 localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
 localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);

src/axis/rtl/taxi_axis_mux.sv

@@ -63,21 +63,21 @@ if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
 
 parameter CL_S_COUNT = $clog2(S_COUNT);
 
-reg [CL_S_COUNT-1:0] select_reg = '0, select_next;
-reg frame_reg = 1'b0, frame_next;
+logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
+logic frame_reg = 1'b0, frame_next;
 
-reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
+logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
 
 // internal datapath
-reg  [DATA_W-1:0]  m_axis_tdata_int;
-reg  [KEEP_W-1:0]  m_axis_tkeep_int;
-reg  [KEEP_W-1:0]  m_axis_tstrb_int;
-reg                m_axis_tvalid_int;
-reg                m_axis_tready_int_reg = 1'b0;
-reg                m_axis_tlast_int;
-reg  [ID_W-1:0]    m_axis_tid_int;
-reg  [DEST_W-1:0]  m_axis_tdest_int;
-reg  [USER_W-1:0]  m_axis_tuser_int;
+logic  [DATA_W-1:0]  m_axis_tdata_int;
+logic  [KEEP_W-1:0]  m_axis_tkeep_int;
+logic  [KEEP_W-1:0]  m_axis_tstrb_int;
+logic                m_axis_tvalid_int;
+logic                m_axis_tready_int_reg = 1'b0;
+logic                m_axis_tlast_int;
+logic  [ID_W-1:0]    m_axis_tid_int;
+logic  [DEST_W-1:0]  m_axis_tdest_int;
+logic  [USER_W-1:0]  m_axis_tuser_int;
 wire               m_axis_tready_int_early;
 
 // unpack interface array
@@ -162,28 +162,28 @@ always_ff @(posedge clk) begin
 end
 
 // output datapath logic
-reg [DATA_W-1:0]  m_axis_tdata_reg  = '0;
-reg [KEEP_W-1:0]  m_axis_tkeep_reg  = '0;
-reg [KEEP_W-1:0]  m_axis_tstrb_reg  = '0;
-reg               m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
-reg               m_axis_tlast_reg  = 1'b0;
-reg [ID_W-1:0]    m_axis_tid_reg    = '0;
-reg [DEST_W-1:0]  m_axis_tdest_reg  = '0;
-reg [USER_W-1:0]  m_axis_tuser_reg  = '0;
+logic [DATA_W-1:0]  m_axis_tdata_reg  = '0;
+logic [KEEP_W-1:0]  m_axis_tkeep_reg  = '0;
+logic [KEEP_W-1:0]  m_axis_tstrb_reg  = '0;
+logic               m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+logic               m_axis_tlast_reg  = 1'b0;
+logic [ID_W-1:0]    m_axis_tid_reg    = '0;
+logic [DEST_W-1:0]  m_axis_tdest_reg  = '0;
+logic [USER_W-1:0]  m_axis_tuser_reg  = '0;
 
-reg [DATA_W-1:0]  temp_m_axis_tdata_reg  = '0;
-reg [KEEP_W-1:0]  temp_m_axis_tkeep_reg  = '0;
-reg [KEEP_W-1:0]  temp_m_axis_tstrb_reg  = '0;
-reg               temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
-reg               temp_m_axis_tlast_reg  = 1'b0;
-reg [ID_W-1:0]    temp_m_axis_tid_reg    = '0;
-reg [DEST_W-1:0]  temp_m_axis_tdest_reg  = '0;
-reg [USER_W-1:0]  temp_m_axis_tuser_reg  = '0;
+logic [DATA_W-1:0]  temp_m_axis_tdata_reg  = '0;
+logic [KEEP_W-1:0]  temp_m_axis_tkeep_reg  = '0;
+logic [KEEP_W-1:0]  temp_m_axis_tstrb_reg  = '0;
+logic               temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+logic               temp_m_axis_tlast_reg  = 1'b0;
+logic [ID_W-1:0]    temp_m_axis_tid_reg    = '0;
+logic [DEST_W-1:0]  temp_m_axis_tdest_reg  = '0;
+logic [USER_W-1:0]  temp_m_axis_tuser_reg  = '0;
 
 // datapath control
-reg store_axis_int_to_output;
-reg store_axis_int_to_temp;
-reg store_axis_temp_to_output;
+logic store_axis_int_to_output;
+logic store_axis_int_to_temp;
+logic store_axis_temp_to_output;
 
 assign m_axis.tdata  = m_axis_tdata_reg;
 assign m_axis.tkeep  = KEEP_EN ? m_axis_tkeep_reg : '1;

src/dma/rtl/taxi_dma_client_axis_sink.sv

@@ -418,7 +418,7 @@ always_comb begin
     end
 end
 
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
     state_reg <= state_next;
 
     desc_req_ready_reg <= desc_req_ready_next;
@@ -484,27 +484,27 @@ end
 // output datapath logic (write data)
 for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin
 
-    reg [RAM_SEG_BE_W-1:0]   ram_wr_cmd_be_reg = '0;
-    reg [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0;
-    reg [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0;
-    reg                      ram_wr_cmd_valid_reg = 1'b0;
+    logic [RAM_SEG_BE_W-1:0]   ram_wr_cmd_be_reg = '0;
+    logic [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0;
+    logic [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0;
+    logic                      ram_wr_cmd_valid_reg = 1'b0;
 
-    reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
-    reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
-    reg out_fifo_half_full_reg = 1'b0;
+    logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
+    logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
+    logic out_fifo_half_full_reg = 1'b0;
 
     wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_BE_W-1:0]   out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_BE_W-1:0]   out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    reg [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW];
+    logic [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW];
 
-    reg [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0;
-    reg done_reg = 1'b0;
+    logic [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0;
+    logic done_reg = 1'b0;
 
     assign ram_wr_cmd_ready_int[n] = !out_fifo_half_full_reg;
 
@@ -515,7 +515,7 @@ for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin
 
     assign out_done[n] = done_reg;
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_reg && !dma_ram_wr.wr_cmd_ready[n];
 
         out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);

src/dma/rtl/taxi_dma_if_pcie_us_rd.sv

@@ -1537,7 +1537,7 @@ always_comb begin
     end
 end
 
-reg [1:0] active_tx_count_ovf;
+logic [1:0] active_tx_count_ovf;
 
 always_comb begin
     {active_tx_count_ovf, active_tx_count_next} = $signed({1'b0, active_tx_count_reg}) + $signed({1'b0, inc_active_tx});

src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -89,9 +89,9 @@ wire qsfp_0_mgt_refclk_bufg;
 
 wire qsfp_rst;
 
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_tx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[8]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_rx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_rx[8]();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2]();
 
 if (SIM) begin

src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv

@@ -105,9 +105,9 @@ assign sfp_mgt_refclk_out = sfp_mgt_refclk_bufg;
 
 wire sfp_rst;
 
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_tx[2]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_rx[2]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2]();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
 if (SIM) begin

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -231,12 +231,12 @@ assign eth_port_lpmode = '0;
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 

src/eth/example/Arty/fpga/rtl/fpga_core.sv

@@ -157,7 +157,7 @@ xfcp_stats_inst (
     .s_axis_stat(axis_mac_stat)
 );
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 taxi_eth_mac_mii_fifo #(

src/eth/example/HTG9200/fpga/rtl/fpga_core.sv

@@ -299,12 +299,12 @@ assign eth_port_resetl = {PORT_CNT{~eth_reset}};
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 

src/eth/example/HTG940/fpga/rtl/fpga_core.sv

@@ -147,7 +147,7 @@ xfcp_stats_inst (
 );
 
 // BASE-T PHY
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 taxi_eth_mac_1g_rgmii_fifo #(

src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv

@@ -256,12 +256,12 @@ assign eth_port_resetl = {PORT_CNT{~eth_reset}};
 
 wire eth_gty_tx_clk[GTY_CNT];
 wire eth_gty_tx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
 
 wire eth_gty_rx_clk[GTY_CNT];
 wire eth_gty_rx_rst[GTY_CNT];
-taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
 
 wire eth_gty_rx_status[GTY_CNT];
 

src/eth/example/KC705/fpga/fpga.xdc

@@ -80,8 +80,9 @@ set_false_path -from [get_ports {uart_rxd uart_rts}]
 set_input_delay 0 [get_ports {uart_rxd uart_rts}]
 
 # I2C interface
-#set_property -dict {LOC K21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
-#set_property -dict {LOC L21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC K21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC L21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC P23  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
 
 #set_false_path -to [get_ports {i2c_sda i2c_scl}]
 #set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
@@ -139,17 +140,28 @@ set_property -dict {LOC H6   } [get_ports phy_sgmii_rx_p] ;# MGTXRXP1_117 GTXE2_
 set_property -dict {LOC H5   } [get_ports phy_sgmii_rx_n] ;# MGTXRXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A8 SOUT_N
 set_property -dict {LOC J4   } [get_ports phy_sgmii_tx_p] ;# MGTXTXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A3 SIN_P
 set_property -dict {LOC J3   } [get_ports phy_sgmii_tx_n] ;# MGTXTXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A4 SIN_N
-set_property -dict {LOC G8   } [get_ports sgmii_clk_p] ;# MGTREFCLK0P_117 from U2.7
-set_property -dict {LOC G7   } [get_ports sgmii_clk_n] ;# MGTREFCLK0N_117 from U2.6
-#set_property -dict {LOC L8   } [get_ports sfp_clk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
-#set_property -dict {LOC L7   } [get_ports sfp_clk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
+set_property -dict {LOC G8   } [get_ports sgmii_mgt_refclk_p] ;# MGTREFCLK0P_117 from U2.7
+set_property -dict {LOC G7   } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117 from U2.6
+#set_property -dict {LOC L8   } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
+#set_property -dict {LOC L7   } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
 #set_property -dict {LOC W27 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to Si5324 U70.16 CKIN1_P
 #set_property -dict {LOC W28 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to Si5324 U70.17 CKIN1_N
 
+#set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
+#set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
+
 set_property -dict {LOC Y20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
 
-create_clock -period 8.000 -name sgmii_clk [get_ports sgmii_clk_p]
-#create_clock -period 6.400 -name sgmii_clk [get_ports sfp_clk_p]
+# 125 MHz MGT reference clock (SGMII, 1000BASE-X)
+#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]
+
+# 156.25 MHz MGT reference clock (10GBASE-R)
+#create_clock -period 6.400 -name sgmii_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+#set_false_path -to [get_ports {si5324_rst}]
+#set_output_delay 0 [get_ports {si5324_rst}]
+#set_false_path -from [get_ports {si5324_int}]
+#set_input_delay 0 [get_ports {si5324_int}]
 
 set_false_path -to [get_ports {sfp_tx_disable_b}]
 set_output_delay 0 [get_ports {sfp_tx_disable_b}]

src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile

@@ -22,6 +22,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile

@@ -22,6 +22,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KC705/fpga/rtl/fpga.sv

@@ -58,6 +58,13 @@ module fpga #
     input  wire logic        uart_rts,
     output wire logic        uart_cts,
 
+    /*
+     * I2C
+     */
+    inout  wire logic        i2c_scl,
+    inout  wire logic        i2c_sda,
+    output wire logic        i2c_mux_reset,
+
     /*
      * Ethernet: SFP+
      */
@@ -69,8 +76,8 @@ module fpga #
     input  wire logic        phy_sgmii_rx_n,
     output wire logic        phy_sgmii_tx_p,
     output wire logic        phy_sgmii_tx_n,
-    input  wire logic        sgmii_clk_p,
-    input  wire logic        sgmii_clk_n,
+    input  wire logic        sgmii_mgt_refclk_p,
+    input  wire logic        sgmii_mgt_refclk_n,
 
     output wire logic        sfp_tx_disable_b,
 
@@ -265,6 +272,17 @@ sync_signal_inst (
 
 wire [7:0] led_int;
 
+// I2C
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+
 // SGMII interface to PHY
 wire phy_sgmii_clk_int;
 wire phy_sgmii_rst_int;
@@ -338,8 +356,8 @@ assign sgmii_an_config_vect[0]     = 1'b1;    // SGMII
 sgmii_pcs_pma_0
 sgmii_pcspma (
     // Transceiver Interface
-    .gtrefclk_p            (sgmii_clk_p),
-    .gtrefclk_n            (sgmii_clk_n),
+    .gtrefclk_p            (sgmii_mgt_refclk_p),
+    .gtrefclk_n            (sgmii_mgt_refclk_n),
     .gtrefclk_out          (sgmii_gtrefclk),
     .gtrefclk_bufg_out     (sgmii_gtrefclk_bufg),
     .txp                   (phy_sgmii_tx_p),
@@ -661,6 +679,14 @@ core_inst (
     .uart_rts(uart_rts_int),
     .uart_cts(uart_cts),
 
+    /*
+     * I2C
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o),
+
     /*
      * Ethernet: 1000BASE-X SFP
      */

src/eth/example/KC705/fpga/rtl/fpga_core.sv

@@ -58,6 +58,14 @@ module fpga_core #
     input  wire logic        uart_rts,
     output wire logic        uart_cts,
 
+    /*
+     * I2C
+     */
+    input  wire logic        i2c_scl_i,
+    output wire logic        i2c_scl_o,
+    input  wire logic        i2c_sda_i,
+    output wire logic        i2c_sda_o,
+
     /*
      * Ethernet: 1000BASE-X SFP
      */
@@ -136,7 +144,7 @@ xfcp_if_uart_inst (
     .prescale(16'(125000000/921600))
 );
 
-taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2]();
 
 taxi_xfcp_switch #(
     .XFCP_ID_STR("KC705"),
@@ -209,10 +217,34 @@ stat_mux_inst (
     .m_axis(axis_stat)
 );
 
+// I2C
+taxi_xfcp_mod_i2c_master #(
+    .XFCP_EXT_ID_STR("I2C"),
+    .DEFAULT_PRESCALE(16'(125000000/200000/4))
+)
+xfcp_mod_i2c_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[1]),
+    .xfcp_usp_us(xfcp_sw_us[1]),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o)
+);
+
 // BASE-T PHY
 assign phy_reset_n = !rst;
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
@@ -491,7 +523,7 @@ end
 // SFP+
 assign sfp_tx_disable_b = 1'b1;
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
 
 taxi_eth_mac_1g_fifo #(

src/eth/example/KC705/fpga/tb/fpga_core/Makefile

@@ -28,6 +28,7 @@ VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py

@@ -150,20 +150,22 @@ async def run_test(dut):
 
     await tb.init()
 
+    tests = []
+
     tb.log.info("Start BASE-T MAC loopback test")
 
     if hasattr(dut, "baset_mac_gmii"):
-        baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))
+        tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
     elif hasattr(dut, "baset_mac_rgmii"):
-        baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))
+        tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
     elif hasattr(dut, "baset_mac_sgmii"):
-        baset_test_cr = cocotb.start_soon(mac_test(tb, tb.sgmii_source, tb.sgmii_sink))
+        tests.append(cocotb.start_soon(mac_test(tb, tb.sgmii_source, tb.sgmii_sink)))
 
     tb.log.info("Start SFP MAC loopback test")
 
-    sfp_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink))
+    tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink)))
 
-    await Combine(baset_test_cr, sfp_test_cr)
+    await Combine(*tests)
 
     await RisingEdge(dut.clk)
     await RisingEdge(dut.clk)
@@ -203,6 +205,7 @@ def test_fpga_core(request, phy_type):
         os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),

src/eth/example/KC705/fpga_10g/README.md

@@ -0,0 +1,51 @@
+# Taxi Example Design for KC705
+
+## Introduction
+
+This example design targets the Xilinx KC705 FPGA board.
+
+The design places looped-back MACs on both the BASE-T port and the SFP+ cage, as well as XFCP on the USB UART for monitoring and control.
+
+Note that this design does not support SGMII as the Xilinx SGMII core requires the GTX QPLL, which is already used for 10GBASE-R on the same quad.
+
+*  USB UART
+    *  XFCP (921600 baud)
+*  RJ-45 Ethernet port with Marvell 88E1111 PHY
+    *  Looped-back MAC via GMII
+    *  Looped-back MAC via RGMII
+*  SFP+ cage
+    *  Looped-back 10GBASE-R MACs via GTX transceiver
+
+## Board details
+
+*  FPGA: XC7K325T-2FFG900C
+*  USB UART: Silicon Labs CP2103
+*  1000BASE-T PHY: Marvell 88E1111 via GMII or RGMII
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## Board configuration
+
+Several jumpers must be configured to configure the PHY chip for the appropriate mode.
+
+| Mode     | J29  | J30  | J64  |
+| -------- | ---- | ---- | ---- |
+| GMII/MII | 1-2  | 1-2  | open |
+| RGMII    | 1-2  | open | 1-2  |
+
+Also, note that version 1.0 of the KC705 has the SFP+ TX and RX connections polarity-inverted.  Version 1.1 has this fixed.  This setting is controlled via a top-level parameter setting that is configurable via config.tcl, so ensure to use a design matching the board revision.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.

src/eth/example/KC705/fpga_10g/common/vivado.mk

@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/eth/example/KC705/fpga_10g/eth_gmii.xdc

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Ethernet constraints
+
+# BUFGMUX outputs (GMII)
+set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk

src/eth/example/KC705/fpga_10g/eth_rgmii.xdc

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Ethernet constraints
+
+# IDELAY from PHY chip (RGMII)
+set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
+
+# MMCM phase (RGMII)
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]

src/eth/example/KC705/fpga_10g/fpga.xdc

@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx KC705 board
+# part: xc7k325tffg900-2
+
+# General configuration
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 2.5                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+
+# System clocks
+# 200 MHz system clock
+set_property -dict {LOC AD12 IOSTANDARD LVDS} [get_ports clk_200mhz_p] ;# from SiT9102 U6.4
+set_property -dict {LOC AD11 IOSTANDARD LVDS} [get_ports clk_200mhz_n] ;# from SiT9102 U6.5
+create_clock -period 5.000 -name clk_200mhz [get_ports clk_200mhz_p]
+
+# Si570 user clock (156.25 MHz default)
+#set_property -dict {LOC K28 IOSTANDARD LVDS_25} [get_ports clk_user_p] ;# from Si570 U45.4
+#set_property -dict {LOC K29 IOSTANDARD LVDS_25} [get_ports clk_user_n] ;# from Si570 U45.5
+#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
+
+# User SMA clock
+#set_property -dict {LOC L25 IOSTANDARD LVDS_25} [get_ports clk_user_sma_p] ;# from J11
+#set_property -dict {LOC K25 IOSTANDARD LVDS_25} [get_ports clk_user_sma_n] ;# from J12
+#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
+
+# LEDs
+set_property -dict {LOC AB8  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# to DS4
+set_property -dict {LOC AA8  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# to DS1
+set_property -dict {LOC AC9  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# to DS10
+set_property -dict {LOC AB9  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# to DS2
+set_property -dict {LOC AE26 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[4]}] ;# to DS3
+set_property -dict {LOC G19  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[5]}] ;# to DS25
+set_property -dict {LOC E18  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[6]}] ;# to DS26
+set_property -dict {LOC F16  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[7]}] ;# to DS27
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Reset button
+set_property -dict {LOC AB7  IOSTANDARD LVCMOS15} [get_ports reset] ;# from SW7
+
+set_false_path -from [get_ports {reset}]
+set_input_delay 0 [get_ports {reset}]
+
+# Push buttons
+set_property -dict {LOC AA12 IOSTANDARD LVCMOS15} [get_ports btnu] ;# from SW2
+set_property -dict {LOC AC6  IOSTANDARD LVCMOS15} [get_ports btnl] ;# from SW6
+set_property -dict {LOC AB12 IOSTANDARD LVCMOS15} [get_ports btnd] ;# from SW4
+set_property -dict {LOC AG5  IOSTANDARD LVCMOS15} [get_ports btnr] ;# from SW3
+set_property -dict {LOC G12  IOSTANDARD LVCMOS25} [get_ports btnc] ;# from SW5
+
+set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
+set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
+
+# DIP switches
+set_property -dict {LOC Y29  IOSTANDARD LVCMOS25} [get_ports {sw[0]}] ;# from SW4.4
+set_property -dict {LOC W29  IOSTANDARD LVCMOS25} [get_ports {sw[1]}] ;# from SW4.3
+set_property -dict {LOC AA28 IOSTANDARD LVCMOS25} [get_ports {sw[2]}] ;# from SW4.2
+set_property -dict {LOC Y28  IOSTANDARD LVCMOS25} [get_ports {sw[3]}] ;# from SW4.1
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# UART (U12 CP2103)
+set_property -dict {LOC K24  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
+set_property -dict {LOC M19  IOSTANDARD LVCMOS25} [get_ports {uart_rxd}] ;# U12.25 TXD_O
+set_property -dict {LOC L27  IOSTANDARD LVCMOS25} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
+set_property -dict {LOC K23  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
+
+set_false_path -to [get_ports {uart_txd uart_cts}]
+set_output_delay 0 [get_ports {uart_txd uart_cts}]
+set_false_path -from [get_ports {uart_rxd uart_rts}]
+set_input_delay 0 [get_ports {uart_rxd uart_rts}]
+
+# I2C interface
+set_property -dict {LOC K21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC L21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC P23  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
+
+set_false_path -to [get_ports {i2c_sda i2c_scl}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# Gigabit Ethernet GMII PHY
+set_property -dict {LOC U27  IOSTANDARD LVCMOS25} [get_ports phy_rx_clk] ;# from U37.C1 RXCLK
+set_property -dict {LOC U30  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[0]}] ;# from U37.B2 RXD0
+set_property -dict {LOC U25  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[1]}] ;# from U37.D3 RXD1
+set_property -dict {LOC T25  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[2]}] ;# from U37.C3 RXD2
+set_property -dict {LOC U28  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[3]}] ;# from U37.B3 RXD3
+set_property -dict {LOC R19  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[4]}] ;# from U37.C4 RXD4
+set_property -dict {LOC T27  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[5]}] ;# from U37.A1 RXD5
+set_property -dict {LOC T26  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[6]}] ;# from U37.A2 RXD6
+set_property -dict {LOC T28  IOSTANDARD LVCMOS25} [get_ports {phy_rxd[7]}] ;# from U37.C5 RXD7
+set_property -dict {LOC R28  IOSTANDARD LVCMOS25} [get_ports phy_rx_dv] ;# from U37.B1 RXCTL_RXDV
+set_property -dict {LOC V26  IOSTANDARD LVCMOS25} [get_ports phy_rx_er] ;# from U37.D4 RXER
+set_property -dict {LOC K30  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_gtx_clk] ;# from U37.E2 TXC_GTXCLK
+set_property -dict {LOC M28  IOSTANDARD LVCMOS25} [get_ports phy_tx_clk] ;# from U37.D1 TXCLK
+set_property -dict {LOC N27  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}] ;# from U37.F1 TXD0
+set_property -dict {LOC N25  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}] ;# from U37.G2 TXD1
+set_property -dict {LOC M29  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}] ;# from U37.G3 TXD2
+set_property -dict {LOC L28  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}] ;# from U37.H1 TXD3
+set_property -dict {LOC J26  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[4]}] ;# from U37.H2 TXD4
+set_property -dict {LOC K26  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[5]}] ;# from U37.H3 TXD5
+set_property -dict {LOC L30  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[6]}] ;# from U37.J1 TXD6
+set_property -dict {LOC J28  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[7]}] ;# from U37.J2 TXD7
+set_property -dict {LOC M27  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_en] ;# from U37.E1 TXCTL_TXEN
+set_property -dict {LOC N29  IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_er] ;# from U37.F2 TXER
+set_property -dict {LOC L20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# from U37.K3 RESET_B
+set_property -dict {LOC N30  IOSTANDARD LVCMOS25} [get_ports phy_int_n] ;# from U37.L1 INT_B
+#set_property -dict {LOC J21  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# from U37.M1 MDIO
+#set_property -dict {LOC R23  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# from U37.L3 MDC
+
+create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+
+set_false_path -to [get_ports {phy_reset_n}]
+set_output_delay 0 [get_ports {phy_reset_n}]
+set_false_path -from [get_ports {phy_int_n}]
+set_input_delay 0 [get_ports {phy_int_n}]
+
+#set_false_path -to [get_ports {phy_mdio phy_mdc}]
+#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
+#set_false_path -from [get_ports {phy_mdio}]
+#set_input_delay 0 [get_ports {phy_mdio}]
+
+# GTX for Ethernet
+set_property -dict {LOC G4   } [get_ports sfp_rx_p] ;# MGTXRXP2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.13
+set_property -dict {LOC G3   } [get_ports sfp_rx_n] ;# MGTXRXN2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.12
+set_property -dict {LOC H2   } [get_ports sfp_tx_p] ;# MGTXTXP2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.18
+set_property -dict {LOC H1   } [get_ports sfp_tx_n] ;# MGTXTXN2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.19
+#set_property -dict {LOC H6   } [get_ports phy_sgmii_rx_p] ;# MGTXRXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A7 SOUT_P
+#set_property -dict {LOC H5   } [get_ports phy_sgmii_rx_n] ;# MGTXRXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A8 SOUT_N
+#set_property -dict {LOC J4   } [get_ports phy_sgmii_tx_p] ;# MGTXTXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A3 SIN_P
+#set_property -dict {LOC J3   } [get_ports phy_sgmii_tx_n] ;# MGTXTXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A4 SIN_N
+#set_property -dict {LOC G8   } [get_ports sgmii_mgt_refclk_p] ;# MGTREFCLK0P_117 from U2.7
+#set_property -dict {LOC G7   } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117 from U2.6
+set_property -dict {LOC L8   } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
+set_property -dict {LOC L7   } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
+#set_property -dict {LOC W27 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to Si5324 U70.16 CKIN1_P
+#set_property -dict {LOC W28 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to Si5324 U70.17 CKIN1_N
+
+set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
+set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
+
+set_property -dict {LOC Y20  IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
+
+# 125 MHz MGT reference clock (SGMII, 1000BASE-X)
+#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]
+
+# 156.25 MHz MGT reference clock (10GBASE-R)
+create_clock -period 6.400 -name sgmii_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+set_false_path -to [get_ports {si5324_rst}]
+set_output_delay 0 [get_ports {si5324_rst}]
+set_false_path -from [get_ports {si5324_int}]
+set_input_delay 0 [get_ports {si5324_int}]
+
+set_false_path -to [get_ports {sfp_tx_disable_b}]
+set_output_delay 0 [get_ports {sfp_tx_disable_b}]
+
+# PCIe Interface
+#set_property -dict {LOC M6  } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC M5  } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC L4  } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC L3  } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC P6  } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC P5  } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC M2  } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC M1  } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC R4  } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC R3  } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC N4  } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC N3  } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC T6  } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC T5  } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC P2  } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC P1  } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
+#set_property -dict {LOC V6  } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC V5  } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC T2  } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC T1  } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC W4  } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC W3  } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC U4  } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC U3  } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC Y6  } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC Y5  } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC V2  } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC V1  } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC Y2  } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC Y1  } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
+#set_property -dict {LOC U8  } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
+#set_property -dict {LOC U7  } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
+#set_property -dict {LOC G25  IOSTANDARD LVCMOS25 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
+
+#set_false_path -from [get_ports {pcie_reset_n}]
+#set_input_delay 0 [get_ports {pcie_reset_n}]

src/eth/example/KC705/fpga_10g/fpga_gmii/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/si5324_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../eth_gmii.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/KC705/fpga_10g/fpga_gmii/config.tcl

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII or RGMII)
+dict set params BASET_PHY_TYPE "GMII"
+
+# Invert polarity for SFP+ cage
+# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
+dict set params SFP_INVERT "1"
+# KC705 rev 1.1: diff pairs to SFP+ are correct
+#dict set params SFP_INVERT "0"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/KC705/fpga_10g/fpga_rgmii/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/si5324_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../eth_rgmii.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/KC705/fpga_10g/fpga_rgmii/config.tcl

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII or RGMII)
+dict set params BASET_PHY_TYPE "RGMII"
+
+# Invert polarity for SFP+ cage
+# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
+dict set params SFP_INVERT "1"
+# KC705 rev 1.1: diff pairs to SFP+ are correct
+#dict set params SFP_INVERT "0"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/KC705/fpga_10g/lib/taxi

@@ -0,0 +1 @@
+../../../../../../

src/eth/example/KC705/fpga_10g/rtl/fpga.sv

@@ -0,0 +1,556 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "kintex7",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1,
+    // BASE-T PHY type (GMII, RGMII)
+    parameter BASET_PHY_TYPE = "GMII",
+    // SFP rate selection (0 for 1G, 1 for 10G)
+    parameter logic SFP_RATE = 1'b1,
+    // Invert SFP data pins
+    parameter logic SFP_INVERT = 1'b1,
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1
+)
+(
+    /*
+     * Clock: 200MHz
+     * Reset: Push button, active high
+     */
+    input  wire logic        clk_200mhz_p,
+    input  wire logic        clk_200mhz_n,
+    input  wire logic        reset,
+
+    /*
+     * GPIO
+     */
+    input  wire logic        btnu,
+    input  wire logic        btnl,
+    input  wire logic        btnd,
+    input  wire logic        btnr,
+    input  wire logic        btnc,
+    input  wire logic [3:0]  sw,
+    output wire logic [7:0]  led,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire logic        uart_rxd,
+    output wire logic        uart_txd,
+    input  wire logic        uart_rts,
+    output wire logic        uart_cts,
+
+    /*
+     * I2C
+     */
+    inout  wire logic        i2c_scl,
+    inout  wire logic        i2c_sda,
+    output wire logic        i2c_mux_reset,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic        sfp_rx_p,
+    input  wire logic        sfp_rx_n,
+    output wire logic        sfp_tx_p,
+    output wire logic        sfp_tx_n,
+    input  wire logic        sfp_mgt_refclk_p,
+    input  wire logic        sfp_mgt_refclk_n,
+
+    output wire logic        si5324_rst,
+    input  wire logic        si5324_int,
+
+    output wire logic        sfp_tx_disable_b,
+
+    /*
+     * Ethernet: 1000BASE-T GMII or RGMII
+     */
+    input  wire logic        phy_rx_clk,
+    input  wire logic [7:0]  phy_rxd,
+    input  wire logic        phy_rx_dv,
+    input  wire logic        phy_rx_er,
+    output wire logic        phy_gtx_clk,
+    input  wire logic        phy_tx_clk,
+    output wire logic [7:0]  phy_txd,
+    output wire logic        phy_tx_en,
+    output wire logic        phy_tx_er,
+    output wire logic        phy_reset_n,
+    input  wire logic        phy_int_n
+);
+
+// Clock and reset
+
+wire clk_200mhz_ibufg;
+
+// Internal 125 MHz clock
+wire clk_mmcm_out;
+wire clk_int;
+wire clk90_mmcm_out;
+wire clk90_int;
+wire rst_int;
+
+wire clk_200mhz_mmcm_out;
+wire clk_200mhz_int;
+
+wire mmcm_rst = reset;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS
+clk_200mhz_ibufgds_inst(
+    .I(clk_200mhz_p),
+    .IB(clk_200mhz_n),
+    .O(clk_200mhz_ibufg)
+);
+
+// MMCM instance
+MMCME2_BASE #(
+    // 200 MHz input
+    .CLKIN1_PERIOD(5.0),
+    .REF_JITTER1(0.010),
+    // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz VCO / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // 1000 MHz VCO / 8 = 125 MHz, 90 degrees
+    .CLKOUT1_DIVIDE(8),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    // 1000 MHz VCO / 5 = 200 MHz, 0 degrees
+    .CLKOUT2_DIVIDE(5),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 200 MHz input
+    .CLKIN1(clk_200mhz_ibufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_mmcm_out),
+    .CLKOUT0B(),
+    // 125 MHz, 90 degrees
+    .CLKOUT1(clk90_mmcm_out),
+    .CLKOUT1B(),
+    // 200 MHz, 0 degrees
+    .CLKOUT2(clk_200mhz_mmcm_out),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_bufg_inst (
+    .I(clk_mmcm_out),
+    .O(clk_int)
+);
+
+BUFG
+clk90_bufg_inst (
+    .I(clk90_mmcm_out),
+    .O(clk90_int)
+);
+
+BUFG
+clk_200mhz_bufg_inst (
+    .I(clk_200mhz_mmcm_out),
+    .O(clk_200mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_inst (
+    .clk(clk_int),
+    .rst(~mmcm_locked),
+    .out(rst_int)
+);
+
+// GPIO
+wire btnu_int;
+wire btnl_int;
+wire btnd_int;
+wire btnr_int;
+wire btnc_int;
+wire [3:0] sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(9),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_int),
+    .rst(rst_int),
+    .in({btnu,
+        btnl,
+        btnd,
+        btnr,
+        btnc,
+        sw}),
+    .out({btnu_int,
+        btnl_int,
+        btnd_int,
+        btnr_int,
+        btnc_int,
+        sw_int})
+);
+
+wire uart_rxd_int;
+wire uart_rts_int;
+
+taxi_sync_signal #(
+    .WIDTH(2),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_int),
+    .in({uart_rxd, uart_rts}),
+    .out({uart_rxd_int, uart_rts_int})
+);
+
+// I2C
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+
+wire i2c_init_scl_i = i2c_scl_i;
+wire i2c_init_scl_o;
+wire i2c_init_sda_i = i2c_sda_i;
+wire i2c_init_sda_o;
+
+wire i2c_int_scl_i = i2c_scl_i;
+wire i2c_int_scl_o;
+wire i2c_int_sda_i = i2c_sda_i;
+wire i2c_int_sda_o;
+
+assign i2c_scl_o = i2c_init_scl_o & i2c_int_scl_o;
+assign i2c_sda_o = i2c_init_sda_o & i2c_int_sda_o;
+
+// Si5324 init
+taxi_axis_if #(.DATA_W(12)) si5324_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) si5324_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) si5324_i2c_rx();
+
+assign si5324_i2c_rx.tready = 1'b1;
+
+wire si5324_i2c_busy;
+
+assign si5324_rst = ~rst_int;
+
+taxi_i2c_master
+si5324_i2c_master_inst (
+    .clk(clk_int),
+    .rst(rst_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(si5324_i2c_cmd),
+    .s_axis_tx(si5324_i2c_tx),
+    .m_axis_rx(si5324_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(i2c_init_scl_i),
+    .scl_o(i2c_init_scl_o),
+    .sda_i(i2c_init_sda_i),
+    .sda_o(i2c_init_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 32 : 312),
+    .stop_on_idle(1)
+);
+
+si5324_i2c_init #(
+    .SIM_SPEEDUP(SIM)
+)
+si5324_i2c_init_inst (
+    .clk(clk_int),
+    .rst(rst_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(si5324_i2c_cmd),
+    .m_axis_tx(si5324_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(si5324_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+wire phy_rgmii_rx_clk_int;
+wire [3:0] phy_rgmii_rxd_int;
+wire phy_rgmii_rx_ctl_int;
+wire phy_rgmii_tx_clk_int;
+wire [3:0] phy_rgmii_txd_int;
+wire phy_rgmii_tx_ctl_int;
+
+wire phy_gmii_rx_clk_int;
+wire [7:0] phy_gmii_rxd_int;
+wire phy_gmii_rx_dv_int;
+wire phy_gmii_rx_er_int;
+wire phy_gmii_gtx_clk_int;
+wire phy_gmii_tx_clk_int;
+wire [7:0] phy_gmii_txd_int;
+wire phy_gmii_tx_en_int;
+wire phy_gmii_tx_er_int;
+
+if (BASET_PHY_TYPE == "RGMII") begin : phy_if
+
+    assign phy_rgmii_rx_clk_int = phy_rx_clk;
+
+    // IODELAY elements for RGMII interface to PHY
+    IDELAYCTRL
+    idelayctrl_inst (
+        .REFCLK(clk_200mhz_int),
+        .RST(rst_int),
+        .RDY()
+    );
+
+    for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
+
+        IDELAYE2 #(
+            .IDELAY_TYPE("FIXED")
+        )
+        idelay_inst (
+            .IDATAIN(phy_rxd[n]),
+            .DATAOUT(phy_rgmii_rxd_int[n]),
+            .DATAIN(1'b0),
+            .C(1'b0),
+            .CE(1'b0),
+            .INC(1'b0),
+            .CINVCTRL(1'b0),
+            .CNTVALUEIN(5'd0),
+            .CNTVALUEOUT(),
+            .LD(1'b0),
+            .LDPIPEEN(1'b0),
+            .REGRST(1'b0)
+        );
+
+    end
+
+    IDELAYE2 #(
+        .IDELAY_TYPE("FIXED")
+    )
+    phy_rx_ctl_idelay (
+        .IDATAIN(phy_rx_dv),
+        .DATAOUT(phy_rgmii_rx_ctl_int),
+        .DATAIN(1'b0),
+        .C(1'b0),
+        .CE(1'b0),
+        .INC(1'b0),
+        .CINVCTRL(1'b0),
+        .CNTVALUEIN(5'd0),
+        .CNTVALUEOUT(),
+        .LD(1'b0),
+        .LDPIPEEN(1'b0),
+        .REGRST(1'b0)
+    );
+
+    assign phy_gtx_clk = phy_rgmii_tx_clk_int;
+    assign phy_txd[3:0] = phy_rgmii_txd_int;
+    assign phy_tx_en = phy_rgmii_tx_ctl_int;
+
+    assign phy_txd[7:4] = '0;
+    assign phy_tx_er = 1'b0;
+
+    assign phy_gmii_rx_clk_int = 1'b0;
+    assign phy_gmii_rxd_int = '0;
+    assign phy_gmii_rx_dv_int = 1'b0;
+    assign phy_gmii_rx_er_int = 1'b0;
+    assign phy_gmii_tx_clk_int = 1'b0;
+
+end else begin : phy_if
+
+    assign phy_rgmii_rx_clk_int = 1'b0;
+    assign phy_rgmii_rxd_int = '0;
+    assign phy_rgmii_rx_ctl_int = 1'b0;
+
+    assign phy_gmii_rx_clk_int = phy_rx_clk;
+    assign phy_gmii_rxd_int = phy_rxd;
+    assign phy_gmii_rx_dv_int = phy_rx_dv;
+    assign phy_gmii_rx_er_int = phy_rx_er;
+
+    assign phy_gtx_clk = phy_gmii_gtx_clk_int;
+    assign phy_gmii_tx_clk_int = phy_tx_clk;
+    assign phy_txd = phy_gmii_txd_int;
+    assign phy_tx_en = phy_gmii_tx_en_int;
+    assign phy_tx_er = phy_gmii_tx_er_int;
+
+end
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .BASET_PHY_TYPE(BASET_PHY_TYPE),
+    .SFP_INVERT(SFP_INVERT),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk(clk_int),
+    .clk90(clk90_int),
+    .rst(rst_int),
+
+    /*
+     * GPIO
+     */
+    .btnu(btnu_int),
+    .btnl(btnl_int),
+    .btnd(btnd_int),
+    .btnr(btnr_int),
+    .btnc(btnc_int),
+    .sw(sw_int),
+    .led(led),
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    .uart_rxd(uart_rxd_int),
+    .uart_txd(uart_txd),
+    .uart_rts(uart_rts_int),
+    .uart_cts(uart_cts),
+
+    /*
+     * I2C
+     */
+    .i2c_scl_i(i2c_int_scl_i),
+    .i2c_scl_o(i2c_int_scl_o),
+    .i2c_sda_i(i2c_int_sda_i),
+    .i2c_sda_o(i2c_int_sda_o),
+
+    /*
+     * Ethernet: SFP+
+     */
+    .sfp_rx_p(sfp_rx_p),
+    .sfp_rx_n(sfp_rx_n),
+    .sfp_tx_p(sfp_tx_p),
+    .sfp_tx_n(sfp_tx_n),
+    .sfp_mgt_refclk_p(sfp_mgt_refclk_p),
+    .sfp_mgt_refclk_n(sfp_mgt_refclk_n),
+
+    .sfp_tx_disable_b(sfp_tx_disable_b),
+
+    /*
+     * Ethernet: 1000BASE-T GMII/RGMII/SGMII
+     */
+    .phy_rgmii_rx_clk(phy_rgmii_rx_clk_int),
+    .phy_rgmii_rxd(phy_rgmii_rxd_int),
+    .phy_rgmii_rx_ctl(phy_rgmii_rx_ctl_int),
+    .phy_rgmii_tx_clk(phy_rgmii_tx_clk_int),
+    .phy_rgmii_txd(phy_rgmii_txd_int),
+    .phy_rgmii_tx_ctl(phy_rgmii_tx_ctl_int),
+
+    .phy_gmii_rx_clk(phy_gmii_rx_clk_int),
+    .phy_gmii_rxd(phy_gmii_rxd_int),
+    .phy_gmii_rx_dv(phy_gmii_rx_dv_int),
+    .phy_gmii_rx_er(phy_gmii_rx_er_int),
+    .phy_gmii_gtx_clk(phy_gmii_gtx_clk_int),
+    .phy_gmii_tx_clk(phy_gmii_tx_clk_int),
+    .phy_gmii_txd(phy_gmii_txd_int),
+    .phy_gmii_tx_en(phy_gmii_tx_en_int),
+    .phy_gmii_tx_er(phy_gmii_tx_er_int),
+
+    .phy_reset_n(phy_reset_n),
+    .phy_int_n(phy_int_n)
+);
+
+endmodule
+
+`resetall

src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv

@@ -0,0 +1,766 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "kintex7",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1,
+    // BASE-T PHY type (GMII or RGMII)
+    parameter BASET_PHY_TYPE = "GMII",
+    // Invert SFP data pins
+    parameter logic SFP_INVERT = 1'b1,
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 32
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire logic        clk,
+    input  wire logic        clk90,
+    input  wire logic        rst,
+
+    /*
+     * GPIO
+     */
+    input  wire logic        btnu,
+    input  wire logic        btnl,
+    input  wire logic        btnd,
+    input  wire logic        btnr,
+    input  wire logic        btnc,
+    input  wire logic [7:0]  sw,
+    output wire logic [7:0]  led,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire logic        uart_rxd,
+    output wire logic        uart_txd,
+    input  wire logic        uart_rts,
+    output wire logic        uart_cts,
+
+    /*
+     * I2C
+     */
+    input  wire logic        i2c_scl_i,
+    output wire logic        i2c_scl_o,
+    input  wire logic        i2c_sda_i,
+    output wire logic        i2c_sda_o,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic        sfp_rx_p,
+    input  wire logic        sfp_rx_n,
+    output wire logic        sfp_tx_p,
+    output wire logic        sfp_tx_n,
+    input  wire logic        sfp_mgt_refclk_p,
+    input  wire logic        sfp_mgt_refclk_n,
+
+    output wire logic        sfp_tx_disable_b,
+
+    /*
+     * Ethernet: 1000BASE-T
+     */
+    input  wire logic        phy_rgmii_rx_clk,
+    input  wire logic [3:0]  phy_rgmii_rxd,
+    input  wire logic        phy_rgmii_rx_ctl,
+    output wire logic        phy_rgmii_tx_clk,
+    output wire logic [3:0]  phy_rgmii_txd,
+    output wire logic        phy_rgmii_tx_ctl,
+
+    input  wire logic        phy_gmii_rx_clk,
+    input  wire logic [7:0]  phy_gmii_rxd,
+    input  wire logic        phy_gmii_rx_dv,
+    input  wire logic        phy_gmii_rx_er,
+    output wire logic        phy_gmii_gtx_clk,
+    input  wire logic        phy_gmii_tx_clk,
+    output wire logic [7:0]  phy_gmii_txd,
+    output wire logic        phy_gmii_tx_en,
+    output wire logic        phy_gmii_tx_er,
+
+    output wire logic        phy_reset_n,
+    input  wire logic        phy_int_n
+);
+
+assign led = sw;
+
+// XFCP
+assign uart_cts = 1'b0;
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
+
+taxi_xfcp_if_uart #(
+    .TX_FIFO_DEPTH(512),
+    .RX_FIFO_DEPTH(512)
+)
+xfcp_if_uart_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * UART interface
+     */
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+
+    /*
+     * XFCP downstream interface
+     */
+    .xfcp_dsp_ds(xfcp_ds),
+    .xfcp_dsp_us(xfcp_us),
+
+    /*
+     * Configuration
+     */
+    .prescale(16'(125000000/921600))
+);
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2]();
+
+taxi_xfcp_switch #(
+    .XFCP_ID_STR("KC705"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR("Taxi example"),
+    .PORTS($size(xfcp_sw_us))
+)
+xfcp_sw_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_ds),
+    .xfcp_usp_us(xfcp_us),
+
+    /*
+     * XFCP downstream ports
+     */
+    .xfcp_dsp_ds(xfcp_sw_ds),
+    .xfcp_dsp_us(xfcp_sw_us)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
+
+taxi_xfcp_mod_stats #(
+    .XFCP_ID_STR("Statistics"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR(""),
+    .STAT_COUNT_W(64),
+    .STAT_PIPELINE(2)
+)
+xfcp_stats_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[0]),
+    .xfcp_usp_us(xfcp_sw_us[0]),
+
+    /*
+     * Statistics increment input
+     */
+    .s_axis_stat(axis_stat)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2]();
+
+taxi_axis_arb_mux #(
+    .S_COUNT($size(axis_eth_stat)),
+    .UPDATE_TID(1'b0),
+    .ARB_ROUND_ROBIN(1'b1),
+    .ARB_LSB_HIGH_PRIO(1'b0)
+)
+stat_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream inputs (sink)
+     */
+    .s_axis(axis_eth_stat),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(axis_stat)
+);
+
+// I2C
+taxi_xfcp_mod_i2c_master #(
+    .XFCP_EXT_ID_STR("I2C"),
+    .DEFAULT_PRESCALE(16'(125000000/200000/4))
+)
+xfcp_mod_i2c_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[1]),
+    .xfcp_usp_us(xfcp_sw_us[1]),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o)
+);
+
+// BASE-T PHY
+assign phy_reset_n = !rst;
+
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
+
+if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
+
+    taxi_eth_mac_1g_gmii_fifo #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+        .PADDING_EN(1),
+        .MIN_FRAME_LEN(64),
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(0),
+        .STAT_UPDATE_PERIOD(1024),
+        .STAT_STR_EN(1),
+        .STAT_PREFIX_STR("GMII0"),
+        .TX_FIFO_DEPTH(16384),
+        .TX_FRAME_FIFO(1),
+        .RX_FIFO_DEPTH(16384),
+        .RX_FRAME_FIFO(1)
+    )
+    eth_mac_inst (
+        .gtx_clk(clk),
+        .gtx_rst(rst),
+        .logic_clk(clk),
+        .logic_rst(rst),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(axis_eth),
+        .m_axis_tx_cpl(axis_tx_cpl),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(axis_eth),
+
+        /*
+         * GMII interface
+         */
+        .gmii_rx_clk(phy_gmii_rx_clk),
+        .gmii_rxd(phy_gmii_rxd),
+        .gmii_rx_dv(phy_gmii_rx_dv),
+        .gmii_rx_er(phy_gmii_rx_er),
+        .gmii_tx_clk(phy_gmii_gtx_clk),
+        .mii_tx_clk(phy_gmii_tx_clk),
+        .gmii_txd(phy_gmii_txd),
+        .gmii_tx_en(phy_gmii_tx_en),
+        .gmii_tx_er(phy_gmii_tx_er),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk),
+        .stat_rst(rst),
+        .m_axis_stat(axis_eth_stat[0]),
+
+        /*
+         * Status
+         */
+        .tx_error_underflow(),
+        .tx_fifo_overflow(),
+        .tx_fifo_bad_frame(),
+        .tx_fifo_good_frame(),
+        .rx_error_bad_frame(),
+        .rx_error_bad_fcs(),
+        .rx_fifo_overflow(),
+        .rx_fifo_bad_frame(),
+        .rx_fifo_good_frame(),
+        .link_speed(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len(16'd9218),
+        .cfg_tx_ifg(8'd12),
+        .cfg_tx_enable(1'b1),
+        .cfg_rx_max_pkt_len(16'd9218),
+        .cfg_rx_enable(1'b1)
+    );
+
+end else if (BASET_PHY_TYPE == "RGMII") begin : baset_mac_rgmii
+
+    taxi_eth_mac_1g_rgmii_fifo #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+        .USE_CLK90(USE_CLK90),
+        .PADDING_EN(1),
+        .MIN_FRAME_LEN(64),
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(0),
+        .STAT_UPDATE_PERIOD(1024),
+        .STAT_STR_EN(1),
+        .STAT_PREFIX_STR("RGMII0"),
+        .TX_FIFO_DEPTH(16384),
+        .TX_FRAME_FIFO(1),
+        .RX_FIFO_DEPTH(16384),
+        .RX_FRAME_FIFO(1)
+    )
+    eth_mac_inst (
+        .gtx_clk(clk),
+        .gtx_clk90(clk90),
+        .gtx_rst(rst),
+        .logic_clk(clk),
+        .logic_rst(rst),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(axis_eth),
+        .m_axis_tx_cpl(axis_tx_cpl),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(axis_eth),
+
+        /*
+         * RGMII interface
+         */
+        .rgmii_rx_clk(phy_rgmii_rx_clk),
+        .rgmii_rxd(phy_rgmii_rxd),
+        .rgmii_rx_ctl(phy_rgmii_rx_ctl),
+        .rgmii_tx_clk(phy_rgmii_tx_clk),
+        .rgmii_txd(phy_rgmii_txd),
+        .rgmii_tx_ctl(phy_rgmii_tx_ctl),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk),
+        .stat_rst(rst),
+        .m_axis_stat(axis_eth_stat[0]),
+
+        /*
+         * Status
+         */
+        .tx_error_underflow(),
+        .tx_fifo_overflow(),
+        .tx_fifo_bad_frame(),
+        .tx_fifo_good_frame(),
+        .rx_error_bad_frame(),
+        .rx_error_bad_fcs(),
+        .rx_fifo_overflow(),
+        .rx_fifo_bad_frame(),
+        .rx_fifo_good_frame(),
+        .link_speed(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len(16'd9218),
+        .cfg_tx_ifg(8'd12),
+        .cfg_tx_enable(1'b1),
+        .cfg_rx_max_pkt_len(16'd9218),
+        .cfg_rx_enable(1'b1)
+    );
+
+    assign phy_gmii_gtx_clk = 1'b0;
+    assign phy_gmii_txd = '0;
+    assign phy_gmii_tx_en = 1'b0;
+    assign phy_gmii_tx_er = 1'b0;
+
+end
+
+// SFP+
+assign sfp_tx_disable_b = 1'b1;
+
+wire sfp_tx_clk[1];
+wire sfp_tx_rst[1];
+wire sfp_rx_clk[1];
+wire sfp_rx_rst[1];
+
+wire sfp_rx_status[1];
+
+wire sfp_gtpowergood;
+
+wire sfp_mgt_refclk;
+wire sfp_mgt_refclk_bufg;
+
+wire sfp_rst;
+
+taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[1]();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[1]();
+taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[1]();
+
+if (SIM) begin
+
+    assign sfp_mgt_refclk = sfp_mgt_refclk_p;
+    assign sfp_mgt_refclk_bufg = sfp_mgt_refclk;
+
+end else begin
+
+    IBUFDS_GTE2 ibufds_gte2_sfp_mgt_refclk_inst (
+        .I     (sfp_mgt_refclk_p),
+        .IB    (sfp_mgt_refclk_n),
+        .CEB   (1'b0),
+        .O     (sfp_mgt_refclk),
+        .ODIV2 ()
+    );
+
+    BUFG bufg_sfp_mgt_refclk_inst (
+        .I (sfp_mgt_refclk),
+        .O (sfp_mgt_refclk_bufg)
+    );
+
+end
+
+taxi_sync_reset #(
+    .N(4)
+)
+sfp_sync_reset_inst (
+    .clk(sfp_mgt_refclk_bufg),
+    .rst(rst),
+    .out(sfp_rst)
+);
+
+wire sfp_tx_p_int[1];
+wire sfp_tx_n_int[1];
+
+assign sfp_tx_p = sfp_tx_p_int[0];
+assign sfp_tx_n = sfp_tx_n_int[0];
+
+// synthesis translate_off
+`define SIM
+// synthesis translate_on
+
+taxi_eth_mac_25g_us #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+
+    .CNT(1),
+
+    // GT config
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+
+    // GT type
+    .GT_TYPE("GTX"),
+
+    // GT parameters
+    // workaround for verilator bug
+    `ifndef SIM
+    .GT_TX_DIFFCTRL('{1{5'd8}}),
+    .GT_TX_POLARITY('{1{SFP_INVERT}}),
+    .GT_RX_POLARITY('{1{SFP_INVERT}}),
+    `endif
+
+    // MAC/PHY config
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .DATA_W(MAC_DATA_W),
+    .PADDING_EN(1'b1),
+    .DIC_EN(1'b1),
+    .MIN_FRAME_LEN(64),
+    .PTP_TS_EN(1'b0),
+    .PTP_TS_FMT_TOD(1'b1),
+    .PTP_TS_W(96),
+    .PRBS31_EN(1'b0),
+    .TX_SERDES_PIPELINE(1),
+    .RX_SERDES_PIPELINE(1),
+    .COUNT_125US(125000/6.4),
+    .STAT_EN(1),
+    .STAT_TX_LEVEL(1),
+    .STAT_RX_LEVEL(1),
+    .STAT_ID_BASE(16+16),
+    .STAT_UPDATE_PERIOD(1024)
+    // workaround for verilator bug
+    `ifndef SIM
+    ,
+    .STAT_STR_EN(1),
+    .STAT_PREFIX_STR('{"SFP"})
+    `endif
+)
+sfp_mac_inst (
+    .xcvr_ctrl_clk(clk),
+    .xcvr_ctrl_rst(sfp_rst),
+
+    /*
+     * Common
+     */
+    .xcvr_gtpowergood_out(sfp_gtpowergood),
+    .xcvr_gtrefclk00_in(sfp_mgt_refclk),
+    .xcvr_qpll0pd_in(1'b0),
+    .xcvr_qpll0reset_in(1'b0),
+    .xcvr_qpll0pcierate_in(3'd0),
+    .xcvr_qpll0lock_out(),
+    .xcvr_qpll0clk_out(),
+    .xcvr_qpll0refclk_out(),
+    .xcvr_gtrefclk01_in(sfp_mgt_refclk),
+    .xcvr_qpll1pd_in(1'b0),
+    .xcvr_qpll1reset_in(1'b0),
+    .xcvr_qpll1pcierate_in(3'd0),
+    .xcvr_qpll1lock_out(),
+    .xcvr_qpll1clk_out(),
+    .xcvr_qpll1refclk_out(),
+
+    /*
+     * Serial data
+     */
+    .xcvr_txp(sfp_tx_p_int),
+    .xcvr_txn(sfp_tx_n_int),
+    .xcvr_rxp('{1{sfp_rx_p}}),
+    .xcvr_rxn('{1{sfp_rx_n}}),
+
+    /*
+     * MAC clocks
+     */
+    .rx_clk(sfp_rx_clk),
+    .rx_rst_in('{1{1'b0}}),
+    .rx_rst_out(sfp_rx_rst),
+    .tx_clk(sfp_tx_clk),
+    .tx_rst_in('{1{1'b0}}),
+    .tx_rst_out(sfp_tx_rst),
+    .ptp_sample_clk('{1{1'b0}}),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_sfp_tx),
+    .m_axis_tx_cpl(axis_sfp_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_sfp_rx),
+
+    /*
+     * PTP clock
+     */
+    .tx_ptp_ts('{1{'0}}),
+    .tx_ptp_ts_step('{1{1'b0}}),
+    .rx_ptp_ts('{1{'0}}),
+    .rx_ptp_ts_step('{1{1'b0}}),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req('{1{1'b0}}),
+    .tx_lfc_resend('{1{1'b0}}),
+    .rx_lfc_en('{1{1'b0}}),
+    .rx_lfc_req(),
+    .rx_lfc_ack('{1{1'b0}}),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req('{1{'0}}),
+    .tx_pfc_resend('{1{1'b0}}),
+    .rx_pfc_en('{1{'0}}),
+    .rx_pfc_req(),
+    .rx_pfc_ack('{1{'0}}),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en('{1{1'b0}}),
+    .tx_pause_req('{1{1'b0}}),
+    .tx_pause_ack(),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(clk),
+    .stat_rst(rst),
+    .m_axis_stat(axis_eth_stat[1]),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(),
+    .stat_tx_byte(),
+    .stat_tx_pkt_len(),
+    .stat_tx_pkt_ucast(),
+    .stat_tx_pkt_mcast(),
+    .stat_tx_pkt_bcast(),
+    .stat_tx_pkt_vlan(),
+    .stat_tx_pkt_good(),
+    .stat_tx_pkt_bad(),
+    .stat_tx_err_oversize(),
+    .stat_tx_err_user(),
+    .stat_tx_err_underflow(),
+    .rx_start_packet(),
+    .rx_error_count(),
+    .rx_block_lock(),
+    .rx_high_ber(),
+    .rx_status(sfp_rx_status),
+    .stat_rx_byte(),
+    .stat_rx_pkt_len(),
+    .stat_rx_pkt_fragment(),
+    .stat_rx_pkt_jabber(),
+    .stat_rx_pkt_ucast(),
+    .stat_rx_pkt_mcast(),
+    .stat_rx_pkt_bcast(),
+    .stat_rx_pkt_vlan(),
+    .stat_rx_pkt_good(),
+    .stat_rx_pkt_bad(),
+    .stat_rx_err_oversize(),
+    .stat_rx_err_bad_fcs(),
+    .stat_rx_err_bad_block(),
+    .stat_rx_err_framing(),
+    .stat_rx_err_preamble(),
+    .stat_rx_fifo_drop('{1{1'b0}}),
+    .stat_tx_mcf(),
+    .stat_rx_mcf(),
+    .stat_tx_lfc_pkt(),
+    .stat_tx_lfc_xon(),
+    .stat_tx_lfc_xoff(),
+    .stat_tx_lfc_paused(),
+    .stat_tx_pfc_pkt(),
+    .stat_tx_pfc_xon(),
+    .stat_tx_pfc_xoff(),
+    .stat_tx_pfc_paused(),
+    .stat_rx_lfc_pkt(),
+    .stat_rx_lfc_xon(),
+    .stat_rx_lfc_xoff(),
+    .stat_rx_lfc_paused(),
+    .stat_rx_pfc_pkt(),
+    .stat_rx_pfc_xon(),
+    .stat_rx_pfc_xoff(),
+    .stat_rx_pfc_paused(),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len('{1{16'd9218}}),
+    .cfg_tx_ifg('{1{8'd12}}),
+    .cfg_tx_enable('{1{1'b1}}),
+    .cfg_rx_max_pkt_len('{1{16'd9218}}),
+    .cfg_rx_enable('{1{1'b1}}),
+    .cfg_tx_prbs31_enable('{1{1'b0}}),
+    .cfg_rx_prbs31_enable('{1{1'b0}}),
+    .cfg_mcf_rx_eth_dst_mcast('{1{48'h01_80_C2_00_00_01}}),
+    .cfg_mcf_rx_check_eth_dst_mcast('{1{1'b1}}),
+    .cfg_mcf_rx_eth_dst_ucast('{1{48'd0}}),
+    .cfg_mcf_rx_check_eth_dst_ucast('{1{1'b0}}),
+    .cfg_mcf_rx_eth_src('{1{48'd0}}),
+    .cfg_mcf_rx_check_eth_src('{1{1'b0}}),
+    .cfg_mcf_rx_eth_type('{1{16'h8808}}),
+    .cfg_mcf_rx_opcode_lfc('{1{16'h0001}}),
+    .cfg_mcf_rx_check_opcode_lfc('{1{1'b1}}),
+    .cfg_mcf_rx_opcode_pfc('{1{16'h0101}}),
+    .cfg_mcf_rx_check_opcode_pfc('{1{1'b1}}),
+    .cfg_mcf_rx_forward('{1{1'b0}}),
+    .cfg_mcf_rx_enable('{1{1'b0}}),
+    .cfg_tx_lfc_eth_dst('{1{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_lfc_eth_src('{1{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_lfc_eth_type('{1{16'h8808}}),
+    .cfg_tx_lfc_opcode('{1{16'h0001}}),
+    .cfg_tx_lfc_en('{1{1'b0}}),
+    .cfg_tx_lfc_quanta('{1{16'hffff}}),
+    .cfg_tx_lfc_refresh('{1{16'h7fff}}),
+    .cfg_tx_pfc_eth_dst('{1{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_pfc_eth_src('{1{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_pfc_eth_type('{1{16'h8808}}),
+    .cfg_tx_pfc_opcode('{1{16'h0101}}),
+    .cfg_tx_pfc_en('{1{1'b0}}),
+    .cfg_tx_pfc_quanta('{1{'{8{16'hffff}}}}),
+    .cfg_tx_pfc_refresh('{1{'{8{16'h7fff}}}}),
+    .cfg_rx_lfc_opcode('{1{16'h0001}}),
+    .cfg_rx_lfc_en('{1{1'b0}}),
+    .cfg_rx_pfc_opcode('{1{16'h0101}}),
+    .cfg_rx_pfc_en('{1{1'b0}})
+);
+
+for (genvar n = 0; n < 1; n = n + 1) begin : sfp_ch
+
+    taxi_axis_async_fifo #(
+        .DEPTH(16384),
+        .RAM_PIPELINE(2),
+        .FRAME_FIFO(1),
+        .USER_BAD_FRAME_VALUE(1'b1),
+        .USER_BAD_FRAME_MASK(1'b1),
+        .DROP_OVERSIZE_FRAME(1),
+        .DROP_BAD_FRAME(1),
+        .DROP_WHEN_FULL(1)
+    )
+    ch_fifo (
+        /*
+            * AXI4-Stream input (sink)
+            */
+        .s_clk(sfp_rx_clk[n]),
+        .s_rst(sfp_rx_rst[n]),
+        .s_axis(axis_sfp_rx[n]),
+
+        /*
+            * AXI4-Stream output (source)
+            */
+        .m_clk(sfp_tx_clk[n]),
+        .m_rst(sfp_tx_rst[n]),
+        .m_axis(axis_sfp_tx[n]),
+
+        /*
+            * Pause
+            */
+        .s_pause_req(1'b0),
+        .s_pause_ack(),
+        .m_pause_req(1'b0),
+        .m_pause_ack(),
+
+        /*
+            * Status
+            */
+        .s_status_depth(),
+        .s_status_depth_commit(),
+        .s_status_overflow(),
+        .s_status_bad_frame(),
+        .s_status_good_frame(),
+        .m_status_depth(),
+        .m_status_depth_commit(),
+        .m_status_overflow(),
+        .m_status_bad_frame(),
+        .m_status_good_frame()
+    );
+
+end
+
+endmodule
+
+`resetall

src/eth/example/KC705/fpga_10g/rtl/si5324_i2c_init.sv

@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2015-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C init
+ */
+module si5324_i2c_init #
+(
+    parameter logic SIM_SPEEDUP = 1'b0
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * I2C master interface
+     */
+    taxi_axis_if.src   m_axis_cmd,
+    taxi_axis_if.src   m_axis_tx,
+
+    /*
+     * Status
+     */
+    output wire logic  busy,
+
+    /*
+     * Configuration
+     */
+    input  wire logic  start
+);
+
+/*
+
+Generic module for I2C bus initialization.  Good for use when multiple devices
+on an I2C bus must be initialized on system start without intervention of a
+general-purpose processor.
+
+Copy this file and change init_data and INIT_DATA_LEN as needed.
+
+This module can be used in two modes: simple device initialization, or multiple
+device initialization.  In multiple device mode, the same initialization sequence
+can be performed on multiple different device addresses.
+
+To use single device mode, only use the start write to address and write data commands.
+The module will generate the I2C commands in sequential order.  Terminate the list
+with a 0 entry.
+
+To use the multiple device mode, use the start data and start address block commands
+to set up lists of initialization data and device addresses.  The module enters
+multiple device mode upon seeing a start data block command.  The module stores the
+offset of the start of the data block and then skips ahead until it reaches a start
+address block command.  The module will store the offset to the address block and
+read the first address in the block.  Then it will jump back to the data block
+and execute it, substituting the stored address for each current address write
+command.  Upon reaching the start address block command, the module will read out the
+next address and start again at the top of the data block.  If the module encounters
+a start data block command while looking for an address, then it will store a new data
+offset and then look for a start address block command.  Terminate the list with a 0
+entry.  Normal address commands will operate normally inside a data block.
+
+Commands:
+
+00 0000000 : halt
+00 0000001 : exit multiple device mode
+00 0000011 : start write to current address
+00 0001000 : start address block
+00 0001001 : start data block
+00 001dddd : delay 2**(16+d) cycles
+00 1000001 : send I2C stop
+01 aaaaaaa : start write to address
+1 dddddddd : write 8-bit data
+
+Examples
+
+write 0x11223344 to register 0x0004 on device at 0x50
+
+01 1010000  start write to 0x50
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+0 00000000  halt
+
+write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
+
+00 0001001  start data block
+00 0000011  start write to current address
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+00 0001000  start address block
+01 1010000  address 0x50
+01 1010001  address 0x51
+01 1010010  address 0x52
+01 1010011  address 0x53
+00 0000001  exit multi-dev mode
+00 0000000  halt
+
+*/
+
+// check configuration
+if (m_axis_cmd.DATA_W < 12)
+    $fatal(0, "Command interface width must be at least 12 bits (instance %m)");
+
+if (m_axis_tx.DATA_W != 8)
+    $fatal(0, "Data interface width must be 8 bits (instance %m)");
+
+function [8:0] cmd_start(input [6:0] addr);
+    cmd_start = {2'b01, addr};
+endfunction
+
+function [8:0] cmd_wr(input [7:0] data);
+    cmd_wr = {1'b1, data};
+endfunction
+
+function [8:0] cmd_stop();
+    cmd_stop = {2'b00, 7'b1000001};
+endfunction
+
+function [8:0] cmd_delay(input [3:0] d);
+    cmd_delay = {2'b00, 3'b001, d};
+endfunction
+
+function [8:0] cmd_halt();
+    cmd_halt = 9'd0;
+endfunction
+
+function [8:0] blk_start_data();
+    blk_start_data = {2'b00, 7'b0001001};
+endfunction
+
+function [8:0] blk_start_addr();
+    blk_start_addr = {2'b00, 7'b0001000};
+endfunction
+
+function [8:0] cmd_start_cur();
+    cmd_start_cur = {2'b00, 7'b0000011};
+endfunction
+
+function [8:0] cmd_exit();
+    cmd_exit = {2'b00, 7'b0000001};
+endfunction
+
+// init_data ROM
+localparam INIT_DATA_LEN = 38;
+
+logic [8:0] init_data [INIT_DATA_LEN-1:0];
+
+initial begin
+    // Initial delay
+    init_data[0] = cmd_delay(6); // delay 30 ms
+    // Select Si5324
+    init_data[1]  = cmd_start(7'h74);
+    init_data[2]  = cmd_wr(8'h80);
+    init_data[3]  = cmd_stop();
+    // init Si5324 registers
+    init_data[4] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[5] = cmd_wr(8'd0);  // register 0
+    init_data[6] = cmd_wr(8'h54); // Reg 0: Free run, Clock off before ICAL, Bypass off (normal operation)
+    init_data[7] = cmd_wr(8'hE4); // Reg 1: CKIN2 second priority, CKIN1 first priority
+    init_data[8] = cmd_wr(8'h12); // Reg 2: BWSEL = 1
+    init_data[9] = cmd_wr(8'h15); // Reg 3: CKIN1 selected, Digital Hold off, Output clocks disabled during ICAL
+    init_data[10] = cmd_wr(8'h92); // Reg 4: Automatic Revertive, HIST_DEL = 0x12
+    init_data[11] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[12] = cmd_wr(8'd10); // register 10
+    init_data[13] = cmd_wr(8'h08); // Reg 10: CKOUT2 disabled, CKOUT1 enabled
+    init_data[14] = cmd_wr(8'h40); // Reg 11: CKIN2 enabled, CKIN1 enabled
+    init_data[15] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[16] = cmd_wr(8'd25); // register 25
+    init_data[17] = cmd_wr(8'hA0); // Reg 25: N1_HS = 9
+    init_data[18] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[19] = cmd_wr(8'd31); // register 31
+    init_data[20] = cmd_wr(8'h00); // Regs 31,32,33: NC1_LS = 4
+    init_data[21] = cmd_wr(8'h00);
+    init_data[22] = cmd_wr(8'h03);
+    init_data[23] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[24] = cmd_wr(8'd40); // register 40
+    init_data[25] = cmd_wr(8'hC2); // Regs 40,41,42: N2_HS = 10, N2_LS = 150000
+    init_data[26] = cmd_wr(8'h49);
+    init_data[27] = cmd_wr(8'hEF);
+    init_data[28] = cmd_wr(8'h00); // Regs 43,44,45: N31 = 30475
+    init_data[29] = cmd_wr(8'h77);
+    init_data[30] = cmd_wr(8'h0B);
+    init_data[31] = cmd_wr(8'h00); // Regs 46,47,48: N32 = 30475
+    init_data[32] = cmd_wr(8'h77);
+    init_data[33] = cmd_wr(8'h0B);
+    init_data[34] = cmd_start(7'h68); // start write to 0x68 (Si5324)
+    init_data[35] = cmd_wr(8'd136); // register 136
+    init_data[36] = cmd_wr(8'h40); // Reg 136: ICAL = 1
+    init_data[37] = cmd_halt(); // stop
+end
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_RUN = 3'd1,
+    STATE_TABLE_1 = 3'd2,
+    STATE_TABLE_2 = 3'd3,
+    STATE_TABLE_3 = 3'd4;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+localparam AW = $clog2(INIT_DATA_LEN);
+
+logic [8:0] init_data_reg = '0;
+
+logic [AW-1:0] address_reg = '0, address_next;
+logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
+logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
+
+logic [6:0] cur_address_reg = '0, cur_address_next;
+
+logic [31:0] delay_counter_reg = '0, delay_counter_next;
+
+logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
+logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
+logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
+logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
+logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
+
+logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
+logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
+
+logic start_flag_reg = 1'b0, start_flag_next;
+
+logic busy_reg = 1'b0;
+
+assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
+assign m_axis_cmd.tdata[7]   = m_axis_cmd_start_reg;
+assign m_axis_cmd.tdata[8]   = 1'b0; // read
+assign m_axis_cmd.tdata[9]   = m_axis_cmd_write_reg;
+assign m_axis_cmd.tdata[10]  = 1'b0; // write multi
+assign m_axis_cmd.tdata[11]  = m_axis_cmd_stop_reg;
+assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
+assign m_axis_cmd.tlast = 1'b1;
+assign m_axis_cmd.tid = '0;
+assign m_axis_cmd.tdest = '0;
+assign m_axis_cmd.tuser = '0;
+
+assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
+assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
+assign m_axis_tx.tlast = 1'b1;
+assign m_axis_tx.tid = '0;
+assign m_axis_tx.tdest = '0;
+assign m_axis_tx.tuser = '0;
+
+assign busy = busy_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    address_next = address_reg;
+    address_ptr_next = address_ptr_reg;
+    data_ptr_next = data_ptr_reg;
+
+    cur_address_next = cur_address_reg;
+
+    delay_counter_next = delay_counter_reg;
+
+    m_axis_cmd_address_next = m_axis_cmd_address_reg;
+    m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
+
+    m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
+    m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
+
+    start_flag_next = start_flag_reg;
+
+    if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
+        // wait for output registers to clear
+        state_next = state_reg;
+    end else if (delay_counter_reg != 0) begin
+        // delay
+        delay_counter_next = delay_counter_reg - 1;
+        state_next = state_reg;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // wait for start signal
+                if (!start_flag_reg && start) begin
+                    address_next = '0;
+                    start_flag_next = 1'b1;
+                    state_next = STATE_RUN;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_RUN: begin
+                // process commands
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end
+            end
+            STATE_TABLE_1: begin
+                // find address table start
+                if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end
+            end
+            STATE_TABLE_2: begin
+                // find next address
+                if (init_data_reg[8:7] == 2'b01) begin
+                    // write address command
+                    // store address and move to data table
+                    cur_address_next = init_data_reg[6:0];
+                    address_ptr_next = address_reg + 1;
+                    address_next = data_ptr_reg;
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end
+            end
+            STATE_TABLE_3: begin
+                // process data table with selected address
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000000011) begin
+                    // write current address
+                    m_axis_cmd_address_next = cur_address_reg;
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_next = address_ptr_reg;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_3;
+                end
+            end
+            default: begin
+                // invalid state
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    delay_counter_reg <= delay_counter_next;
+
+    m_axis_cmd_address_reg <= m_axis_cmd_address_next;
+    m_axis_cmd_start_reg <= m_axis_cmd_start_next;
+    m_axis_cmd_write_reg <= m_axis_cmd_write_next;
+    m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
+    m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
+
+    m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
+    m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
+
+    start_flag_reg <= start && start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        init_data_reg <= '0;
+
+        address_reg <= '0;
+        address_ptr_reg <= '0;
+        data_ptr_reg <= '0;
+
+        cur_address_reg <= '0;
+
+        delay_counter_reg <= '0;
+
+        m_axis_cmd_valid_reg <= 1'b0;
+
+        m_axis_tx_tvalid_reg <= 1'b0;
+
+        start_flag_reg <= 1'b0;
+
+        busy_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/eth/example/KC705/fpga_10g/tb/fpga_core/Makefile

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"kintex7\""
+export PARAM_USE_CLK90 := "1'b1"
+export PARAM_BASET_PHY_TYPE := "\"GMII\""
+export PARAM_SFP_INVERT := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/example/KC705/fpga_10g/tb/fpga_core/baser.py

@@ -0,0 +1 @@
+../../lib/taxi/src/eth/tb/baser.py

src/eth/example/KC705/fpga_10g/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,309 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import sys
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, Combine
+
+from cocotbext.eth import XgmiiFrame
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, GmiiPhy, RgmiiPhy
+from cocotbext.uart import UartSource, UartSink
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if hasattr(dut, "baset_mac_gmii"):
+            self.baset_phy = GmiiPhy(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en, dut.phy_gmii_tx_clk, dut.phy_gmii_gtx_clk,
+                dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv, dut.phy_gmii_rx_clk, speed=speed)
+        elif hasattr(dut, "baset_mac_rgmii"):
+            self.baset_phy = RgmiiPhy(dut.phy_rgmii_txd, dut.phy_rgmii_tx_ctl, dut.phy_rgmii_tx_clk,
+                dut.phy_rgmii_rxd, dut.phy_rgmii_rx_ctl, dut.phy_rgmii_rx_clk, speed=speed)
+
+        self.sfp_sources = []
+        self.sfp_sinks = []
+
+        cocotb.start_soon(Clock(dut.sfp_mgt_refclk_p, 6.4, units="ns").start())
+
+        for ch in dut.sfp_mac_inst.ch:
+            gt_inst = ch.ch_inst.gt.gt_inst
+
+            if ch.ch_inst.CFG_LOW_LATENCY.value:
+                clk = 3.102
+                gbx_cfg = (66, [64, 65])
+            else:
+                clk = 3.2
+                gbx_cfg = None
+
+            cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+            cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+            self.sfp_sources.append(BaseRSerdesSource(
+                data=gt_inst.serdes_rx_data,
+                data_valid=gt_inst.serdes_rx_data_valid,
+                hdr=gt_inst.serdes_rx_hdr,
+                hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                clock=gt_inst.rx_clk,
+                slip=gt_inst.serdes_rx_bitslip,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+            self.sfp_sinks.append(BaseRSerdesSink(
+                data=gt_inst.serdes_tx_data,
+                data_valid=gt_inst.serdes_tx_data_valid,
+                hdr=gt_inst.serdes_tx_hdr,
+                hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                clock=gt_inst.tx_clk,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+
+        self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
+        self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
+
+        dut.btnu.setimmediatevalue(0)
+        dut.btnl.setimmediatevalue(0)
+        dut.btnd.setimmediatevalue(0)
+        dut.btnr.setimmediatevalue(0)
+        dut.btnc.setimmediatevalue(0)
+        dut.sw.setimmediatevalue(0)
+        dut.uart_rts.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_clk())
+
+    async def init(self):
+        self.dut.rst.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 0
+
+    async def _run_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.clk.value = 1
+            await t
+            self.dut.clk90.value = 1
+            await t
+            self.dut.clk.value = 0
+            await t
+            self.dut.clk90.value = 0
+            await t
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("MAC test done")
+
+
+async def mac_test_10g(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk)
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    tb.log.info("Start BASE-T MAC loopback test")
+
+    if hasattr(dut, "baset_mac_gmii"):
+        tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
+    elif hasattr(dut, "baset_mac_rgmii"):
+        tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
+
+    for k in range(len(tb.sfp_sources)):
+        tb.log.info("Start SFP %d 10G MAC loopback test", k)
+        tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("phy_type", ["GMII", "RGMII"])
+def test_fpga_core(request, phy_type):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_gmii_fifo.f"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+        os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"artix7\""
+    parameters['USE_CLK90'] = "1'b1"
+    parameters['BASET_PHY_TYPE'] = f"\"{phy_type}\""
+    parameters['SFP_INVERT'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/example/KCU105/fpga/fpga.xdc

@@ -121,13 +121,14 @@ set_false_path -from [get_ports {uart_rxd uart_rts}]
 set_input_delay 0 [get_ports {uart_rxd uart_rts}]
 
 # I2C interface
-#set_property -dict {LOC J24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
-#set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC J24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC AP10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
 
-#set_false_path -to [get_ports {i2c_sda i2c_scl}]
-#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
-#set_false_path -from [get_ports {i2c_sda i2c_scl}]
-#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+set_false_path -to [get_ports {i2c_sda i2c_scl}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
 
 # Gigabit Ethernet SGMII PHY
 set_property -dict {LOC P24  IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p]
@@ -376,14 +377,14 @@ set_output_delay 0 [get_ports {sfp_tx_disable_b[*]}]
 #set_property -dict {LOC N3} [get_ports {fmc_hpc_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A35 DP4_C2M_N
 #set_property -dict {LOC M2} [get_ports {fmc_hpc_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A14 DP4_M2C_P
 #set_property -dict {LOC M1} [get_ports {fmc_hpc_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A15 DP4_M2C_N
-#set_property -dict {LOC L4} [get_ports {fmc_hpc_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A38 DP5_C2M_P
-#set_property -dict {LOC L3} [get_ports {fmc_hpc_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A39 DP5_C2M_N
-#set_property -dict {LOC K2} [get_ports {fmc_hpc_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A18 DP5_M2C_P
-#set_property -dict {LOC K1} [get_ports {fmc_hpc_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A19 DP5_M2C_N
-#set_property -dict {LOC J4} [get_ports {fmc_hpc_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B36 DP6_C2M_P
-#set_property -dict {LOC J3} [get_ports {fmc_hpc_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B37 DP6_C2M_N
-#set_property -dict {LOC H2} [get_ports {fmc_hpc_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B16 DP6_M2C_P
-#set_property -dict {LOC H1} [get_ports {fmc_hpc_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B17 DP6_M2C_N
+#set_property -dict {LOC J4} [get_ports {fmc_hpc_dp_c2m_p[5]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B36 DP5_C2M_P
+#set_property -dict {LOC J3} [get_ports {fmc_hpc_dp_c2m_n[5]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B37 DP5_C2M_N
+#set_property -dict {LOC H2} [get_ports {fmc_hpc_dp_m2c_p[5]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B16 DP5_M2C_P
+#set_property -dict {LOC H1} [get_ports {fmc_hpc_dp_m2c_n[5]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B17 DP5_M2C_N
+#set_property -dict {LOC L4} [get_ports {fmc_hpc_dp_c2m_p[6]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A38 DP6_C2M_P
+#set_property -dict {LOC L3} [get_ports {fmc_hpc_dp_c2m_n[6]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A39 DP6_C2M_N
+#set_property -dict {LOC K2} [get_ports {fmc_hpc_dp_m2c_p[6]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A18 DP6_M2C_P
+#set_property -dict {LOC K1} [get_ports {fmc_hpc_dp_m2c_n[6]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A19 DP6_M2C_N
 #set_property -dict {LOC G4} [get_ports {fmc_hpc_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B32 DP7_C2M_P
 #set_property -dict {LOC G3} [get_ports {fmc_hpc_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B33 DP7_C2M_N
 #set_property -dict {LOC F2} [get_ports {fmc_hpc_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B12 DP7_M2C_P

src/eth/example/KCU105/fpga/fpga_10g/Makefile

@@ -22,6 +22,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KCU105/fpga/fpga_1g/Makefile

@@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv
 SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KCU105/fpga/rtl/fpga.sv

@@ -54,6 +54,13 @@ module fpga #
     input  wire logic        uart_rts,
     output wire logic        uart_cts,
 
+    /*
+     * I2C
+     */
+    inout  wire logic        i2c_scl,
+    inout  wire logic        i2c_sda,
+    output wire logic        i2c_mux_reset,
+
     /*
      * Ethernet: 1000BASE-T SGMII
      */
@@ -250,6 +257,17 @@ sync_signal_inst (
 
 wire [7:0] led_int;
 
+// I2C
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+
 // SGMII interface to PHY
 wire phy_gmii_clk_int;
 wire phy_gmii_rst_int;
@@ -573,6 +591,14 @@ core_inst (
     .uart_rts(uart_rts_int),
     .uart_cts(uart_cts),
 
+    /*
+     * I2C
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o),
+
     /*
      * Ethernet: 1000BASE-T SGMII
      */

src/eth/example/KCU105/fpga/rtl/fpga_core.sv

@@ -53,6 +53,14 @@ module fpga_core #
     input  wire logic        uart_rts,
     output wire logic        uart_cts,
 
+    /*
+     * I2C
+     */
+    input  wire logic        i2c_scl_i,
+    output wire logic        i2c_scl_o,
+    input  wire logic        i2c_sda_i,
+    output wire logic        i2c_sda_o,
+
     /*
      * Ethernet: 1000BASE-T
      */
@@ -134,7 +142,7 @@ xfcp_if_uart_inst (
     .prescale(16'(125000000/921600))
 );
 
-taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2]();
 
 taxi_xfcp_switch #(
     .XFCP_ID_STR("KCU105"),
@@ -207,10 +215,34 @@ stat_mux_inst (
     .m_axis(axis_stat)
 );
 
+// I2C
+taxi_xfcp_mod_i2c_master #(
+    .XFCP_EXT_ID_STR("I2C"),
+    .DEFAULT_PRESCALE(16'(125000000/200000/4))
+)
+xfcp_mod_i2c_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[1]),
+    .xfcp_usp_us(xfcp_sw_us[1]),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o)
+);
+
 // BASE-T PHY
 assign phy_reset_n = !rst;
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
 
 taxi_eth_mac_1g_fifo #(
@@ -300,10 +332,10 @@ assign sfp_tx_disable_b = '1;
 
 if (SFP_RATE == 0) begin : sfp_mac
 
-    taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp0_eth();
+    taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp0_eth();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp0_tx_cpl();
 
-    taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp1_eth();
+    taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp1_eth();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp1_tx_cpl();
 
     taxi_eth_mac_1g_fifo #(
@@ -487,9 +519,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_tx[2]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
-    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_rx[2]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2]();
 
     if (SIM) begin
 

src/eth/example/KCU105/fpga/tb/fpga_core/Makefile

@@ -27,6 +27,7 @@ VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv

src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py

@@ -290,6 +290,7 @@ def test_fpga_core(request, sfp_rate):
         os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
         os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
         os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),

src/eth/example/KR260/fpga/rtl/fpga_core.sv

@@ -99,11 +99,11 @@ module fpga_core #
 assign phy2_reset_n = !rst;
 assign phy3_reset_n = !rst;
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy2_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_phy2_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy2_tx_cpl();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_phy2_stat();
 
-taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy3_eth();
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_phy3_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy3_tx_cpl();
 taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_phy3_stat();
 
@@ -256,7 +256,7 @@ assign sfp_tx_disable = 1'b0;
 
 if (SFP_RATE == 0) begin : sfp_mac
 
-    taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
+    taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_eth();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
     taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
@@ -353,9 +353,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_tx[0:0]();
-    taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[0:0]();
-    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_rx[0:0]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[1]();
+    taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[1]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[1]();
     taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
     if (SIM) begin

src/eth/example/NetFPGA_SUME/fpga/README.md

@@ -0,0 +1,34 @@
+# Taxi Example Design for NetFPGA SUME
+
+## Introduction
+
+This example design targets the Digilent NetFPGA SUME FPGA board.
+
+The design places looped-back MACs on the SFP+ cages, as well as XFCP on the USB UART for monitoring and control.
+
+*  USB UART
+    *  XFCP (3 Mbaud)
+*  SFP+ cages
+    *  Looped-back 10GBASE-R MACs via GTH transceivers
+
+## Board details
+
+*  FPGA: XC7VX690T-3FFG1761
+*  USB UART: FTDI FT2232HQ
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.

src/eth/example/NetFPGA_SUME/fpga/common/vivado.mk

@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/eth/example/NetFPGA_SUME/fpga/fpga.xdc

@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx VC709
+# part: xc7vx690tffg1761-2
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+
+# 200 MHz system clock
+set_property -dict {LOC H19  IOSTANDARD LVDS} [get_ports clk_200mhz_p]
+set_property -dict {LOC G18  IOSTANDARD LVDS} [get_ports clk_200mhz_n]
+create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
+
+# 200 MHz QDRII A/B MIG clock
+#set_property -dict {LOC AD32 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_p]
+#set_property -dict {LOC AD33 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_n]
+#create_clock -period 5 -name clk_qdrii_200mhz [get_ports clk_qdrii_200mhz_p]
+
+# 200 MHz QDRII C MIG clock
+#set_property -dict {LOC AU14 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_p]
+#set_property -dict {LOC AU13 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_n]
+#create_clock -period 5 -name clk_qdriic_200mhz [get_ports clk_qdriic_200mhz_p]
+
+# 233.33 MHz DDR3 MIG clock
+#set_property -dict {LOC E34  IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_p]
+#set_property -dict {LOC E35  IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_n]
+#create_clock -period 4.286 -name clk_ddr_233mhz [get_ports clk_ddr_233mhz_p]
+
+# LEDs
+set_property -dict {LOC G13  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
+set_property -dict {LOC L15  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
+set_property -dict {LOC AL22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
+set_property -dict {LOC BA20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
+set_property -dict {LOC AY18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][0]}]
+set_property -dict {LOC AY17 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][1]}]
+set_property -dict {LOC P31  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][0]}]
+set_property -dict {LOC K32  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][1]}]
+set_property -dict {LOC AR22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
+set_property -dict {LOC AR23 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
+
+set_false_path -to [get_ports {sfp_led[*][*] led[*]}]
+set_output_delay 0 [get_ports {sfp_led[*][*] led[*]}]
+
+# Push buttons
+set_property -dict {LOC AR13 IOSTANDARD LVCMOS15} [get_ports {btn[0]}]
+set_property -dict {LOC BB12 IOSTANDARD LVCMOS15} [get_ports {btn[1]}]
+
+set_false_path -from [get_ports {btn[*]}]
+set_input_delay 0 [get_ports {btn[*]}]
+
+# UART (IC47 FT2232HQ)
+set_property -dict {LOC BA19 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# IC47.38 RXD_I
+set_property -dict {LOC AY19 IOSTANDARD LVCMOS15} [get_ports {uart_rxd}] ;# IC47.39 TXD_O
+set_property -dict {LOC BB16 IOSTANDARD LVCMOS15} [get_ports {uart_rts}] ;# IC47.40 RTS_O_B
+set_property -dict {LOC BA16 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# IC47.41 CTS_I_B
+
+set_false_path -to [get_ports {uart_txd uart_cts}]
+set_output_delay 0 [get_ports {uart_txd uart_cts}]
+set_false_path -from [get_ports {uart_rxd uart_rts}]
+set_input_delay 0 [get_ports {uart_rxd uart_rts}]
+
+# I2C interface
+set_property -dict {LOC AK24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_scl]
+set_property -dict {LOC AK25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_sda]
+set_property -dict {LOC AM39 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports i2c_mux_reset]
+
+set_false_path -to [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# SFP+ Interfaces
+set_property -dict {LOC A6  } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC A5  } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B4  } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B3  } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B8  } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B7  } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC C2  } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC C1  } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC C6  } [get_ports {sfp_rx_p[2]}] ;# MGTHRXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC C5  } [get_ports {sfp_rx_n[2]}] ;# MGTHRXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D4  } [get_ports {sfp_tx_p[2]}] ;# MGTHTXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D3  } [get_ports {sfp_tx_n[2]}] ;# MGTHTXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D8  } [get_ports {sfp_rx_p[3]}] ;# MGTHRXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D7  } [get_ports {sfp_rx_n[3]}] ;# MGTHRXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC E2  } [get_ports {sfp_tx_p[3]}] ;# MGTHTXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC E1  } [get_ports {sfp_tx_n[3]}] ;# MGTHTXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC E10 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_118 from IC20.28
+set_property -dict {LOC E9  } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_118 from IC20.29
+#set_property -dict {LOC AW32 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to IC20.16
+#set_property -dict {LOC AW33 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to IC20.17
+
+set_property -dict {LOC BA29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
+set_property -dict {LOC AM29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5324_int]
+
+set_property -dict {LOC N18  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[0]}]
+set_property -dict {LOC L19  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[1]}]
+set_property -dict {LOC J37  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[2]}]
+set_property -dict {LOC H36  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[3]}]
+set_property -dict {LOC N19  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}]
+set_property -dict {LOC P18  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}]
+set_property -dict {LOC P20  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}]
+set_property -dict {LOC N20  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}]
+set_property -dict {LOC F39  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][0]}]
+set_property -dict {LOC G36  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][1]}]
+set_property -dict {LOC H38  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][0]}]
+set_property -dict {LOC G38  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][1]}]
+set_property -dict {LOC L17  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[0]}]
+set_property -dict {LOC L20  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[1]}]
+set_property -dict {LOC G37  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[2]}]
+set_property -dict {LOC J36  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[3]}]
+set_property -dict {LOC M18  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
+set_property -dict {LOC B31  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
+set_property -dict {LOC J38  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[2]}]
+set_property -dict {LOC L21  IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[3]}]
+set_property -dict {LOC M19  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[0]}]
+set_property -dict {LOC C26  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[1]}]
+set_property -dict {LOC E39  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[2]}]
+set_property -dict {LOC J26  IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[3]}]
+
+# 156.25 MHz MGT reference clock
+create_clock -period 6.4 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+set_false_path -to [get_ports {si5324_rst}]
+set_output_delay 0 [get_ports {si5324_rst}]
+set_false_path -from [get_ports {si5324_int}]
+set_input_delay 0 [get_ports {si5324_int}]
+
+set_false_path -from [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
+set_input_delay 0 [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
+set_false_path -to [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
+set_output_delay 0 [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
+
+# PCIe Interface
+#set_property -dict {LOC Y4   } [get_ports {pcie_rx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC Y3   } [get_ports {pcie_rx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC W2   } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC W1   } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AA6  } [get_ports {pcie_rx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AA5  } [get_ports {pcie_rx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AA2  } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AA1  } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AB4  } [get_ports {pcie_rx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AB3  } [get_ports {pcie_rx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AC2  } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AC1  } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AC6  } [get_ports {pcie_rx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AC5  } [get_ports {pcie_rx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AE2  } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AE1  } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
+#set_property -dict {LOC AD4  } [get_ports {pcie_rx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AD3  } [get_ports {pcie_rx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AG2  } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AG1  } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AE6  } [get_ports {pcie_rx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AE5  } [get_ports {pcie_rx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AH4  } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AH3  } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AF4  } [get_ports {pcie_rx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AF3  } [get_ports {pcie_rx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AJ2  } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AJ1  } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AG6  } [get_ports {pcie_rx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AG5  } [get_ports {pcie_rx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AK4  } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AK3  } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
+#set_property -dict {LOC AB8  } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK1P_115
+#set_property -dict {LOC AB7  } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK1N_115
+#set_property -dict {LOC AY35 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
+
+#set_false_path -from [get_ports {pcie_reset_n}]
+#set_input_delay 0 [get_ports {pcie_reset_n}]

src/eth/example/NetFPGA_SUME/fpga/fpga/Makefile

@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7vx690tffg1761-3
+FPGA_TOP = fpga
+FPGA_ARCH = virtex7
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/si5324_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+
+# Configuration
+#CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/NetFPGA_SUME/fpga/lib/taxi

@@ -0,0 +1 @@
+../../../../../../