#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""

Copyright (c) 2021-2026 FPGA Ninja, LLC

Authors:
- Alex Forencich

"""

import itertools
import logging
import os
import sys

import pytest
import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.utils import get_time_from_sim_steps
from cocotb.regression import TestFactory

from cocotbext.eth import GmiiFrame, PtpClockSimTime
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame

try:
    from basex import BaseXSerdesSource, BaseXSerdesSink
    from ptp_td import PtpTdSource
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from basex import BaseXSerdesSource, BaseXSerdesSink
        from ptp_td import PtpTdSource
    finally:
        del sys.path[0]


class TB:
    def __init__(self, dut, gbx_cfg=None):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        if len(dut.serdes_tx_data) == 16:
            if gbx_cfg:
                self.clk_period = 16
            else:
                self.clk_period = 16
        else:
            if gbx_cfg:
                self.clk_period = 8
            else:
                self.clk_period = 8

        cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
        cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())

        self.serdes_source = BaseXSerdesSource(
            data=dut.serdes_rx_data,
            data_k=dut.serdes_rx_data_k,
            data_valid=dut.serdes_rx_data_valid,
            clock=dut.rx_clk,
            enc_8b10b=False,
            gbx_cfg=gbx_cfg
        )
        self.serdes_sink = BaseXSerdesSink(
            data=dut.serdes_tx_data,
            data_k=dut.serdes_tx_data_k,
            data_valid=dut.serdes_tx_data_valid,
            gbx_req_sync=dut.serdes_tx_gbx_req_sync,
            gbx_req_stall=dut.serdes_tx_gbx_req_stall,
            gbx_sync=dut.serdes_tx_gbx_sync,
            clock=dut.tx_clk,
            dec_8b10b=False,
            gbx_cfg=gbx_cfg
        )

        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)

        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)

        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts_in, clock=dut.logic_clk)
        dut.ptp_ts_step_in.setimmediatevalue(0)

        self.ptp_clk_period = self.clk_period

        cocotb.start_soon(Clock(dut.ptp_clk, self.ptp_clk_period, units="ns").start())
        cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())

        self.ptp_td_source = PtpTdSource(
            data=dut.ptp_td_sdi,
            clock=dut.ptp_clk,
            reset=dut.ptp_rst,
            period_ns=self.ptp_clk_period
        )

        dut.an_en.setimmediatevalue(0)
        dut.an_restart.setimmediatevalue(0)
        dut.an_speedup.setimmediatevalue(1)
        dut.an_timeout_en.setimmediatevalue(1)
        dut.an_sgmii_en.setimmediatevalue(0)
        dut.an_sgmii_auto.setimmediatevalue(1)
        dut.an_adv_ability_basex.setimmediatevalue(0x0020)
        dut.an_adv_ability_sgmii.setimmediatevalue(0x0001)

        dut.cfg_tx_pad_en.setimmediatevalue(0)
        dut.cfg_tx_min_pkt_len.setimmediatevalue(0)
        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
        dut.cfg_tx_ifg.setimmediatevalue(0)
        dut.cfg_tx_enable.setimmediatevalue(0)
        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
        dut.cfg_rx_enable.setimmediatevalue(0)
        dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
        dut.cfg_rx_prbs31_enable.setimmediatevalue(0)

    async def reset(self):
        self.dut.logic_rst.setimmediatevalue(0)
        self.dut.rx_rst.setimmediatevalue(0)
        self.dut.tx_rst.setimmediatevalue(0)
        self.dut.ptp_rst.setimmediatevalue(0)
        self.dut.stat_rst.setimmediatevalue(0)
        await RisingEdge(self.dut.logic_clk)
        await RisingEdge(self.dut.logic_clk)
        self.dut.logic_rst.value = 1
        self.dut.rx_rst.value = 1
        self.dut.tx_rst.value = 1
        self.dut.ptp_rst.value = 1
        self.dut.stat_rst.value = 1
        await RisingEdge(self.dut.logic_clk)
        await RisingEdge(self.dut.logic_clk)
        self.dut.logic_rst.value = 0
        self.dut.rx_rst.value = 0
        self.dut.tx_rst.value = 0
        self.dut.ptp_rst.value = 0
        self.dut.stat_rst.value = 0
        await RisingEdge(self.dut.logic_clk)
        await RisingEdge(self.dut.logic_clk)

        self.ptp_td_source.set_ts_tod_sim_time()
        self.ptp_td_source.set_ts_rel_sim_time()


async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):

    if len(dut.serdes_tx_data) == 64:
        pipe_delay = int(dut.RX_SERDES_PIPELINE.value) + 1 + 1
    else:
        pipe_delay = int(dut.RX_SERDES_PIPELINE.value) + 1 + 1

    tb = TB(dut, gbx_cfg)

    tb.serdes_source.ifg = ifg
    tb.dut.cfg_tx_ifg.value = ifg
    tb.dut.cfg_rx_max_pkt_len.value = 9218-1
    tb.dut.cfg_rx_enable.value = 1

    await tb.reset()

    tb.log.info("Wait for block lock")
    while not int(dut.rx_block_lock.value):
        await RisingEdge(dut.rx_clk)

    tb.log.info("Wait for PTP CDC lock")
    while not int(dut.rx_ptp_locked.value):
        await RisingEdge(dut.rx_clk)
    for k in range(2000):
        await RisingEdge(dut.rx_clk)

    # clear out sink buffer
    tb.axis_sink.clear()

    test_frames = [payload_data(x) for x in payload_lengths()]
    tx_frames = []

    for test_data in test_frames:
        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
        await tb.serdes_source.send(test_frame)

    for test_data in test_frames:
        rx_frame = await tb.axis_sink.recv()
        tx_frame = tx_frames.pop(0)

        frame_error = rx_frame.tuser & 1
        ptp_ts = rx_frame.tuser >> 1
        ptp_ts_ns = ptp_ts / 2**16

        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")

        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))

        assert rx_frame.tdata == test_data
        assert frame_error == 0
        if gbx_cfg is None:
            if dut.PTP_TD_EN.value:
                assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
            else:
                assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < tb.clk_period*2

    assert tb.axis_sink.empty()

    for k in range(10):
        await RisingEdge(dut.logic_clk)


async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):

    if len(dut.serdes_tx_data) == 16:
        pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 0 + 1
    else:
        pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 0 + 1

    tb = TB(dut, gbx_cfg)

    tb.serdes_source.ifg = ifg
    tb.dut.cfg_tx_pad_en.value = 1
    tb.dut.cfg_tx_min_pkt_len.value = 60-1
    tb.dut.cfg_tx_max_pkt_len.value = 9218-1
    tb.dut.cfg_tx_ifg.value = ifg

    await tb.reset()

    tb.log.info("Wait for PTP CDC lock")
    while not int(dut.tx_ptp_locked.value):
        await RisingEdge(dut.tx_clk)
    for k in range(2000):
        await RisingEdge(dut.tx_clk)

    tb.dut.cfg_tx_enable.value = 1
    tb.serdes_sink.clear()

    test_frames = [payload_data(x) for x in payload_lengths()]

    for test_data in test_frames:
        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))

    for test_data in test_frames:
        rx_frame = await tb.serdes_sink.recv()
        tx_cpl = await tb.tx_cpl_sink.recv()

        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16

        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")

        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))

        assert rx_frame.get_payload() == test_data
        assert rx_frame.check_fcs()
        assert rx_frame.error is None
        if gbx_cfg is None:
            if dut.PTP_TD_EN.value:
                assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
            else:
                assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < tb.clk_period*2

    assert tb.serdes_sink.empty()

    for k in range(10):
        await RisingEdge(dut.logic_clk)


async def run_basex_an(tb, cfg, sgmii=False):
    # link timer scaled by 1000x for faster simulation
    link_timer = Timer(10, 'us')

    if sgmii:
        link_timer = Timer(1.6, 'us')

    dut = tb.dut

    for k in range(10):
        tb.log.info("AN_RESTART")
        tb.serdes_source.set_an_cfg(0x0000)

        await link_timer

        tb.log.info("ABILITY_DETECT")
        tb.serdes_source.set_an_cfg(cfg & ~0x4000)
        tb.serdes_sink.get_an_cfg()

        lp_cfg = None
        while True:
            await RisingEdge(dut.tx_clk)
            lp_cfg = tb.serdes_sink.get_an_cfg()
            if tb.serdes_sink.get_an_ability_match() and lp_cfg is not None and lp_cfg != 0:
                break

        tb.log.info("ACKNOWLEDGE_DETECT")
        tb.serdes_source.set_an_cfg(cfg | 0x4000)
        tb.serdes_sink.get_an_cfg()

        lp_cfg_ack = None
        while True:
            await RisingEdge(dut.tx_clk)
            lp_cfg_ack = tb.serdes_sink.get_an_cfg()
            if tb.serdes_sink.get_an_ack_match() and lp_cfg_ack is not None:
                break
            elif tb.serdes_sink.get_an_ability_match() and lp_cfg_ack is not None and lp_cfg_ack == 0:
                break

        if lp_cfg | 0x4000 != lp_cfg_ack:
            tb.log.warning("AN inconsistent, restarting (0x%04x != 0x%04x)", lp_cfg | 0x4000, lp_cfg_ack)
            continue

        if lp_cfg_ack == 0:
            tb.log.warning("AN restart requested")
            continue

        tb.log.info("COMPLETE_ACKNOWLEDGE")
        await link_timer

        tb.log.info("IDLE_DETECT")
        tb.serdes_source.set_an_cfg(None)

        await link_timer

        while True:
            await RisingEdge(dut.tx_clk)
            lp_cfg_ack2 = tb.serdes_sink.get_an_cfg()
            if tb.serdes_sink.get_an_idle_match():
                break
            elif tb.serdes_sink.get_an_ability_match() and lp_cfg_ack2 is not None and (lp_cfg_ack2 == 0 or lp_cfg_ack != lp_cfg_ack2):
                break

        if lp_cfg_ack2 is not None and lp_cfg_ack != lp_cfg_ack2:
            tb.log.warning("AN inconsistent, restarting (0x%04x != 0x%04x)", lp_cfg_ack, lp_cfg_ack2)
            continue

        if lp_cfg_ack2 == 0:
            tb.log.warning("AN restart requested")
            continue

        tb.log.info("AN done")
        return lp_cfg_ack

    tb.log.warning("AN timed out")
    tb.serdes_source.set_an_cfg(None)
    return None


async def run_test_an(dut, gbx_cfg=None, sgmii_en=False, sgmii_auto=False):

    tb = TB(dut, gbx_cfg)

    dut.an_en.value = 1
    dut.an_restart.value = 0
    dut.an_speedup.value = 1
    dut.an_timeout_en.value = 1
    dut.an_sgmii_en.value = sgmii_en
    dut.an_sgmii_auto.value = sgmii_auto
    dut.an_adv_ability_basex.value = 0x0020
    dut.an_adv_ability_sgmii.value = 0x0001

    await tb.reset()

    for k in range(100):
        await RisingEdge(dut.tx_clk)

    tb.log.info("Link partner is 1000BASE-X")

    if not sgmii_en:
        for x in range(16):
            cfg1 = 0x000A | ((x & 3) << 5) | ((x & 3) << 7) | ((x & 3) << 12)
            cfg2 = 0x000C | (((x >> 2) & 3) << 5) | (((x >> 2) & 3) << 7) | (((x >> 2) & 3) << 12)
            dut.an_adv_ability_basex.value = cfg2

            lp_cfg = await run_basex_an(tb, cfg1, False)

            for k in range(2000):
                if not dut.an_running.value:
                    break
                await RisingEdge(dut.tx_clk)

            assert lp_cfg == cfg2 | 0x4000
            assert not int(dut.an_running.value)
            assert int(dut.an_complete.value)
            assert not int(dut.an_timeout.value)
            assert not int(dut.an_sgmii_mode.value)
            assert int(dut.an_lp_adv_ability.value) == cfg1 | 0x4000
            assert int(dut.an_lp_remote_fault.value) == (cfg1 >> 12) & 0x3
            assert bool(dut.an_res_full_duplex.value) == ((((cfg1 & cfg2) >> 5) & 0x3) != 0x2)
            if ((cfg1 & cfg2) >> 7) & 0x1 == 0x1:
                # both ends support symmetric pause
                assert bool(dut.an_res_tx_pause.value)
                assert bool(dut.an_res_rx_pause.value)
            elif ((cfg1 >> 7) & 3) == 2 and ((cfg2 >> 7) & 3) == 3:
                # asymmetric towards local
                assert not bool(dut.an_res_tx_pause.value)
                assert bool(dut.an_res_rx_pause.value)
            elif ((cfg1 >> 7) & 3) == 3 and ((cfg2 >> 7) & 3) == 2:
                # asymmetric towards partner
                assert bool(dut.an_res_tx_pause.value)
                assert not bool(dut.an_res_rx_pause.value)
            else:
                assert not bool(dut.an_res_tx_pause.value)
                assert not bool(dut.an_res_rx_pause.value)
    else:
        lp_cfg = await run_basex_an(tb, 0x002A, False)

        for k in range(2000):
            if not dut.an_running.value:
                break
            await RisingEdge(dut.tx_clk)

        assert lp_cfg is None

    for k in range(100):
        await RisingEdge(dut.tx_clk)

    tb.log.info("Link partner is SGMII")

    if sgmii_en or sgmii_auto:
        for x in range(4):
            cfg1 = 0x0001 | (x << 10) | ((x & 1) << 12) | ((x & 2) << 14)
            cfg2 = cfg1
            dut.an_adv_ability_sgmii.value = cfg2

            lp_cfg = await run_basex_an(tb, cfg1, True)

            for k in range(2000):
                if not dut.an_running.value:
                    break
                await RisingEdge(dut.tx_clk)

            assert lp_cfg == cfg2 | 0x4000
            assert not int(dut.an_running.value)
            assert int(dut.an_complete.value)
            assert not int(dut.an_timeout.value)
            assert int(dut.an_sgmii_mode.value)
            assert int(dut.an_lp_adv_ability.value) == cfg1 | 0x4000
            assert bool(dut.an_lp_sgmii_link.value) == bool((cfg1 >> 15) & 1)
            assert int(dut.an_lp_sgmii_speed.value) == (cfg1 >> 10) & 0x3
            assert bool(dut.an_res_full_duplex.value) == bool((cfg1 >> 12) & 1)
    else:
        lp_cfg = await run_basex_an(tb, 0x9801, True)

        for k in range(2000):
            if not dut.an_running.value:
                break
            await RisingEdge(dut.tx_clk)

        assert lp_cfg is None

    for k in range(10):
        await RisingEdge(dut.tx_clk)


def size_list():
    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10


def incrementing_payload(length):
    return bytearray(itertools.islice(itertools.cycle(range(256)), length))


def cycle_en():
    return itertools.cycle([0, 0, 0, 1])


if getattr(cocotb, 'top', None) is not None:

    gbx_cfgs = [None]

    if cocotb.top.RX_GBX_IF_EN.value:
        gbx_cfgs.append((5, [4]))

    for test in [run_test_rx, run_test_tx]:

        factory = TestFactory(test)
        factory.add_option("payload_lengths", [size_list])
        factory.add_option("payload_data", [incrementing_payload])
        factory.add_option("ifg", [12, 0])
        factory.add_option("gbx_cfg", gbx_cfgs)
        factory.generate_tests()

    if cocotb.top.AN_EN.value:
        for test in [run_test_an]:
            factory = TestFactory(test)
            factory.add_option("gbx_cfg", gbx_cfgs)
            factory.add_option(("sgmii_en", "sgmii_auto"),
                [(False, False), (True, False), (False, True)])
            factory.generate_tests()


# cocotb-test

tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))


def process_f_files(files):
    lst = {}
    for f in files:
        if f[-2:].lower() == '.f':
            with open(f, 'r') as fp:
                l = fp.read().split()
            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
                lst[os.path.basename(f)] = f
        else:
            lst[os.path.basename(f)] = f
    return list(lst.values())


@pytest.mark.parametrize("dic_en", [1, 0])
@pytest.mark.parametrize("gbx_en", [1, 0])
@pytest.mark.parametrize("data_w", [8, 16])
def test_taxi_eth_mac_phy_1g_basex_fifo(request, data_w, gbx_en, dic_en):
    dut = "taxi_eth_mac_phy_1g_basex_fifo"
    module = os.path.splitext(os.path.basename(__file__))[0]
    toplevel = module

    verilog_sources = [
        os.path.join(tests_dir, f"{toplevel}.sv"),
        os.path.join(rtl_dir, f"{dut}.f"),
    ]

    verilog_sources = process_f_files(verilog_sources)

    parameters = {}

    parameters['DATA_W'] = data_w
    parameters['TX_GBX_IF_EN'] = gbx_en
    parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
    parameters['AXIS_DATA_W'] = parameters['DATA_W']
    parameters['SGMII_EN'] = 1
    parameters['AN_EN'] = parameters['SGMII_EN']
    parameters['DIC_EN'] = dic_en
    parameters['PTP_TS_EN'] = 1
    parameters['PTP_TD_EN'] = parameters['PTP_TS_EN']
    parameters['PTP_TS_FMT_TOD'] = 1
    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
    parameters['PTP_TD_SDI_PIPELINE'] = 2
    parameters['TX_TAG_W'] = 16
    parameters['BIT_REVERSE'] = 0
    parameters['ENC_8B10B_EN'] = 0
    parameters['DEC_8B10B_EN'] = parameters['ENC_8B10B_EN']
    parameters['PRBS31_EN'] = 1
    parameters['TX_SERDES_PIPELINE'] = 2
    parameters['RX_SERDES_PIPELINE'] = 2
    parameters['STAT_EN'] = 1
    parameters['STAT_TX_LEVEL'] = 2
    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
    parameters['STAT_ID_BASE'] = 0
    parameters['STAT_UPDATE_PERIOD'] = 1024
    parameters['STAT_STR_EN'] = 1
    parameters['STAT_PREFIX_STR'] = "\"MAC\""
    parameters['TX_FIFO_DEPTH'] = 16384
    parameters['TX_FIFO_RAM_PIPELINE'] = 1
    parameters['TX_FRAME_FIFO'] = 1
    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
    parameters['TX_DROP_WHEN_FULL'] = 0
    parameters['TX_CPL_FIFO_DEPTH'] = 64
    parameters['RX_FIFO_DEPTH'] = 16384
    parameters['RX_FIFO_RAM_PIPELINE'] = 1
    parameters['RX_FRAME_FIFO'] = 1
    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']

    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

    sim_build = os.path.join(tests_dir, "sim_build",
        request.node.name.replace('[', '-').replace(']', ''))

    cocotb_test.simulator.run(
        simulator="verilator",
        python_search=[tests_dir],
        verilog_sources=verilog_sources,
        toplevel=toplevel,
        module=module,
        parameters=parameters,
        sim_build=sim_build,
        extra_env=extra_env,
    )
