/* SPDX-License-Identifier: GPL */
/*

Copyright (c) 2026 FPGA Ninja, LLC

Authors:
- Alex Forencich

*/

#ifndef FPGA_ID_H
#define FPGA_ID_H

#define FPGA_ID_MASK_FULL   0xFFFFFFFF
#define FPGA_ID_MASK_VER    0xF0000000
#define FPGA_ID_MASK_PART   0x0FFFF000
#define FPGA_ID_MASK_MFR    0x00000FFE
#define FPGA_ID_MASK_NOVER  0x0FFFFFFF

// Xilinx
// Spartan 7
#define FPGA_ID_XC7S6       0x3622093
#define FPGA_ID_XC7S15      0x3620093
#define FPGA_ID_XC7S25      0x37C4093
#define FPGA_ID_XC7S50      0x362F093
#define FPGA_ID_XC7S75      0x37C8093
#define FPGA_ID_XC7S100     0x37C7093
// Artix 7
#define FPGA_ID_XC7A15T     0x362D093
#define FPGA_ID_XC7A35T     0x362D093
#define FPGA_ID_XC7A50T     0x362C093
#define FPGA_ID_XC7A75T     0x3632093
#define FPGA_ID_XC7A100T    0x3631093
#define FPGA_ID_XC7A200T    0x3636093
// Kintex 7
#define FPGA_ID_XC7K70T     0x3647093
#define FPGA_ID_XC7K160T    0x364C093
#define FPGA_ID_XC7K325T    0x3651093
#define FPGA_ID_XC7K355T    0x3747093
#define FPGA_ID_XC7K410T    0x3656093
#define FPGA_ID_XC7K420T    0x3752093
#define FPGA_ID_XC7K480T    0x3751093
// Virtex 7
#define FPGA_ID_XC7V585T    0x3671093
#define FPGA_ID_XC7V2000T   0x36B3093
#define FPGA_ID_XC7VX330T   0x3667093
#define FPGA_ID_XC7VX415T   0x3682093
#define FPGA_ID_XC7VX485T   0x3687093
#define FPGA_ID_XC7VX550T   0x3692093
#define FPGA_ID_XC7VX690T   0x3691093
#define FPGA_ID_XC7VX980T   0x3696093
#define FPGA_ID_XC7VX1140T  0x36D5093
#define FPGA_ID_XC7VH580T   0x36D9093
#define FPGA_ID_XC7VH870T   0x36DB093
// Zynq 7000
#define FPGA_ID_XC7Z007     0x3723093
#define FPGA_ID_XC7Z010     0x3722093
#define FPGA_ID_XC7Z012     0x373C093
#define FPGA_ID_XC7Z014     0x3728093
#define FPGA_ID_XC7Z015     0x373B093
#define FPGA_ID_XC7Z020     0x3727093
#define FPGA_ID_XC7Z030     0x372C093
#define FPGA_ID_XC7Z035     0x3732093
#define FPGA_ID_XC7Z045     0x3731093
#define FPGA_ID_XC7Z100     0x3736093
// Kintex UltraScale
#define FPGA_ID_XCKU025     0x3824093
#define FPGA_ID_XCKU035     0x3823093
#define FPGA_ID_XCKU040     0x3822093
#define FPGA_ID_XCKU060     0x3919093
#define FPGA_ID_XCKU085     0x380F093
#define FPGA_ID_XCKU095     0x3844093
#define FPGA_ID_XCKU115     0x390D093
// Virtex UltraScale
#define FPGA_ID_XCVU065     0x3939093
#define FPGA_ID_XCVU080     0x3843093
#define FPGA_ID_XCVU095     0x3842093
#define FPGA_ID_XCVU125     0x392D093
#define FPGA_ID_XCVU160     0x3933093
#define FPGA_ID_XCVU190     0x3931093
#define FPGA_ID_XCVU440     0x396D093
// Artix UltraScale+
#define FPGA_ID_XCAU10P     0x4AC5093
#define FPGA_ID_XCAU15P     0x4AC4093
#define FPGA_ID_XCAU20P     0x4A65093
#define FPGA_ID_XCAU25P     0x4A64093
// Kintex UltraScale+
#define FPGA_ID_XCKU3P      0x4A63093
#define FPGA_ID_XCKU5P      0x4A62093
#define FPGA_ID_XCKU9P      0x484A093
#define FPGA_ID_XCKU11P     0x4A4E093
#define FPGA_ID_XCKU13P     0x4A52093
#define FPGA_ID_XCKU15P     0x4A56093
#define FPGA_ID_XCKU19P     0x4ACF093
// Virtex UltraScale+
#define FPGA_ID_XCVU3P      0x4B39093
#define FPGA_ID_XCVU5P      0x4B2B093
#define FPGA_ID_XCVU7P      0x4B29093
#define FPGA_ID_XCVU9P      0x4B31093
#define FPGA_ID_XCVU11P     0x4B49093
#define FPGA_ID_XCVU13P     0x4B51093
#define FPGA_ID_XCVU19P     0x4BA1093
#define FPGA_ID_XCVU23P     0x4ACE093
#define FPGA_ID_XCVU27P     0x4B43093
#define FPGA_ID_XCVU29P     0x4B41093
#define FPGA_ID_XCVU31P     0x4B6B093
#define FPGA_ID_XCVU33P     0x4B69093
#define FPGA_ID_XCVU35P     0x4B71093
#define FPGA_ID_XCVU37P     0x4B79093
#define FPGA_ID_XCVU45P     0x4B73093
#define FPGA_ID_XCVU47P     0x4B7B093
#define FPGA_ID_XCVU57P     0x4B61093
// Zynq UltraScale+
#define FPGA_ID_XCZU1       0x4688093
#define FPGA_ID_XCZU2       0x4711093
#define FPGA_ID_XCZU3       0x4710093
#define FPGA_ID_XCZU4       0x4721093
#define FPGA_ID_XCZU5       0x4720093
#define FPGA_ID_XCZU6       0x4739093
#define FPGA_ID_XCZU7       0x4730093
#define FPGA_ID_XCZU9       0x4738093
#define FPGA_ID_XCZU11      0x4740093
#define FPGA_ID_XCZU15      0x4750093
#define FPGA_ID_XCZU17      0x4759093
#define FPGA_ID_XCZU19      0x4758093
#define FPGA_ID_XCZU21      0x47E1093
#define FPGA_ID_XCZU25      0x47E5093
#define FPGA_ID_XCZU27      0x47E4093
#define FPGA_ID_XCZU28      0x47E0093
#define FPGA_ID_XCZU29      0x47E2093
#define FPGA_ID_XCZU39      0x47E6093
#define FPGA_ID_XCZU43      0x47FD093
#define FPGA_ID_XCZU46      0x47F8093
#define FPGA_ID_XCZU47      0x47FF093
#define FPGA_ID_XCZU48      0x47FB093
#define FPGA_ID_XCZU49      0x47FE093
#define FPGA_ID_XCZU65      0x46D1093
#define FPGA_ID_XCZU67      0x46D0093
// Kria SoM (Zynq UltraScale+)
#define FPGA_ID_XCK26       0x4A49093
// Alveo (Virtex UltraScale+)
#define FPGA_ID_XCU26_XCUX35   0x4AD5093
#define FPGA_ID_XCU50_XCU55N   0x4B77093
#define FPGA_ID_XCU200         0x4B37093
#define FPGA_ID_XCU250         0x4B57093
#define FPGA_ID_XCU280_XCU55C  0x4B7D093
// Versal AI Edge
#define FPGA_ID_XCVE1752    0x4C9A093
#define FPGA_ID_XCVE2002    0x4CC1093
#define FPGA_ID_XCVE2102    0x4CC0093
#define FPGA_ID_XCVE2202    0x4CC9093
#define FPGA_ID_XCVE2302    0x4CC8093
#define FPGA_ID_XCVE2602    0x4CD3093
#define FPGA_ID_XCVE2802    0x4CD1093
// Versal AI Core
#define FPGA_ID_XCVC1352    0x4C93093
#define FPGA_ID_XCVC1502    0x4C9B093
#define FPGA_ID_XCVC1702    0x4C98093
#define FPGA_ID_XCVC1802    0x4CA9093
#define FPGA_ID_XCVC1902    0x4CA8093
#define FPGA_ID_XCVC2602    0x4CD2093
#define FPGA_ID_XCVC2802    0x4CD0093
// Versal Prime
#define FPGA_ID_XCVM1102    0x4CCA093
#define FPGA_ID_XCVM1302    0x4C09093
#define FPGA_ID_XCVM1402    0x4C08093
#define FPGA_ID_XCVM1502    0x4C99093
#define FPGA_ID_XCVM1802    0x4CAA093
#define FPGA_ID_XCVM2202    0x4CD4093
#define FPGA_ID_XCVM2302    0x4C24093
#define FPGA_ID_XCVM2502    0x4D01093
#define FPGA_ID_XCVM2902    0x4C23093
// Versal Premium
#define FPGA_ID_XCVP1002    0x4C1B093
#define FPGA_ID_XCVP1052    0x4C18093
#define FPGA_ID_XCVP1102    0x4C22093
#define FPGA_ID_XCVP1202    0x4D00093
#define FPGA_ID_XCVP1402    0x4C20093
#define FPGA_ID_XCVP1502    0x4D08093
#define FPGA_ID_XCVP1552    0x4D34093
#define FPGA_ID_XCVP1702    0x4D10093
#define FPGA_ID_XCVP1802    0x4D14093
#define FPGA_ID_XCVP2502    0x4D1C093
#define FPGA_ID_XCVP2802    0x4D20093

// Intel
// Stratix 10
#define FPGA_ID_1SG10MH_U1  0x032270DD
#define FPGA_ID_1SG10MH_U2  0x0322F0DD
#define FPGA_ID_1SG040H     0x032200DD
#define FPGA_ID_1SG040H_NL  0x032A00DD
#define FPGA_ID_1SG065H     0x032210DD
#define FPGA_ID_1SG065H_NL  0x032A10DD
#define FPGA_ID_1SG085H     0x132220DD
#define FPGA_ID_1SG110H     0x032220DD
#define FPGA_ID_1SG110H_NL  0x032A20DD
#define FPGA_ID_1SG165H     0xF32250DD
#define FPGA_ID_1SG166H     0x532240DD
#define FPGA_ID_1SG166H_NL  0x5322C0DD
#define FPGA_ID_1SG210H     0xE32250DD
#define FPGA_ID_1SG210H_ES1 0x232250DD
#define FPGA_ID_1SG211H     0x432240DD
#define FPGA_ID_1SG250L     0xD32150DD
#define FPGA_ID_1SG250H     0xD32250DD
#define FPGA_ID_1SG280L     0xC32150DD
#define FPGA_ID_1SG280L_NL  0xC32950DD
#define FPGA_ID_1SG280L_ES1 0x032150DD
#define FPGA_ID_1SG280L_ES2 0x032250DD
#define FPGA_ID_1SG280L_ES3 0xC32150DD
#define FPGA_ID_1SG280H     0xC32250DD
#define FPGA_ID_1SG280H_NL  0xC32A50DD
#define FPGA_ID_1SG280H_ES1 0x032250DD
#define FPGA_ID_1SG280H_ES2 0xC32150DD
#define FPGA_ID_1SG280H_ES3 0xC32250DD
#define FPGA_ID_1SX040H     0x032280DD
#define FPGA_ID_1SX065H     0x032290DD
#define FPGA_ID_1SX085H     0x1322A0DD
#define FPGA_ID_1SX110H     0x0322A0DD
#define FPGA_ID_1SX165H     0xF322D0DD
#define FPGA_ID_1SX210H     0xE322D0DD
#define FPGA_ID_1SX250L     0xD321D0DD
#define FPGA_ID_1SX250H     0xD322D0DD
#define FPGA_ID_1SX280L     0xC321D0DD
#define FPGA_ID_1SX280L_ES1 0x4321D0DD
#define FPGA_ID_1SX280L_ES2 0x4321D0DD
#define FPGA_ID_1SX280H     0xC322D0DD
#define FPGA_ID_1SX280H_ES1 0x4322D0DD
#define FPGA_ID_1SX280H_ES2 0xC322D0DD
#define FPGA_ID_1ST040E     0x032380DD
#define FPGA_ID_1ST040E_NL  0x032B00DD
#define FPGA_ID_1ST085E     0x1323A0DD
#define FPGA_ID_1ST110E     0x0323A0DD
#define FPGA_ID_1ST110E_NL  0x032B20DD
#define FPGA_ID_1ST165E     0x532340DD
#define FPGA_ID_1ST210E     0x432340DD
#define FPGA_ID_1ST210E_ES1 0x032340DD
#define FPGA_ID_1ST250E     0xD323D0DD
#define FPGA_ID_1ST280E     0xC323D0DD
#define FPGA_ID_1ST280E_ES1 0xC323D0DD
#define FPGA_ID_1SM16BE     0x732BC0DD
#define FPGA_ID_1SM16BE_ES1 0x732BC0DD
#define FPGA_ID_1SM16BH     0x732AC0DD
#define FPGA_ID_1SM16BH_ES1 0x332AC0DD
#define FPGA_ID_1SM16CH     0x532AC0DD
#define FPGA_ID_1SM16CH_ES1 0x132AC0DD
#define FPGA_ID_1SM21BE     0x632BC0DD
#define FPGA_ID_1SM21BE_ES1 0x632BC0DD
#define FPGA_ID_1SM21BH     0x632AC0DD
#define FPGA_ID_1SM21BH_ES1 0x232AC0DD
#define FPGA_ID_1SM21CH     0x432AC0DD
#define FPGA_ID_1SM21CH_ES1 0x032AC0DD
#define FPGA_ID_1SD110P     0x0324A0DD
#define FPGA_ID_1SD110P_NL  0x032C20DD
#define FPGA_ID_1SD21BP     0x632CC0DD
#define FPGA_ID_1SD280P     0xC32450DD
// Agilex
#define FPGA_ID_AGFA006R16A    0x134310DD
#define FPGA_ID_AGFA008R16A    0x034310DD
#define FPGA_ID_AGFA012R24A    0x534120DD
#define FPGA_ID_AGFA012R24B    0xD34120DD
#define FPGA_ID_AGFA014R24AR0  0x034120DD
#define FPGA_ID_AGFA014R24A    0x434120DD
#define FPGA_ID_AGFA014R24B    0xC34120DD
#define FPGA_ID_AGFA019R25A    0x134150DD
#define FPGA_ID_AGFA022R24C    0x134330DD
#define FPGA_ID_AGFA022R25A    0x134130DD
#define FPGA_ID_AGFA022R31C    0x134330DD
#define FPGA_ID_AGFA023R25AR0  0x034150DD
#define FPGA_ID_AGFA023R25A    0x034150DD
#define FPGA_ID_AGFA027R24CR0  0x034330DD
#define FPGA_ID_AGFA027R24CR2  0x034330DD
#define FPGA_ID_AGFA027R24C    0x034330DD
#define FPGA_ID_AGFA027R25AR0  0x034130DD
#define FPGA_ID_AGFA027R25A    0x034130DD
#define FPGA_ID_AGFA027R31C    0x034330DD
#define FPGA_ID_AGFB006R16A    0x134390DD
#define FPGA_ID_AGFB008R16A    0x034390DD
#define FPGA_ID_AGFB012R24A    0x5341A0DD
#define FPGA_ID_AGFB012R24B    0xD341A0DD
#define FPGA_ID_AGFB014R24AR0  0x0341A0DD
#define FPGA_ID_AGFB014R24A    0x4341A0DD
#define FPGA_ID_AGFB014R24B    0xC341A0DD
#define FPGA_ID_AGFB019R25A    0x1341D0DD
#define FPGA_ID_AGFB022R24C    0x1343B0DD
#define FPGA_ID_AGFB022R25A    0x1341B0DD
#define FPGA_ID_AGFB022R31C    0x1343B0DD
#define FPGA_ID_AGFB023R25AR0  0x0341D0DD
#define FPGA_ID_AGFB023R25A    0x0341D0DD
#define FPGA_ID_AGFB027R24CR0  0x0343B0DD
#define FPGA_ID_AGFB027R24CR2  0x0343B0DD
#define FPGA_ID_AGFB027R24C    0x0343B0DD
#define FPGA_ID_AGFB027R25AR0  0x0341B0DD
#define FPGA_ID_AGFB027R25A    0x0341B0DD
#define FPGA_ID_AGFB027R31C    0x0343B0DD
#define FPGA_ID_AGFC019R25A    0x334150DD
#define FPGA_ID_AGFC023R25AR0  0x234150DD
#define FPGA_ID_AGFC023R25A    0x234150DD
#define FPGA_ID_AGFD019R25A    0x3341D0DD
#define FPGA_ID_AGFD023R25AR0  0x2341D0DD
#define FPGA_ID_AGFD023R25A    0x2341D0DD
#define FPGA_ID_AGIB022R29A    0x134BB0DD
#define FPGA_ID_AGIB022R31B    0x1343B0DD
#define FPGA_ID_AGIB027R29AR0  0x034BB0DD
#define FPGA_ID_AGIB027R29AR1  0x034BB0DD
#define FPGA_ID_AGIB027R29AR3  0x034BB0DD
#define FPGA_ID_AGIB027R29A    0x034BB0DD
#define FPGA_ID_AGIB027R31BR0  0x0343B0DD
#define FPGA_ID_AGIB027R31B    0x0343B0DD

const char *get_fpga_part(int id);

#endif /* FPGA_ID_H */
