#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""

Copyright (c) 2023-2025 FPGA Ninja, LLC

Authors:
- Alex Forencich

"""

import itertools
import logging
import os
import random
import sys

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory

try:
    from dma_psdp_ram import PsdpRamMasterWrite, PsdpRamMasterRead, PsdpRamWriteBus, PsdpRamReadBus
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from dma_psdp_ram import PsdpRamMasterWrite, PsdpRamMasterRead, PsdpRamWriteBus, PsdpRamReadBus
    finally:
        del sys.path[0]


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk_wr, 10, units="ns").start())
        cocotb.start_soon(Clock(dut.clk_rd, 11, units="ns").start())

        # DMA RAM
        self.dma_ram_master_wr = PsdpRamMasterWrite(PsdpRamWriteBus.from_entity(dut.dma_ram), dut.clk_wr, dut.rst_wr)
        self.dma_ram_master_rd = PsdpRamMasterRead(PsdpRamReadBus.from_entity(dut.dma_ram), dut.clk_rd, dut.rst_rd)

    def set_idle_generator(self, generator=None):
        if generator:
            self.dma_ram_master_wr.set_pause_generator(generator())
            self.dma_ram_master_rd.set_pause_generator(generator())

    def set_backpressure_generator(self, generator=None):
        if generator:
            pass

    async def cycle_reset(self):
        self.dut.rst_wr.setimmediatevalue(0)
        self.dut.rst_rd.setimmediatevalue(0)
        await RisingEdge(self.dut.clk_wr)
        await RisingEdge(self.dut.clk_wr)
        self.dut.rst_wr.value = 1
        self.dut.rst_rd.value = 1
        await RisingEdge(self.dut.clk_wr)
        await RisingEdge(self.dut.clk_wr)
        self.dut.rst_wr.value = 0
        self.dut.rst_rd.value = 0
        await RisingEdge(self.dut.clk_wr)
        await RisingEdge(self.dut.clk_wr)


async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):

    tb = TB(dut)

    byte_lanes = tb.dma_ram_master_wr.byte_lanes

    await tb.cycle_reset()

    tb.set_idle_generator(idle_inserter)
    tb.set_backpressure_generator(backpressure_inserter)

    for length in list(range(1, byte_lanes*2))+[1024]:
        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
            tb.log.info("length %d, offset %d", length, offset)
            addr = offset+0x1000
            test_data = bytearray([x % 256 for x in range(length)])

            await tb.dma_ram_master_wr.write(addr-4, b'\xaa'*(length+8))

            await tb.dma_ram_master_wr.write(addr, test_data)

            data = await tb.dma_ram_master_rd.read(addr-1, length+2)

            assert data.data == b'\xaa'+test_data+b'\xaa'

    await RisingEdge(dut.clk_wr)
    await RisingEdge(dut.clk_wr)


async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):

    tb = TB(dut)

    byte_lanes = tb.dma_ram_master_wr.byte_lanes

    await tb.cycle_reset()

    tb.set_idle_generator(idle_inserter)
    tb.set_backpressure_generator(backpressure_inserter)

    for length in list(range(1, byte_lanes*2))+[1024]:
        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
            tb.log.info("length %d, offset %d", length, offset)
            addr = offset+0x1000
            test_data = bytearray([x % 256 for x in range(length)])

            await tb.dma_ram_master_wr.write(addr, test_data)

            data = await tb.dma_ram_master_rd.read(addr, length)

            assert data.data == test_data

    await RisingEdge(dut.clk_wr)
    await RisingEdge(dut.clk_wr)


async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):

    tb = TB(dut)

    await tb.cycle_reset()

    tb.set_idle_generator(idle_inserter)
    tb.set_backpressure_generator(backpressure_inserter)

    async def worker(master_wr, master_rd, offset, aperture, count=16):
        for k in range(count):
            length = random.randint(1, min(512, aperture))
            addr = offset+random.randint(0, aperture-length)
            test_data = bytearray([x % 256 for x in range(length)])

            await Timer(random.randint(1, 100), 'ns')

            await master_wr.write(addr, test_data)

            await Timer(random.randint(1, 100), 'ns')

            data = await master_rd.read(addr, length)
            assert data.data == test_data

    workers = []

    for k in range(16):
        workers.append(cocotb.start_soon(worker(tb.dma_ram_master_wr, tb.dma_ram_master_rd, k*0x1000, 0x1000, count=16)))

    while workers:
        await workers.pop(0).join()

    await RisingEdge(dut.clk_wr)
    await RisingEdge(dut.clk_wr)


def cycle_pause():
    return itertools.cycle([1, 1, 1, 0])


if getattr(cocotb, 'top', None) is not None:

    for test in [run_test_write, run_test_read, run_stress_test]:

        factory = TestFactory(test)
        factory.add_option("idle_inserter", [None, cycle_pause])
        factory.add_option("backpressure_inserter", [None, cycle_pause])
        factory.generate_tests()


# cocotb-test

tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))


def process_f_files(files):
    lst = {}
    for f in files:
        if f[-2:].lower() == '.f':
            with open(f, 'r') as fp:
                l = fp.read().split()
            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
                lst[os.path.basename(f)] = f
        else:
            lst[os.path.basename(f)] = f
    return list(lst.values())


@pytest.mark.parametrize("seg_data_w", [32, 64])
@pytest.mark.parametrize("segs", [2, 4])
def test_taxi_dma_psdpram_async(request, seg_data_w, segs):
    dut = "taxi_dma_psdpram_async"
    module = os.path.splitext(os.path.basename(__file__))[0]
    toplevel = module

    verilog_sources = [
        os.path.join(tests_dir, f"{toplevel}.sv"),
        os.path.join(rtl_dir, f"{dut}.sv"),
        os.path.join(rtl_dir, "taxi_dma_ram_if.sv"),
    ]

    verilog_sources = process_f_files(verilog_sources)

    parameters = {}

    parameters['SIZE'] = 65536
    parameters['SEGS'] = segs
    parameters['SEG_DATA_W'] = seg_data_w
    parameters['SEG_BE_W'] = parameters['SEG_DATA_W'] // 8
    parameters['SEG_ADDR_W'] = (parameters['SIZE']//(parameters['SEGS']*parameters['SEG_BE_W'])-1).bit_length()
    parameters['PIPELINE'] = 2

    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

    sim_build = os.path.join(tests_dir, "sim_build",
        request.node.name.replace('[', '-').replace(']', ''))

    cocotb_test.simulator.run(
        simulator="verilator",
        python_search=[tests_dir],
        verilog_sources=verilog_sources,
        toplevel=toplevel,
        module=module,
        parameters=parameters,
        sim_build=sim_build,
        extra_env=extra_env,
    )
