# Configuration for LMK04208 PLL

# PLL1
# CLKin0 = 12.8 MHz TCXO
# CLKin1 = 10 MHz
# CLKin0 R = 800
# CLKin1 R = 625
# PFD = in0 / R0 = in1 / R1 = 16 kHz
# N1 = 7680
# VCO = PFD * N1 = 122.88 MHz
# Ext VCO is 122.88 MHz

# PLL2
# 122.88 MHz from ext VCO
# VCO range 2750 - 3072 MHz
# R2 = 384
# VCODIV = 3
# N2 P = 5
# N2 = 625
# PFD = 122.88 / R2 = 0.32
# VCO = PFD * VCODIV * P * N2 = 3000
# VCO/3/4 = 250 MHz
# VCO/3/100 = 10 MHz
# VCO/3/512 = 1.953125 MHz

# CLKout0: FPGA SYSREF
# CLKout1: DAC 228 SYSREF
# CLKout2: FPGA REFCLK
# CLKout3: SYNC_2594
# CLKout4: REFCLK_2594
# CLKout5: SMA

Data

# Reset
0x00020000
0x00000000

# CLKout0 DDLY 10, DIV 512
0x00284000
# CLKout1 DDLY 10, DIV 512
0x00284001
# CLKout2 DDLY 10, DIV 4
0x00280082
# CLKout3 DDLY 10, DIV 512
0x00284003
# CLKout4 DDLY 10, DIV 4
0x00280084
# CLKout5 DDLY 10, DIV 100
0x00280c85
# CLKout0 LVDS, CLKout1 LVDS
0x01100006
# CLKout2 LVDS, CLKout3 LVDS
0x01100007
# CLKout4 LVDS, CLKout5 LVCMOS
0x06010008
# RSVD
0x55555549
# OSCout off, VCO div 3
0x1000530a
# MODE 0, sync on, SYNC_TYPE input with pull-up, no xtal
0x0400200b
# LD_MUX PLL1&PLL2, SYNC_PLL2_DLD on, EN_TRACK on, holdover disable
0x1b8c016c
# HOLDOVER_MUX readback, DISABLE_DLD1_DET on, CLKin_SELECT_MODE CLKin0, EN_CLKin0
0x3b00802d
# LOS_TIMEOUT 1200 ns, CLKinX_BUF_TYPE Bipolar, DAC_HIGH_TRIP 63, DAC_LOW_TRIP 0
0x000fc00e
# MAN_DAC 0, EN_MAN_DAC auto
0x0000000f
# XTAL_LVL 1.65 Vpp
0x01550410
# PLL2_C4_LF 10pF, PLL2_C3_LF 10 pF, PLL2_R4_LF 200 ohm, PLL2_R3_LF 200 ohm, PLL1_N_DLY 0 ps, PLL1_R_DLY 0 ps, PLL1_WND_SIZE 5.5 ns
0x00000018
# DAC_CLK_DIV 1023, PLL1_DLD_CNT 16383
0xffcfffd9
# PLL2_WND_SIZE 2, EN_PLL2_REF_2X off, PLL2_CP_POL neg, PLL2_CP_GAIN 100, PLL2_DLD_CNT 16383, PLL2_CP_TRI off
0x83afffda
# PLL1_CP_POL pos, PLL1_CP_GAIN 100, CLKinX_PreR_DIV 1, PLL1_R 800, PLL1_CP_TRI off
0x1000c81b
# PLL2_R 384, PLL1_N 7680
0x1807801c
# OSCin_FREQ 63-127, PLL2_FAST_PDF under 100, PLL2_N_CAL 625
0x01004e3d
# PLL2_P 5, PLL2_N 625
0x05004e3e
# READBACK_LE 0
0x0000001f
