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Use logic instead of reg

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-07 02:14:19 -08:00
parent 5f814e7da8
commit 004246608e
25 changed files with 265 additions and 265 deletions
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12
src/eth/rtl/taxi_eth_mac_1g_gmii.sv
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@@ -197,8 +197,8 @@ module taxi_eth_mac_1g_gmii #
input wire logic cfg_rx_pfc_en = 1'b0
);
reg [1:0] link_speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
logic [1:0] link_speed_reg = 2'b10;
logic mii_select_reg = 1'b0;
wire tx_mii_select_sync;
@@ -225,7 +225,7 @@ rx_mii_select_sync_inst (
);
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
logic [2:0] rx_prescale = 3'd0;
always_ff @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
@@ -243,9 +243,9 @@ rx_prescale_sync_inst (
.out(rx_prescale_sync)
);
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
reg rx_prescale_sync_last_reg = 1'b0;
logic [6:0] rx_speed_count_1 = 0;
logic [1:0] rx_speed_count_2 = 0;
logic rx_prescale_sync_last_reg = 1'b0;
always_ff @(posedge gtx_clk) begin
rx_prescale_sync_last_reg <= rx_prescale_sync;

4
src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv
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@@ -183,8 +183,8 @@ end
wire [1:0] link_speed_int;
reg [1:0] link_speed_sync_reg_1 = 2'b10;
reg [1:0] link_speed_sync_reg_2 = 2'b10;
logic [1:0] link_speed_sync_reg_1 = 2'b10;
logic [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2;

12
src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
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@@ -196,8 +196,8 @@ module taxi_eth_mac_1g_rgmii #
input wire logic cfg_rx_pfc_en = 1'b0
);
reg [1:0] link_speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
logic [1:0] link_speed_reg = 2'b10;
logic mii_select_reg = 1'b0;
wire tx_mii_select_sync;
@@ -224,7 +224,7 @@ rx_mii_select_sync_inst (
);
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
logic [2:0] rx_prescale = 3'd0;
always_ff @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
@@ -242,9 +242,9 @@ rx_prescale_sync_inst (
.out(rx_prescale_sync)
);
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
reg rx_prescale_sync_last_reg = 1'b0;
logic [6:0] rx_speed_count_1 = 0;
logic [1:0] rx_speed_count_2 = 0;
logic rx_prescale_sync_last_reg = 1'b0;
always_ff @(posedge gtx_clk) begin
rx_prescale_sync_last_reg <= rx_prescale_sync;

4
src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
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@@ -182,8 +182,8 @@ end
wire [1:0] link_speed_int;
reg [1:0] link_speed_sync_reg_1 = 2'b10;
reg [1:0] link_speed_sync_reg_2 = 2'b10;
logic [1:0] link_speed_sync_reg_1 = 2'b10;
logic [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2;

16
src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
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@@ -154,10 +154,10 @@ wire rx_ptp_locked;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = '0;
reg [0:0] tx_sync_reg_2 = '0;
reg [0:0] tx_sync_reg_3 = '0;
reg [0:0] tx_sync_reg_4 = '0;
logic [0:0] tx_sync_reg_1 = '0;
logic [0:0] tx_sync_reg_2 = '0;
logic [0:0] tx_sync_reg_3 = '0;
logic [0:0] tx_sync_reg_4 = '0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
@@ -189,10 +189,10 @@ wire rx_block_lock_int;
wire rx_high_ber_int;
wire rx_status_int;
reg [6:0] rx_sync_reg_1 = '0;
reg [6:0] rx_sync_reg_2 = '0;
reg [6:0] rx_sync_reg_3 = '0;
reg [6:0] rx_sync_reg_4 = '0;
logic [6:0] rx_sync_reg_1 = '0;
logic [6:0] rx_sync_reg_2 = '0;
logic [6:0] rx_sync_reg_3 = '0;
logic [6:0] rx_sync_reg_4 = '0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];

10
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
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@@ -100,15 +100,15 @@ end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
logic [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin

34
src/eth/rtl/taxi_mac_ctrl_rx.sv
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@@ -317,26 +317,26 @@ always_ff @(posedge clk) begin
end
// output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0;
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0;
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
logic store_axis_int_to_output;
logic store_axis_int_to_temp;
logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;

34
src/eth/rtl/taxi_mac_ctrl_tx.sv
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@@ -290,26 +290,26 @@ always_ff @(posedge clk) begin
end
// output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0;
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0;
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
logic store_axis_int_to_output;
logic store_axis_int_to_temp;
logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;

4
src/eth/rtl/taxi_mii_phy_if.sv
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@@ -68,9 +68,9 @@ rx_ssio_sdr_inst (
);
(* IOB = "TRUE" *)
reg [3:0] phy_mii_txd_reg = 4'd0;
logic [3:0] phy_mii_txd_reg = 4'd0;
(* IOB = "TRUE" *)
reg phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
logic phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
assign phy_mii_txd = phy_mii_txd_reg;
assign phy_mii_tx_en = phy_mii_tx_en_reg;