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Use logic instead of reg

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-11-07 02:14:19 -08:00
parent 5f814e7da8
commit 004246608e
25 changed files with 265 additions and 265 deletions
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10
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
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@@ -100,15 +100,15 @@ end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
logic [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin