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Use logic instead of reg

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-07 02:14:19 -08:00
parent 5f814e7da8
commit 004246608e
25 changed files with 265 additions and 265 deletions
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54
src/axi/rtl/taxi_axi_fifo_rd.sv
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@@ -61,20 +61,20 @@ if (m_axi_rd.DATA_W != DATA_W)
if (m_axi_rd.STRB_W != STRB_W) if (m_axi_rd.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next; logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
reg [FIFO_AW:0] wr_addr_reg = '0; logic [FIFO_AW:0] wr_addr_reg = '0;
reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next; logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
reg [FIFO_AW:0] rd_addr_reg = '0; logic [FIFO_AW:0] rd_addr_reg = '0;
(* ramstyle = "no_rw_check" *) (* ramstyle = "no_rw_check" *)
reg [RWIDTH-1:0] mem[2**FIFO_AW]; logic [RWIDTH-1:0] mem[2**FIFO_AW];
reg [RWIDTH-1:0] mem_read_data_reg; logic [RWIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [RWIDTH-1:0] m_axi_r; wire [RWIDTH-1:0] m_axi_r;
reg [RWIDTH-1:0] s_axi_r_reg; logic [RWIDTH-1:0] s_axi_r_reg;
reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
// full when first MSB different but rest same // full when first MSB different but rest same
wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) && wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -83,9 +83,9 @@ wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
wire empty = wr_ptr_reg == rd_ptr_reg; wire empty = wr_ptr_reg == rd_ptr_reg;
// control signals // control signals
reg write; logic write;
reg read; logic read;
reg store_output; logic store_output;
assign m_axi_rd.rready = !full; assign m_axi_rd.rready = !full;
@@ -104,24 +104,24 @@ if (FIFO_DELAY) begin
STATE_IDLE = 1'd0, STATE_IDLE = 1'd0,
STATE_WAIT = 1'd1; STATE_WAIT = 1'd1;
reg [0:0] state_reg = STATE_IDLE, state_next; logic [0:0] state_reg = STATE_IDLE, state_next;
reg [COUNT_W-1:0] count_reg = 0, count_next; logic [COUNT_W-1:0] count_reg = 0, count_next;
reg [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next; logic [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next;
reg [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next;
reg [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next; logic [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next;
reg [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next; logic [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next;
reg [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next; logic [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next;
reg m_axi_arlock_reg = '0, m_axi_arlock_next; logic m_axi_arlock_reg = '0, m_axi_arlock_next;
reg [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next; logic [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next;
reg [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next;
reg [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next; logic [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next;
reg [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next; logic [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next;
reg [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next;
reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
reg s_axi_arready_reg = 1'b0, s_axi_arready_next; logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
assign m_axi_rd.arid = m_axi_arid_reg; assign m_axi_rd.arid = m_axi_arid_reg;
assign m_axi_rd.araddr = m_axi_araddr_reg; assign m_axi_rd.araddr = m_axi_araddr_reg;

56
src/axi/rtl/taxi_axi_fifo_wr.sv
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@@ -62,20 +62,20 @@ if (m_axi_wr.DATA_W != DATA_W)
if (m_axi_wr.STRB_W != STRB_W) if (m_axi_wr.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next; logic [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next;
reg [FIFO_AW:0] wr_addr_reg = '0; logic [FIFO_AW:0] wr_addr_reg = '0;
reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next; logic [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next;
reg [FIFO_AW:0] rd_addr_reg = '0; logic [FIFO_AW:0] rd_addr_reg = '0;
(* ramstyle = "no_rw_check" *) (* ramstyle = "no_rw_check" *)
reg [WWIDTH-1:0] mem[2**FIFO_AW]; logic [WWIDTH-1:0] mem[2**FIFO_AW];
reg [WWIDTH-1:0] mem_read_data_reg; logic [WWIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; logic mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [WWIDTH-1:0] s_axi_w; wire [WWIDTH-1:0] s_axi_w;
reg [WWIDTH-1:0] m_axi_w_reg; logic [WWIDTH-1:0] m_axi_w_reg;
reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
// full when first MSB different but rest same // full when first MSB different but rest same
wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) && wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) &&
@@ -86,9 +86,9 @@ wire empty = wr_ptr_reg == rd_ptr_reg;
wire hold; wire hold;
// control signals // control signals
reg write; logic write;
reg read; logic read;
reg store_output; logic store_output;
assign s_axi_wr.wready = !full && !hold; assign s_axi_wr.wready = !full && !hold;
assign s_axi_w[DATA_W-1:0] = s_axi_wr.wdata; assign s_axi_w[DATA_W-1:0] = s_axi_wr.wdata;
@@ -104,25 +104,25 @@ if (FIFO_DELAY) begin
STATE_TRANSFER_IN = 2'd1, STATE_TRANSFER_IN = 2'd1,
STATE_TRANSFER_OUT = 2'd2; STATE_TRANSFER_OUT = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next; logic [1:0] state_reg = STATE_IDLE, state_next;
reg hold_reg = 1'b1, hold_next; logic hold_reg = 1'b1, hold_next;
reg [8:0] count_reg = 9'd0, count_next; logic [8:0] count_reg = 9'd0, count_next;
reg [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next; logic [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next;
reg [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next;
reg [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next; logic [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next;
reg [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next; logic [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next;
reg [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next; logic [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next;
reg m_axi_awlock_reg = '0, m_axi_awlock_next; logic m_axi_awlock_reg = '0, m_axi_awlock_next;
reg [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next; logic [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next;
reg [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next;
reg [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next; logic [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next;
reg [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next; logic [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next;
reg [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next;
reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
reg s_axi_awready_reg = 1'b0, s_axi_awready_next; logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
assign m_axi_wr.awid = m_axi_awid_reg; assign m_axi_wr.awid = m_axi_awid_reg;
assign m_axi_wr.awaddr = m_axi_awaddr_reg; assign m_axi_wr.awaddr = m_axi_awaddr_reg;

22
src/axis/rtl/taxi_axis_cobs_encode.sv
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@@ -380,20 +380,20 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [7:0] m_axis_tdata_reg = 8'd0; logic [7:0] m_axis_tdata_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0; logic m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0; logic m_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_axis_tdata_reg = 8'd0; logic [7:0] temp_m_axis_tdata_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0; logic temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0; logic temp_m_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_axis_int_to_output; logic store_axis_int_to_output;
reg store_axis_int_to_temp; logic store_axis_int_to_temp;
reg store_axis_temp_to_output; logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg; assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = 1'b1; assign m_axis.tkeep = 1'b1;

2
src/axis/rtl/taxi_axis_concat.sv
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@@ -123,7 +123,7 @@ end else begin
// destripe // destripe
logic [CL_S_COUNT-1:0] select_reg = '0, select_next; logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next; logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
assign s_axis_tready = s_axis_tready_reg; assign s_axis_tready = s_axis_tready_reg;

62
src/axis/rtl/taxi_axis_mux.sv
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@@ -63,21 +63,21 @@ if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
parameter CL_S_COUNT = $clog2(S_COUNT); parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = '0, select_next; logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
reg frame_reg = 1'b0, frame_next; logic frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next; logic [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
// internal datapath // internal datapath
reg [DATA_W-1:0] m_axis_tdata_int; logic [DATA_W-1:0] m_axis_tdata_int;
reg [KEEP_W-1:0] m_axis_tkeep_int; logic [KEEP_W-1:0] m_axis_tkeep_int;
reg [KEEP_W-1:0] m_axis_tstrb_int; logic [KEEP_W-1:0] m_axis_tstrb_int;
reg m_axis_tvalid_int; logic m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0; logic m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int; logic m_axis_tlast_int;
reg [ID_W-1:0] m_axis_tid_int; logic [ID_W-1:0] m_axis_tid_int;
reg [DEST_W-1:0] m_axis_tdest_int; logic [DEST_W-1:0] m_axis_tdest_int;
reg [USER_W-1:0] m_axis_tuser_int; logic [USER_W-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early; wire m_axis_tready_int_early;
// unpack interface array // unpack interface array
@@ -162,28 +162,28 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0; logic [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg [KEEP_W-1:0] m_axis_tstrb_reg = '0; logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0; logic m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0; logic [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0; logic [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0; logic [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0; logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0; logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0; logic temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0; logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0; logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0; logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control // datapath control
reg store_axis_int_to_output; logic store_axis_int_to_output;
reg store_axis_int_to_temp; logic store_axis_int_to_temp;
reg store_axis_temp_to_output; logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg; assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1; assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;

24
src/dma/rtl/taxi_dma_client_axis_sink.sv
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@@ -484,27 +484,27 @@ end
// output datapath logic (write data) // output datapath logic (write data)
for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin
reg [RAM_SEG_BE_W-1:0] ram_wr_cmd_be_reg = '0; logic [RAM_SEG_BE_W-1:0] ram_wr_cmd_be_reg = '0;
reg [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0; logic [RAM_SEG_ADDR_W-1:0] ram_wr_cmd_addr_reg = '0;
reg [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0; logic [RAM_SEG_DATA_W-1:0] ram_wr_cmd_data_reg = '0;
reg ram_wr_cmd_valid_reg = 1'b0; logic ram_wr_cmd_valid_reg = 1'b0;
reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0; logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
reg [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0; logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
reg out_fifo_half_full_reg = 1'b0; logic out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}}); wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [RAM_SEG_BE_W-1:0] out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW]; logic [RAM_SEG_BE_W-1:0] out_fifo_wr_cmd_be[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW]; logic [RAM_SEG_ADDR_W-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW]; logic [RAM_SEG_DATA_W-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_AW];
reg [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0; logic [OUTPUT_FIFO_AW+1-1:0] done_count_reg = 0;
reg done_reg = 1'b0; logic done_reg = 1'b0;
assign ram_wr_cmd_ready_int[n] = !out_fifo_half_full_reg; assign ram_wr_cmd_ready_int[n] = !out_fifo_half_full_reg;

2
src/dma/rtl/taxi_dma_if_pcie_us_rd.sv
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@@ -1537,7 +1537,7 @@ always_comb begin
end end
end end
reg [1:0] active_tx_count_ovf; logic [1:0] active_tx_count_ovf;
always_comb begin always_comb begin
{active_tx_count_ovf, active_tx_count_next} = $signed({1'b0, active_tx_count_reg}) + $signed({1'b0, inc_active_tx}); {active_tx_count_ovf, active_tx_count_next} = $signed({1'b0, active_tx_count_reg}) + $signed({1'b0, inc_active_tx});

12
src/eth/rtl/taxi_eth_mac_1g_gmii.sv
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@@ -197,8 +197,8 @@ module taxi_eth_mac_1g_gmii #
input wire logic cfg_rx_pfc_en = 1'b0 input wire logic cfg_rx_pfc_en = 1'b0
); );
reg [1:0] link_speed_reg = 2'b10; logic [1:0] link_speed_reg = 2'b10;
reg mii_select_reg = 1'b0; logic mii_select_reg = 1'b0;
wire tx_mii_select_sync; wire tx_mii_select_sync;
@@ -225,7 +225,7 @@ rx_mii_select_sync_inst (
); );
// PHY speed detection // PHY speed detection
reg [2:0] rx_prescale = 3'd0; logic [2:0] rx_prescale = 3'd0;
always_ff @(posedge rx_clk) begin always_ff @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1; rx_prescale <= rx_prescale + 3'd1;
@@ -243,9 +243,9 @@ rx_prescale_sync_inst (
.out(rx_prescale_sync) .out(rx_prescale_sync)
); );
reg [6:0] rx_speed_count_1 = 0; logic [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0; logic [1:0] rx_speed_count_2 = 0;
reg rx_prescale_sync_last_reg = 1'b0; logic rx_prescale_sync_last_reg = 1'b0;
always_ff @(posedge gtx_clk) begin always_ff @(posedge gtx_clk) begin
rx_prescale_sync_last_reg <= rx_prescale_sync; rx_prescale_sync_last_reg <= rx_prescale_sync;

4
src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv
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@@ -183,8 +183,8 @@ end
wire [1:0] link_speed_int; wire [1:0] link_speed_int;
reg [1:0] link_speed_sync_reg_1 = 2'b10; logic [1:0] link_speed_sync_reg_1 = 2'b10;
reg [1:0] link_speed_sync_reg_2 = 2'b10; logic [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2; assign link_speed = link_speed_sync_reg_2;

12
src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
View File

@@ -196,8 +196,8 @@ module taxi_eth_mac_1g_rgmii #
input wire logic cfg_rx_pfc_en = 1'b0 input wire logic cfg_rx_pfc_en = 1'b0
); );
reg [1:0] link_speed_reg = 2'b10; logic [1:0] link_speed_reg = 2'b10;
reg mii_select_reg = 1'b0; logic mii_select_reg = 1'b0;
wire tx_mii_select_sync; wire tx_mii_select_sync;
@@ -224,7 +224,7 @@ rx_mii_select_sync_inst (
); );
// PHY speed detection // PHY speed detection
reg [2:0] rx_prescale = 3'd0; logic [2:0] rx_prescale = 3'd0;
always_ff @(posedge rx_clk) begin always_ff @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1; rx_prescale <= rx_prescale + 3'd1;
@@ -242,9 +242,9 @@ rx_prescale_sync_inst (
.out(rx_prescale_sync) .out(rx_prescale_sync)
); );
reg [6:0] rx_speed_count_1 = 0; logic [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0; logic [1:0] rx_speed_count_2 = 0;
reg rx_prescale_sync_last_reg = 1'b0; logic rx_prescale_sync_last_reg = 1'b0;
always_ff @(posedge gtx_clk) begin always_ff @(posedge gtx_clk) begin
rx_prescale_sync_last_reg <= rx_prescale_sync; rx_prescale_sync_last_reg <= rx_prescale_sync;

4
src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
View File

@@ -182,8 +182,8 @@ end
wire [1:0] link_speed_int; wire [1:0] link_speed_int;
reg [1:0] link_speed_sync_reg_1 = 2'b10; logic [1:0] link_speed_sync_reg_1 = 2'b10;
reg [1:0] link_speed_sync_reg_2 = 2'b10; logic [1:0] link_speed_sync_reg_2 = 2'b10;
assign link_speed = link_speed_sync_reg_2; assign link_speed = link_speed_sync_reg_2;

16
src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -154,10 +154,10 @@ wire rx_ptp_locked;
// synchronize MAC status signals into logic clock domain // synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int; wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = '0; logic [0:0] tx_sync_reg_1 = '0;
reg [0:0] tx_sync_reg_2 = '0; logic [0:0] tx_sync_reg_2 = '0;
reg [0:0] tx_sync_reg_3 = '0; logic [0:0] tx_sync_reg_3 = '0;
reg [0:0] tx_sync_reg_4 = '0; logic [0:0] tx_sync_reg_4 = '0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0]; assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
@@ -189,10 +189,10 @@ wire rx_block_lock_int;
wire rx_high_ber_int; wire rx_high_ber_int;
wire rx_status_int; wire rx_status_int;
reg [6:0] rx_sync_reg_1 = '0; logic [6:0] rx_sync_reg_1 = '0;
reg [6:0] rx_sync_reg_2 = '0; logic [6:0] rx_sync_reg_2 = '0;
reg [6:0] rx_sync_reg_3 = '0; logic [6:0] rx_sync_reg_3 = '0;
reg [6:0] rx_sync_reg_4 = '0; logic [6:0] rx_sync_reg_4 = '0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0]; assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1]; assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];

10
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
View File

@@ -100,15 +100,15 @@ end
if (SERDES_PIPELINE > 0) begin if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *) (* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0]; logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *) (* srl_style = "register" *)
reg serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *) (* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0]; logic [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *) (* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *) (* srl_style = "register" *)
reg serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin initial begin

34
src/eth/rtl/taxi_mac_ctrl_rx.sv
View File

@@ -317,26 +317,26 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0; logic [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0; logic m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0; logic [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0; logic [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0; logic [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0; logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0; logic temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0; logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0; logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0; logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control // datapath control
reg store_axis_int_to_output; logic store_axis_int_to_output;
reg store_axis_int_to_temp; logic store_axis_int_to_temp;
reg store_axis_temp_to_output; logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg; assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1; assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;

34
src/eth/rtl/taxi_mac_ctrl_tx.sv
View File

@@ -290,26 +290,26 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0; logic [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0; logic m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0; logic [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0; logic [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0; logic [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0; logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0; logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0; logic temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0; logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0; logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0; logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control // datapath control
reg store_axis_int_to_output; logic store_axis_int_to_output;
reg store_axis_int_to_temp; logic store_axis_int_to_temp;
reg store_axis_temp_to_output; logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg; assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1; assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;

4
src/eth/rtl/taxi_mii_phy_if.sv
View File

@@ -68,9 +68,9 @@ rx_ssio_sdr_inst (
); );
(* IOB = "TRUE" *) (* IOB = "TRUE" *)
reg [3:0] phy_mii_txd_reg = 4'd0; logic [3:0] phy_mii_txd_reg = 4'd0;
(* IOB = "TRUE" *) (* IOB = "TRUE" *)
reg phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0; logic phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
assign phy_mii_txd = phy_mii_txd_reg; assign phy_mii_txd = phy_mii_txd_reg;
assign phy_mii_tx_en = phy_mii_tx_en_reg; assign phy_mii_tx_en = phy_mii_tx_en_reg;

4
src/lfsr/rtl/taxi_lfsr_scramble.sv
View File

@@ -148,8 +148,8 @@ pcie Galois, bit-reverse 16 16'h0039 16'hffff PCIe
*/ */
reg [LFSR_W-1:0] state_reg = LFSR_INIT; logic [LFSR_W-1:0] state_reg = LFSR_INIT;
reg [DATA_W-1:0] output_reg = '0; logic [DATA_W-1:0] output_reg = '0;
wire [DATA_W-1:0] lfsr_data; wire [DATA_W-1:0] lfsr_data;
wire [LFSR_W-1:0] lfsr_state; wire [LFSR_W-1:0] lfsr_state;

2
src/lss/rtl/taxi_i2c_init.sv
View File

@@ -160,7 +160,7 @@ endfunction
// init_data ROM // init_data ROM
localparam INIT_DATA_LEN = 22; localparam INIT_DATA_LEN = 22;
reg [8:0] init_data [INIT_DATA_LEN-1:0]; logic [8:0] init_data [INIT_DATA_LEN-1:0];
initial begin initial begin
// single address // single address

28
src/pcie/rtl/taxi_pcie_us_axil_master.sv
View File

@@ -729,22 +729,22 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [AXIS_PCIE_DATA_W-1:0] m_axis_cc_tdata_reg = '0; logic [AXIS_PCIE_DATA_W-1:0] m_axis_cc_tdata_reg = '0;
reg [AXIS_PCIE_KEEP_W-1:0] m_axis_cc_tkeep_reg = '0; logic [AXIS_PCIE_KEEP_W-1:0] m_axis_cc_tkeep_reg = '0;
reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next; logic m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next;
reg m_axis_cc_tlast_reg = 1'b0; logic m_axis_cc_tlast_reg = 1'b0;
reg [AXIS_PCIE_CC_USER_W-1:0] m_axis_cc_tuser_reg = '0; logic [AXIS_PCIE_CC_USER_W-1:0] m_axis_cc_tuser_reg = '0;
reg [AXIS_PCIE_DATA_W-1:0] temp_m_axis_cc_tdata_reg = '0; logic [AXIS_PCIE_DATA_W-1:0] temp_m_axis_cc_tdata_reg = '0;
reg [AXIS_PCIE_KEEP_W-1:0] temp_m_axis_cc_tkeep_reg = '0; logic [AXIS_PCIE_KEEP_W-1:0] temp_m_axis_cc_tkeep_reg = '0;
reg temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next; logic temp_m_axis_cc_tvalid_reg = 1'b0, temp_m_axis_cc_tvalid_next;
reg temp_m_axis_cc_tlast_reg = 1'b0; logic temp_m_axis_cc_tlast_reg = 1'b0;
reg [AXIS_PCIE_CC_USER_W-1:0] temp_m_axis_cc_tuser_reg = '0; logic [AXIS_PCIE_CC_USER_W-1:0] temp_m_axis_cc_tuser_reg = '0;
// datapath control // datapath control
reg store_axis_int_to_output; logic store_axis_int_to_output;
reg store_axis_int_to_temp; logic store_axis_int_to_temp;
reg store_axis_temp_to_output; logic store_axis_temp_to_output;
assign m_axis_cc.tdata = m_axis_cc_tdata_reg; assign m_axis_cc.tdata = m_axis_cc_tdata_reg;
assign m_axis_cc.tkeep = m_axis_cc_tkeep_reg; assign m_axis_cc.tkeep = m_axis_cc_tkeep_reg;
@@ -766,7 +766,7 @@ always_comb begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (m_axis_cc_tready_int_reg) begin if (m_axis_cc_tready_int_reg) begin
// input is ready // input is ready
if (m_axis_cc.tready || !m_axis_cc_tvalid_reg) begin if (m_axis_cc.tready || !m_axis_cc_tvalid_reg) begin

2
src/ptp/rtl/taxi_ptp_td_leaf.sv
View File

@@ -97,7 +97,7 @@ assign ptp_td_sdi_pipe[0] = ptp_td_sdi;
for (genvar n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage for (genvar n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage
(* shreg_extract = "no" *) (* shreg_extract = "no" *)
reg ptp_td_sdi_reg = 0; logic ptp_td_sdi_reg = 0;
assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg; assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg;

2
src/ptp/rtl/taxi_ptp_td_rel2tod.sv
View File

@@ -59,7 +59,7 @@ assign ptp_td_sdi_pipe[0] = ptp_td_sdi;
for (genvar n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage for (genvar n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage
(* shreg_extract = "no" *) (* shreg_extract = "no" *)
reg ptp_td_sdi_reg = 0; logic ptp_td_sdi_reg = 0;
assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg; assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg;

10
src/xfcp/rtl/taxi_xfcp_mod_apb.sv
View File

@@ -86,9 +86,9 @@ localparam ID_RESP = 8'hFF;
// ID ROM // ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5; localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W; localparam ID_ROM_SIZE = 2**ID_PTR_W;
reg [7:0] id_rom[ID_ROM_SIZE]; logic [7:0] id_rom[ID_ROM_SIZE];
reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next; logic [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j; integer j;
@@ -584,9 +584,9 @@ logic temp_xfcp_usp_us_tlast_reg = 1'b0;
logic temp_xfcp_usp_us_tuser_reg = 1'b0; logic temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_xfcp_usp_us_int_to_output; logic store_xfcp_usp_us_int_to_output;
reg store_xfcp_usp_us_int_to_temp; logic store_xfcp_usp_us_int_to_temp;
reg store_xfcp_usp_us_temp_to_output; logic store_xfcp_usp_us_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg; assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1; assign xfcp_usp_us.tkeep = '1;

10
src/xfcp/rtl/taxi_xfcp_mod_axil.sv
View File

@@ -87,9 +87,9 @@ localparam ID_RESP = 8'hFF;
// ID ROM // ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5; localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W; localparam ID_ROM_SIZE = 2**ID_PTR_W;
reg [7:0] id_rom[ID_ROM_SIZE]; logic [7:0] id_rom[ID_ROM_SIZE];
reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next; logic [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j; integer j;
@@ -597,9 +597,9 @@ logic temp_xfcp_usp_us_tlast_reg = 1'b0;
logic temp_xfcp_usp_us_tuser_reg = 1'b0; logic temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_xfcp_usp_us_int_to_output; logic store_xfcp_usp_us_int_to_output;
reg store_xfcp_usp_us_int_to_temp; logic store_xfcp_usp_us_int_to_temp;
reg store_xfcp_usp_us_temp_to_output; logic store_xfcp_usp_us_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg; assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1; assign xfcp_usp_us.tkeep = '1;

22
src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv
View File

@@ -691,20 +691,20 @@ always_ff @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [7:0] xfcp_usp_us_tdata_reg = 8'd0; logic [7:0] xfcp_usp_us_tdata_reg = 8'd0;
reg xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next; logic xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next;
reg xfcp_usp_us_tlast_reg = 1'b0; logic xfcp_usp_us_tlast_reg = 1'b0;
reg xfcp_usp_us_tuser_reg = 1'b0; logic xfcp_usp_us_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0; logic [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0;
reg temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next; logic temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next;
reg temp_xfcp_usp_us_tlast_reg = 1'b0; logic temp_xfcp_usp_us_tlast_reg = 1'b0;
reg temp_xfcp_usp_us_tuser_reg = 1'b0; logic temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_up_xfcp_int_to_output; logic store_up_xfcp_int_to_output;
reg store_up_xfcp_int_to_temp; logic store_up_xfcp_int_to_temp;
reg store_up_xfcp_temp_to_output; logic store_up_xfcp_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg; assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1; assign xfcp_usp_us.tkeep = '1;

98
src/xfcp/rtl/taxi_xfcp_switch.sv
View File

@@ -53,9 +53,9 @@ localparam ID_RESP = 8'hFF;
// ID ROM // ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5; localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W; localparam ID_ROM_SIZE = 2**ID_PTR_W;
reg [7:0] id_rom[ID_ROM_SIZE]; logic [7:0] id_rom[ID_ROM_SIZE];
reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next; logic [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j; integer j;
@@ -115,49 +115,49 @@ localparam [2:0]
DN_STATE_PKT = 3'd3, DN_STATE_PKT = 3'd3,
DN_STATE_ID = 3'd4; DN_STATE_ID = 3'd4;
reg [2:0] dn_state_reg = DN_STATE_IDLE, dn_state_next; logic [2:0] dn_state_reg = DN_STATE_IDLE, dn_state_next;
localparam [0:0] localparam [0:0]
UP_STATE_IDLE = 1'd0, UP_STATE_IDLE = 1'd0,
UP_STATE_TRANSFER = 1'd1; UP_STATE_TRANSFER = 1'd1;
reg [0:0] up_state_reg = UP_STATE_IDLE, up_state_next; logic [0:0] up_state_reg = UP_STATE_IDLE, up_state_next;
reg [CL_PORTS-1:0] dn_select_reg = '0, dn_select_next; logic [CL_PORTS-1:0] dn_select_reg = '0, dn_select_next;
reg dn_frame_reg = 1'b0, dn_frame_next; logic dn_frame_reg = 1'b0, dn_frame_next;
reg dn_enable_reg = 1'b0, dn_enable_next; logic dn_enable_reg = 1'b0, dn_enable_next;
reg [CL_PORTS_P1-1:0] up_select_reg = '0, up_select_next; logic [CL_PORTS_P1-1:0] up_select_reg = '0, up_select_next;
reg up_frame_reg = 1'b0, up_frame_next; logic up_frame_reg = 1'b0, up_frame_next;
reg xfcp_usp_ds_tready_reg = 1'b0, xfcp_usp_ds_tready_next; logic xfcp_usp_ds_tready_reg = 1'b0, xfcp_usp_ds_tready_next;
reg [PORTS-1:0] xfcp_dsp_us_tready_reg = '0, xfcp_dsp_us_tready_next; logic [PORTS-1:0] xfcp_dsp_us_tready_reg = '0, xfcp_dsp_us_tready_next;
wire [PORTS-1:0] xfcp_dsp_ds_tready; wire [PORTS-1:0] xfcp_dsp_ds_tready;
wire [PORTS-1:0] xfcp_dsp_ds_tvalid; wire [PORTS-1:0] xfcp_dsp_ds_tvalid;
// internal datapath // internal datapath
reg [7:0] xfcp_usp_us_tdata_int; logic [7:0] xfcp_usp_us_tdata_int;
reg xfcp_usp_us_tvalid_int; logic xfcp_usp_us_tvalid_int;
reg xfcp_usp_us_tready_int_reg = 1'b0; logic xfcp_usp_us_tready_int_reg = 1'b0;
reg xfcp_usp_us_tlast_int; logic xfcp_usp_us_tlast_int;
reg xfcp_usp_us_tuser_int; logic xfcp_usp_us_tuser_int;
wire xfcp_usp_us_tready_int_early; wire xfcp_usp_us_tready_int_early;
reg [7:0] xfcp_dsp_ds_tdata_int; logic [7:0] xfcp_dsp_ds_tdata_int;
reg [PORTS-1:0] xfcp_dsp_ds_tvalid_int; logic [PORTS-1:0] xfcp_dsp_ds_tvalid_int;
reg xfcp_dsp_ds_tready_int_reg = 1'b0; logic xfcp_dsp_ds_tready_int_reg = 1'b0;
reg xfcp_dsp_ds_tlast_int; logic xfcp_dsp_ds_tlast_int;
reg xfcp_dsp_ds_tuser_int; logic xfcp_dsp_ds_tuser_int;
wire xfcp_dsp_ds_tready_int_early; wire xfcp_dsp_ds_tready_int_early;
reg [7:0] int_loop_tdata_reg = 8'd0, int_loop_tdata_next; logic [7:0] int_loop_tdata_reg = 8'd0, int_loop_tdata_next;
reg int_loop_tvalid_reg = 1'b0, int_loop_tvalid_next; logic int_loop_tvalid_reg = 1'b0, int_loop_tvalid_next;
reg int_loop_tready; logic int_loop_tready;
reg int_loop_tready_early; logic int_loop_tready_early;
reg int_loop_tlast_reg = 1'b0, int_loop_tlast_next; logic int_loop_tlast_reg = 1'b0, int_loop_tlast_next;
reg int_loop_tuser_reg = 1'b0, int_loop_tuser_next; logic int_loop_tuser_reg = 1'b0, int_loop_tuser_next;
assign xfcp_usp_ds.tready = xfcp_usp_ds_tready_reg; assign xfcp_usp_ds.tready = xfcp_usp_ds_tready_reg;
@@ -499,20 +499,20 @@ always_ff @(posedge clk) begin
end end
// upstream output datapath logic // upstream output datapath logic
reg [7:0] xfcp_usp_us_tdata_reg = 8'd0; logic [7:0] xfcp_usp_us_tdata_reg = 8'd0;
reg xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next; logic xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next;
reg xfcp_usp_us_tlast_reg = 1'b0; logic xfcp_usp_us_tlast_reg = 1'b0;
reg xfcp_usp_us_tuser_reg = 1'b0; logic xfcp_usp_us_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0; logic [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0;
reg temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next; logic temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next;
reg temp_xfcp_usp_us_tlast_reg = 1'b0; logic temp_xfcp_usp_us_tlast_reg = 1'b0;
reg temp_xfcp_usp_us_tuser_reg = 1'b0; logic temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_xfcp_usp_us_int_to_output; logic store_xfcp_usp_us_int_to_output;
reg store_xfcp_usp_us_int_to_temp; logic store_xfcp_usp_us_int_to_temp;
reg store_xfcp_usp_us_temp_to_output; logic store_xfcp_usp_us_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg; assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1; assign xfcp_usp_us.tkeep = '1;
@@ -584,20 +584,20 @@ always_ff @(posedge clk) begin
end end
// downstream output datapath logic // downstream output datapath logic
reg [7:0] xfcp_dsp_ds_tdata_reg = 8'd0; logic [7:0] xfcp_dsp_ds_tdata_reg = 8'd0;
reg [PORTS-1:0] xfcp_dsp_ds_tvalid_reg = '0, xfcp_dsp_ds_tvalid_next; logic [PORTS-1:0] xfcp_dsp_ds_tvalid_reg = '0, xfcp_dsp_ds_tvalid_next;
reg xfcp_dsp_ds_tlast_reg = 1'b0; logic xfcp_dsp_ds_tlast_reg = 1'b0;
reg xfcp_dsp_ds_tuser_reg = 1'b0; logic xfcp_dsp_ds_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_dsp_ds_tdata_reg = 8'd0; logic [7:0] temp_xfcp_dsp_ds_tdata_reg = 8'd0;
reg [PORTS-1:0] temp_xfcp_dsp_ds_tvalid_reg = '0, temp_xfcp_dsp_ds_tvalid_next; logic [PORTS-1:0] temp_xfcp_dsp_ds_tvalid_reg = '0, temp_xfcp_dsp_ds_tvalid_next;
reg temp_xfcp_dsp_ds_tlast_reg = 1'b0; logic temp_xfcp_dsp_ds_tlast_reg = 1'b0;
reg temp_xfcp_dsp_ds_tuser_reg = 1'b0; logic temp_xfcp_dsp_ds_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_xfcp_dsp_ds_to_output; logic store_xfcp_dsp_ds_to_output;
reg store_xfcp_dsp_ds_to_temp; logic store_xfcp_dsp_ds_to_temp;
reg store_xfcp_dsp_ds_temp_to_output; logic store_xfcp_dsp_ds_temp_to_output;
assign xfcp_dsp_ds_tvalid = xfcp_dsp_ds_tvalid_reg; assign xfcp_dsp_ds_tvalid = xfcp_dsp_ds_tvalid_reg;