diff --git a/src/eth/rtl/taxi_axis_baser_tx_32.sv b/src/eth/rtl/taxi_axis_baser_tx_32.sv index 9970716..25c60ff 100644 --- a/src/eth/rtl/taxi_axis_baser_tx_32.sv +++ b/src/eth/rtl/taxi_axis_baser_tx_32.sv @@ -177,7 +177,6 @@ out_type_t fcs_output_type_0; out_type_t fcs_output_type_1; logic [7:0] ifg_offset; - logic extra_cycle; logic frame_reg = 1'b0, frame_next; @@ -192,9 +191,7 @@ logic [13:0] frame_len_lim_cyc_reg = '0, frame_len_lim_cyc_next; logic [1:0] frame_len_lim_last_reg = '0, frame_len_lim_last_next; logic frame_len_lim_check_reg = '0, frame_len_lim_check_next; logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next; - -logic [7:0] ifg_count_reg = 8'd0, ifg_count_next; -logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; +logic [1:0] deficit_idle_cnt_reg = 2'd0, deficit_idle_cnt_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next; @@ -344,9 +341,7 @@ always_comb begin frame_len_lim_last_next = frame_len_lim_last_reg; frame_len_lim_check_next = frame_len_lim_check_reg; ifg_cnt_next = ifg_cnt_reg; - - ifg_count_next = ifg_count_reg; - deficit_idle_count_next = deficit_idle_count_reg; + deficit_idle_cnt_next = deficit_idle_cnt_reg; s_axis_tx_tready_next = 1'b0; @@ -470,8 +465,8 @@ always_comb begin s_axis_tx_tready_next = 1'b1; state_next = STATE_PREAMBLE; end else begin - ifg_count_next = 8'd0; - deficit_idle_count_next = 2'd0; + ifg_cnt_next = 8'd0; + deficit_idle_cnt_next = 2'd0; state_next = STATE_IDLE; end end @@ -538,7 +533,6 @@ always_comb begin stat_tx_byte_next = 3'(KEEP_W); - ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_count_reg); if (frame_error_reg) begin state_next = STATE_ERR; end else begin @@ -555,6 +549,8 @@ always_comb begin stat_tx_byte_next = 4-s_empty_reg; frame_len_next = frame_len_reg + 16'(4-s_empty_reg); + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_cnt_reg); + if (extra_cycle) begin state_next = STATE_FCS_3; end else begin @@ -585,17 +581,19 @@ always_comb begin stat_tx_pkt_vlan_next = is_8021q_reg; stat_tx_err_oversize_next = frame_oversize_reg; + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_cnt_reg); + if (DIC_EN) begin - if (ifg_count_next > 8'd3) begin + if (ifg_cnt_next > 8'd3) begin state_next = STATE_IFG; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; s_axis_tx_tready_next = 1'b1; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd0) begin + if (ifg_cnt_next > 8'd0) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -609,7 +607,7 @@ always_comb begin output_data_next = s_tdata_reg; output_type_next = OUTPUT_TYPE_ERROR; - ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; + ifg_cnt_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; stat_tx_pkt_len_next = frame_len_reg; stat_tx_pkt_good_next = !frame_error_reg; @@ -629,22 +627,16 @@ always_comb begin output_data_next = s_tdata_reg; output_type_next = OUTPUT_TYPE_IDLE; - if (ifg_count_reg > 8'd4) begin - ifg_count_next = ifg_count_reg - 8'd4; - end else begin - ifg_count_next = 8'd0; - end - if (DIC_EN) begin - if (ifg_count_next > 8'd3 || frame_reg) begin + if (ifg_cnt_next > 8'd3 || frame_reg) begin state_next = STATE_IFG; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd0 || frame_reg) begin + if (ifg_cnt_next > 8'd0 || frame_reg) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -674,9 +666,7 @@ always_ff @(posedge clk) begin frame_len_lim_last_reg <= frame_len_lim_last_next; frame_len_lim_check_reg <= frame_len_lim_check_next; ifg_cnt_reg <= ifg_cnt_next; - - ifg_count_reg <= ifg_count_next; - deficit_idle_count_reg <= deficit_idle_count_next; + deficit_idle_cnt_reg <= deficit_idle_cnt_next; s_tdata_reg <= s_tdata_next; s_empty_reg <= s_empty_next; @@ -820,9 +810,7 @@ always_ff @(posedge clk) begin state_reg <= STATE_IDLE; frame_reg <= 1'b0; - - ifg_count_reg <= 8'd0; - deficit_idle_count_reg <= 2'd0; + deficit_idle_cnt_reg <= 2'd0; s_axis_tx_tready_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_baser_tx_64.sv b/src/eth/rtl/taxi_axis_baser_tx_64.sv index 0d15a74..f362236 100644 --- a/src/eth/rtl/taxi_axis_baser_tx_64.sv +++ b/src/eth/rtl/taxi_axis_baser_tx_64.sv @@ -187,6 +187,7 @@ out_type_t fcs_output_type_0; out_type_t fcs_output_type_1; logic [7:0] ifg_offset; +logic extra_cycle; logic frame_start_reg = 1'b0, frame_start_next; logic frame_reg = 1'b0, frame_next; @@ -201,9 +202,7 @@ logic [12:0] frame_len_lim_cyc_reg = '0, frame_len_lim_cyc_next; logic [2:0] frame_len_lim_last_reg = '0, frame_len_lim_last_next; logic frame_len_lim_check_reg = '0, frame_len_lim_check_next; logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next; - -logic [7:0] ifg_count_reg = 8'd0, ifg_count_next; -logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; +logic [1:0] deficit_idle_cnt_reg = 2'd0, deficit_idle_cnt_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next; @@ -317,6 +316,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_TERM_5; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd3; + extra_cycle = 1'b0; end 3'd6: begin fcs_output_data_0 = {16'd0, ~crc_state[31:0], s_tdata_reg[15:0]}; @@ -324,6 +324,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_TERM_6; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd2; + extra_cycle = 1'b0; end 3'd5: begin fcs_output_data_0 = {8'd0, ~crc_state[31:0], s_tdata_reg[23:0]}; @@ -331,6 +332,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_TERM_7; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd1; + extra_cycle = 1'b0; end 3'd4: begin fcs_output_data_0 = {~crc_state[31:0], s_tdata_reg[31:0]}; @@ -338,6 +340,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_0; ifg_offset = 8'd8; + extra_cycle = 1'b1; end 3'd3: begin fcs_output_data_0 = {~crc_state[23:0], s_tdata_reg[39:0]}; @@ -345,6 +348,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_1; ifg_offset = 8'd7; + extra_cycle = 1'b1; end 3'd2: begin fcs_output_data_0 = {~crc_state[15:0], s_tdata_reg[47:0]}; @@ -352,6 +356,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_2; ifg_offset = 8'd6; + extra_cycle = 1'b1; end 3'd1: begin fcs_output_data_0 = {~crc_state[7:0], s_tdata_reg[55:0]}; @@ -359,6 +364,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_3; ifg_offset = 8'd5; + extra_cycle = 1'b1; end 3'd0: begin fcs_output_data_0 = s_tdata_reg; @@ -366,6 +372,7 @@ always_comb begin fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_4; ifg_offset = 8'd4; + extra_cycle = 1'b1; end endcase end @@ -373,7 +380,6 @@ end always_comb begin state_next = STATE_IDLE; - swap_lanes_next = swap_lanes_reg; frame_start_next = 1'b0; @@ -389,9 +395,7 @@ always_comb begin frame_len_lim_last_next = frame_len_lim_last_reg; frame_len_lim_check_next = frame_len_lim_check_reg; ifg_cnt_next = ifg_cnt_reg; - - ifg_count_next = ifg_count_reg; - deficit_idle_count_next = deficit_idle_count_reg; + deficit_idle_cnt_next = deficit_idle_cnt_reg; s_axis_tx_tready_next = 1'b0; @@ -515,8 +519,8 @@ always_comb begin state_next = STATE_PAYLOAD; end else begin swap_lanes_next = 1'b0; - ifg_count_next = 8'd0; - deficit_idle_count_next = 2'd0; + ifg_cnt_next = 8'd0; + deficit_idle_cnt_next = 2'd0; state_next = STATE_IDLE; end end @@ -567,8 +571,9 @@ always_comb begin output_data_next = fcs_output_data_0; output_type_next = fcs_output_type_0; - ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_count_reg); - if (s_empty_reg <= 4) begin + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_cnt_reg); + + if (extra_cycle) begin stat_tx_byte_next = 4'(KEEP_W); state_next = STATE_FCS_2; end else begin @@ -607,27 +612,29 @@ always_comb begin crc_data_next = {24'd0, s_axis_tx.tdata} ^ {56'd0, 32'hffffffff}; + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_cnt_reg); + if (DIC_EN) begin - if (ifg_count_next > 8'd7) begin + if (ifg_cnt_next > 8'd7) begin state_next = STATE_IFG; end else begin - if (ifg_count_next >= 8'd4) begin - deficit_idle_count_next = 2'(ifg_count_next - 8'd4); + if (ifg_cnt_next >= 8'd4) begin + deficit_idle_cnt_next = 2'(ifg_cnt_next - 8'd4); swap_lanes_next = 1'b1; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; swap_lanes_next = 1'b0; end s_axis_tx_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd4) begin + if (ifg_cnt_next > 8'd4) begin state_next = STATE_IFG; end else begin s_axis_tx_tready_next = cfg_tx_enable; - swap_lanes_next = ifg_count_next != 0; + swap_lanes_next = ifg_cnt_next != 0; state_next = STATE_IDLE; end end @@ -639,7 +646,7 @@ always_comb begin output_data_next = s_tdata_reg; output_type_next = OUTPUT_TYPE_ERROR; - ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; + ifg_cnt_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; stat_tx_pkt_len_next = frame_len_reg; stat_tx_pkt_good_next = !frame_error_reg; @@ -661,33 +668,27 @@ always_comb begin crc_data_next = {24'd0, s_axis_tx.tdata} ^ {56'd0, 32'hffffffff}; - if (ifg_count_reg > 8'd8) begin - ifg_count_next = ifg_count_reg - 8'd8; - end else begin - ifg_count_next = 8'd0; - end - if (DIC_EN) begin - if (ifg_count_next > 8'd7 || frame_reg) begin + if (ifg_cnt_next > 8'd7 || frame_reg) begin state_next = STATE_IFG; end else begin - if (ifg_count_next >= 8'd4) begin - deficit_idle_count_next = 2'(ifg_count_next - 8'd4); + if (ifg_cnt_next >= 8'd4) begin + deficit_idle_cnt_next = 2'(ifg_cnt_next - 8'd4); swap_lanes_next = 1'b1; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; swap_lanes_next = 1'b0; end s_axis_tx_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd4 || frame_reg) begin + if (ifg_cnt_next > 8'd4 || frame_reg) begin state_next = STATE_IFG; end else begin s_axis_tx_tready_next = cfg_tx_enable; - swap_lanes_next = ifg_count_next != 0; + swap_lanes_next = ifg_cnt_next != 0; state_next = STATE_IDLE; end end @@ -718,9 +719,7 @@ always_ff @(posedge clk) begin frame_len_lim_last_reg <= frame_len_lim_last_next; frame_len_lim_check_reg <= frame_len_lim_check_next; ifg_cnt_reg <= ifg_cnt_next; - - ifg_count_reg <= ifg_count_next; - deficit_idle_count_reg <= deficit_idle_count_next; + deficit_idle_cnt_reg <= deficit_idle_cnt_next; s_tdata_reg <= s_tdata_next; s_empty_reg <= s_empty_next; @@ -966,14 +965,12 @@ always_ff @(posedge clk) begin if (rst) begin state_reg <= STATE_IDLE; - frame_start_reg <= 1'b0; - frame_reg <= 1'b0; - swap_lanes_reg <= 1'b0; swap_lanes_d1_reg <= 1'b0; - ifg_count_reg <= 8'd0; - deficit_idle_count_reg <= 2'd0; + frame_start_reg <= 1'b0; + frame_reg <= 1'b0; + deficit_idle_cnt_reg <= 2'd0; s_axis_tx_tready_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_xgmii_tx_32.sv b/src/eth/rtl/taxi_axis_xgmii_tx_32.sv index 5c747b1..04f121a 100644 --- a/src/eth/rtl/taxi_axis_xgmii_tx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_tx_32.sv @@ -138,7 +138,6 @@ logic [CTRL_W-1:0] fcs_output_txc_0; logic [CTRL_W-1:0] fcs_output_txc_1; logic [7:0] ifg_offset; - logic extra_cycle; logic frame_reg = 1'b0, frame_next; @@ -153,9 +152,7 @@ logic [13:0] frame_len_lim_cyc_reg = '0, frame_len_lim_cyc_next; logic [1:0] frame_len_lim_last_reg = '0, frame_len_lim_last_next; logic frame_len_lim_check_reg = '0, frame_len_lim_check_next; logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next; - -logic [7:0] ifg_count_reg = 8'd0, ifg_count_next; -logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; +logic [1:0] deficit_idle_cnt_reg = 2'd0, deficit_idle_cnt_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next; @@ -286,7 +283,6 @@ end always_comb begin state_next = STATE_IDLE; - frame_next = frame_reg; frame_error_next = frame_error_reg; frame_oversize_next = frame_oversize_reg; @@ -299,9 +295,7 @@ always_comb begin frame_len_lim_last_next = frame_len_lim_last_reg; frame_len_lim_check_next = frame_len_lim_check_reg; ifg_cnt_next = ifg_cnt_reg; - - ifg_count_next = ifg_count_reg; - deficit_idle_count_next = deficit_idle_count_reg; + deficit_idle_cnt_next = deficit_idle_cnt_reg; s_axis_tx_tready_next = 1'b0; @@ -428,8 +422,8 @@ always_comb begin s_axis_tx_tready_next = 1'b1; state_next = STATE_PREAMBLE; end else begin - ifg_count_next = 8'd0; - deficit_idle_count_next = 2'd0; + ifg_cnt_next = 8'd0; + deficit_idle_cnt_next = 2'd0; state_next = STATE_IDLE; end end @@ -496,7 +490,6 @@ always_comb begin stat_tx_byte_next = 3'(CTRL_W); - ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_count_reg); if (frame_error_reg) begin state_next = STATE_ERR; end else begin @@ -513,6 +506,8 @@ always_comb begin stat_tx_byte_next = 4-s_empty_reg; frame_len_next = frame_len_reg + 16'(4-s_empty_reg); + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_cnt_reg); + if (extra_cycle) begin state_next = STATE_FCS_3; end else begin @@ -543,17 +538,19 @@ always_comb begin stat_tx_pkt_vlan_next = is_8021q_reg; stat_tx_err_oversize_next = frame_oversize_reg; + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_cnt_reg); + if (DIC_EN) begin - if (ifg_count_next > 8'd3) begin + if (ifg_cnt_next > 8'd3) begin state_next = STATE_IFG; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; s_axis_tx_tready_next = 1'b1; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd0) begin + if (ifg_cnt_next > 8'd0) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -568,7 +565,7 @@ always_comb begin xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}}; xgmii_txc_next = {CTRL_W{1'b1}}; - ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; + ifg_cnt_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; stat_tx_pkt_len_next = frame_len_reg; stat_tx_pkt_good_next = !frame_error_reg; @@ -589,22 +586,16 @@ always_comb begin xgmii_txd_next = {CTRL_W{XGMII_IDLE}}; xgmii_txc_next = {CTRL_W{1'b1}}; - if (ifg_count_reg > 8'd4) begin - ifg_count_next = ifg_count_reg - 8'd4; - end else begin - ifg_count_next = 8'd0; - end - if (DIC_EN) begin - if (ifg_count_next > 8'd3 || frame_reg) begin + if (ifg_cnt_next > 8'd3 || frame_reg) begin state_next = STATE_IFG; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd0 || frame_reg) begin + if (ifg_cnt_next > 8'd0 || frame_reg) begin state_next = STATE_IFG; end else begin state_next = STATE_IDLE; @@ -634,9 +625,7 @@ always_ff @(posedge clk) begin frame_len_lim_last_reg <= frame_len_lim_last_next; frame_len_lim_check_reg <= frame_len_lim_check_next; ifg_cnt_reg <= ifg_cnt_next; - - ifg_count_reg <= ifg_count_next; - deficit_idle_count_reg <= deficit_idle_count_next; + deficit_idle_cnt_reg <= deficit_idle_cnt_next; s_tdata_reg <= s_tdata_next; s_empty_reg <= s_empty_next; @@ -679,9 +668,7 @@ always_ff @(posedge clk) begin state_reg <= STATE_IDLE; frame_reg <= 1'b0; - - ifg_count_reg <= 8'd0; - deficit_idle_count_reg <= 2'd0; + deficit_idle_cnt_reg <= 2'd0; s_axis_tx_tready_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_xgmii_tx_64.sv b/src/eth/rtl/taxi_axis_xgmii_tx_64.sv index 7116800..0efa814 100644 --- a/src/eth/rtl/taxi_axis_xgmii_tx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_tx_64.sv @@ -141,6 +141,7 @@ logic [CTRL_W-1:0] fcs_output_txc_0; logic [CTRL_W-1:0] fcs_output_txc_1; logic [7:0] ifg_offset; +logic extra_cycle; logic frame_start_reg = 1'b0, frame_start_next; logic frame_reg = 1'b0, frame_next; @@ -155,9 +156,7 @@ logic [12:0] frame_len_lim_cyc_reg = '0, frame_len_lim_cyc_next; logic [2:0] frame_len_lim_last_reg = '0, frame_len_lim_last_next; logic frame_len_lim_check_reg = '0, frame_len_lim_check_next; logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next; - -logic [7:0] ifg_count_reg = 8'd0, ifg_count_next; -logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; +logic [1:0] deficit_idle_cnt_reg = 2'd0, deficit_idle_cnt_next; logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next; @@ -266,6 +265,7 @@ always_comb begin fcs_output_txc_0 = 8'b11100000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd3; + extra_cycle = 1'b0; end 3'd6: begin fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state[31:0], s_tdata_reg[15:0]}; @@ -273,6 +273,7 @@ always_comb begin fcs_output_txc_0 = 8'b11000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd2; + extra_cycle = 1'b0; end 3'd5: begin fcs_output_txd_0 = {XGMII_TERM, ~crc_state[31:0], s_tdata_reg[23:0]}; @@ -280,6 +281,7 @@ always_comb begin fcs_output_txc_0 = 8'b10000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd1; + extra_cycle = 1'b0; end 3'd4: begin fcs_output_txd_0 = {~crc_state[31:0], s_tdata_reg[31:0]}; @@ -287,6 +289,7 @@ always_comb begin fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd8; + extra_cycle = 1'b1; end 3'd3: begin fcs_output_txd_0 = {~crc_state[23:0], s_tdata_reg[39:0]}; @@ -294,6 +297,7 @@ always_comb begin fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111110; ifg_offset = 8'd7; + extra_cycle = 1'b1; end 3'd2: begin fcs_output_txd_0 = {~crc_state[15:0], s_tdata_reg[47:0]}; @@ -301,6 +305,7 @@ always_comb begin fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111100; ifg_offset = 8'd6; + extra_cycle = 1'b1; end 3'd1: begin fcs_output_txd_0 = {~crc_state[7:0], s_tdata_reg[55:0]}; @@ -308,6 +313,7 @@ always_comb begin fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111000; ifg_offset = 8'd5; + extra_cycle = 1'b1; end 3'd0: begin fcs_output_txd_0 = s_tdata_reg; @@ -315,6 +321,7 @@ always_comb begin fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11110000; ifg_offset = 8'd4; + extra_cycle = 1'b1; end endcase end @@ -337,9 +344,7 @@ always_comb begin frame_len_lim_last_next = frame_len_lim_last_reg; frame_len_lim_check_next = frame_len_lim_check_reg; ifg_cnt_next = ifg_cnt_reg; - - ifg_count_next = ifg_count_reg; - deficit_idle_count_next = deficit_idle_count_reg; + deficit_idle_cnt_next = deficit_idle_cnt_reg; s_axis_tx_tready_next = 1'b0; @@ -465,8 +470,8 @@ always_comb begin state_next = STATE_PAYLOAD; end else begin swap_lanes_next = 1'b0; - ifg_count_next = 8'd0; - deficit_idle_count_next = 2'd0; + ifg_cnt_next = 8'd0; + deficit_idle_cnt_next = 2'd0; state_next = STATE_IDLE; end end @@ -517,8 +522,9 @@ always_comb begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; - ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_count_reg); - if (s_empty_reg <= 4) begin + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_cnt_reg); + + if (extra_cycle) begin stat_tx_byte_next = 4'(CTRL_W); state_next = STATE_FCS_2; end else begin @@ -557,27 +563,29 @@ always_comb begin crc_data_next = {24'd0, s_axis_tx.tdata} ^ {56'd0, 32'hffffffff}; + ifg_cnt_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_cnt_reg); + if (DIC_EN) begin - if (ifg_count_next > 8'd7) begin + if (ifg_cnt_next > 8'd7) begin state_next = STATE_IFG; end else begin - if (ifg_count_next >= 8'd4) begin - deficit_idle_count_next = 2'(ifg_count_next - 8'd4); + if (ifg_cnt_next >= 8'd4) begin + deficit_idle_cnt_next = 2'(ifg_cnt_next - 8'd4); swap_lanes_next = 1'b1; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; swap_lanes_next = 1'b0; end s_axis_tx_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd4) begin + if (ifg_cnt_next > 8'd4) begin state_next = STATE_IFG; end else begin s_axis_tx_tready_next = cfg_tx_enable; - swap_lanes_next = ifg_count_next != 0; + swap_lanes_next = ifg_cnt_next != 0; state_next = STATE_IDLE; end end @@ -590,7 +598,7 @@ always_comb begin xgmii_txd_next = {XGMII_TERM, {7{XGMII_ERROR}}}; xgmii_txc_next = {CTRL_W{1'b1}}; - ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; + ifg_cnt_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12; stat_tx_pkt_len_next = frame_len_reg; stat_tx_pkt_good_next = !frame_error_reg; @@ -613,33 +621,27 @@ always_comb begin crc_data_next = {24'd0, s_axis_tx.tdata} ^ {56'd0, 32'hffffffff}; - if (ifg_count_reg > 8'd8) begin - ifg_count_next = ifg_count_reg - 8'd8; - end else begin - ifg_count_next = 8'd0; - end - if (DIC_EN) begin - if (ifg_count_next > 8'd7 || frame_reg) begin + if (ifg_cnt_next > 8'd7 || frame_reg) begin state_next = STATE_IFG; end else begin - if (ifg_count_next >= 8'd4) begin - deficit_idle_count_next = 2'(ifg_count_next - 8'd4); + if (ifg_cnt_next >= 8'd4) begin + deficit_idle_cnt_next = 2'(ifg_cnt_next - 8'd4); swap_lanes_next = 1'b1; end else begin - deficit_idle_count_next = 2'(ifg_count_next); - ifg_count_next = 8'd0; + deficit_idle_cnt_next = 2'(ifg_cnt_next); + ifg_cnt_next = 8'd0; swap_lanes_next = 1'b0; end s_axis_tx_tready_next = cfg_tx_enable; state_next = STATE_IDLE; end end else begin - if (ifg_count_next > 8'd4 || frame_reg) begin + if (ifg_cnt_next > 8'd4 || frame_reg) begin state_next = STATE_IFG; end else begin s_axis_tx_tready_next = cfg_tx_enable; - swap_lanes_next = ifg_count_next != 0; + swap_lanes_next = ifg_cnt_next != 0; state_next = STATE_IDLE; end end @@ -670,9 +672,7 @@ always_ff @(posedge clk) begin frame_len_lim_last_reg <= frame_len_lim_last_next; frame_len_lim_check_reg <= frame_len_lim_check_next; ifg_cnt_reg <= ifg_cnt_next; - - ifg_count_reg <= ifg_count_next; - deficit_idle_count_reg <= deficit_idle_count_next; + deficit_idle_cnt_reg <= deficit_idle_cnt_next; s_tdata_reg <= s_tdata_next; s_empty_reg <= s_empty_next; @@ -767,13 +767,11 @@ always_ff @(posedge clk) begin if (rst) begin state_reg <= STATE_IDLE; - frame_start_reg <= 1'b0; - frame_reg <= 1'b0; - swap_lanes_reg <= 1'b0; - ifg_count_reg <= 8'd0; - deficit_idle_count_reg <= 2'd0; + frame_start_reg <= 1'b0; + frame_reg <= 1'b0; + deficit_idle_cnt_reg <= 2'd0; s_axis_tx_tready_reg <= 1'b0;