stats: Add string support to statistics collector

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/stats/taxi_stats_collect.sv

@@ -24,7 +24,11 @@ module taxi_stats_collect #
     // Base statistic ID
     parameter ID_BASE = 0,
     // Statistics counter update period (cycles)
-    parameter UPDATE_PERIOD = 1024
+    parameter UPDATE_PERIOD = 1024,
+    // Enable strings
+    parameter logic STR_EN = 1'b0,
+    // Common prefix string (8 characters)
+    parameter logic [8*8-1:0] PREFIX_STR = "BLK"
 )
 (
     input  wire logic              clk,
@@ -35,6 +39,7 @@ module taxi_stats_collect #
      */
     input  wire logic [INC_W-1:0]  stat_inc[CNT],
     input  wire logic              stat_valid[CNT] = '{CNT{1'b1}},
+    input  wire logic [8*8-1:0]    stat_str[CNT] = '{CNT{'0}},
 
     /*
      * Statistics increment output
@@ -48,6 +53,17 @@ module taxi_stats_collect #
     input  wire logic              update = 1'b0
 );
 
+// check configuration
+if (STR_EN) begin
+    if (!m_axis_stat.USER_EN)
+        $fatal(0, "Error: statistics strings requires tuser (instance %m)");
+    if (m_axis_stat.DATA_W < 16)
+        $fatal(0, "Error: statistics strings requires tdata width of at least 16 (instance %m)");
+end
+
+if (ID_BASE+CNT > 2**m_axis_stat.ID_W)
+    $fatal(0, "Error: insufficient tid width (instance %m)");
+
 localparam STAT_INC_W = m_axis_stat.DATA_W;
 localparam STAT_ID_W = m_axis_stat.ID_W;
 
@@ -63,7 +79,8 @@ logic [0:0] state_reg = STATE_READ, state_next;
 
 logic [STAT_INC_W-1:0] m_axis_stat_tdata_reg = '0, m_axis_stat_tdata_next;
 logic [STAT_ID_W-1:0] m_axis_stat_tid_reg = '0, m_axis_stat_tid_next;
-logic m_axis_stat_tvalid_reg = 0, m_axis_stat_tvalid_next;
+logic m_axis_stat_tvalid_reg = 1'b0, m_axis_stat_tvalid_next;
+logic m_axis_stat_tuser_reg = 1'b0, m_axis_stat_tuser_next;
 
 logic [CNT_W-1:0] count_reg = '0, count_next;
 logic [PERIOD_CNT_W-1:0] update_period_reg = PERIOD_CNT_W'(UPDATE_PERIOD), update_period_next;
@@ -73,6 +90,33 @@ logic update_reg = 1'b0, update_next;
 logic [CNT-1:0] update_shift_reg = '0, update_shift_next;
 logic [ACC_W-1:0] ch_reg = '0, ch_next;
 
+function automatic [8*6-1:0] pack_str(logic [8*8-1:0] str);
+    // determine length
+    integer j = 0;
+    for (integer i = 0; i < 8; i = i + 1) begin
+        if (str[i*8 +: 8] != 0) begin
+            j = i;
+        end
+    end
+
+    // convert to 6 bit and pack
+    pack_str = '0;
+    for (integer i = 0; i < 8 && i <= j; i = i + 1) begin
+        pack_str[i*6 +: 6] = {str[8*(j-i) + 6], str[8*(j-i) +: 5]};
+    end
+endfunction
+
+logic [3:0][11:0] prefix_str_rom = pack_str(PREFIX_STR);
+logic [CNT*4-1:0][11:0] str_rom;
+logic [CNT_W-1:0] str_sel_reg = '0, str_sel_next;
+logic str_prfx_reg = 1'b0, str_prfx_next;
+logic [1:0] str_ptr_reg = '0, str_ptr_next;
+logic str_update_reg = 1'b0, str_update_next;
+
+for (genvar n = 0; n < CNT; n = n + 1) begin
+    assign str_rom[n*4 +: 4] = pack_str(stat_str[n]);
+end
+
 wire [ACC_W-1:0] acc_int[CNT];
 logic [CNT-1:0] acc_clear;
 
@@ -92,7 +136,7 @@ assign m_axis_stat.tvalid = m_axis_stat_tvalid_reg;
 assign m_axis_stat.tlast = 1'b1;
 assign m_axis_stat.tid = m_axis_stat_tid_reg;
 assign m_axis_stat.tdest = '0;
-assign m_axis_stat.tuser = '0;
+assign m_axis_stat.tuser = STR_EN ? m_axis_stat_tuser_reg : '0;
 
 for (genvar n = 0; n < CNT; n = n + 1) begin : ch
     logic [ACC_W-1:0] acc_reg = '0;
@@ -124,6 +168,7 @@ always_comb begin
     m_axis_stat_tdata_next = m_axis_stat_tdata_reg;
     m_axis_stat_tid_next = m_axis_stat_tid_reg;
     m_axis_stat_tvalid_next = m_axis_stat_tvalid_reg && !m_axis_stat.tready;
+    m_axis_stat_tuser_next = m_axis_stat_tuser_reg;
 
     count_next = count_reg;
     update_period_next = update_period_reg;
@@ -133,6 +178,11 @@ always_comb begin
     update_shift_next = update_shift_reg;
     ch_next = ch_reg;
 
+    str_sel_next = str_sel_reg;
+    str_prfx_next = str_prfx_reg;
+    str_ptr_next = str_ptr_reg;
+    str_update_next = str_update_reg;
+
     acc_clear = '0;
 
     mem_rd_en = 1'b0;
@@ -162,14 +212,34 @@ always_comb begin
                 m_axis_stat_tdata_next = mem_rd_data_reg + STAT_INC_W'(ch_reg);
                 m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
                 m_axis_stat_tvalid_next = mem_rd_data_reg != 0 || ch_reg != 0;
+                m_axis_stat_tuser_next = 1'b0;
             end else begin
                 mem_wr_data = mem_rd_data_reg + STAT_INC_W'(ch_reg);
+
+                if (STR_EN && !m_axis_stat_tvalid_reg && str_update_reg && count_reg == str_sel_reg) begin
+                    str_update_next = 1'b0;
+                    m_axis_stat_tdata_next[15:4] = str_prfx_reg ? str_rom[{str_sel_reg, str_ptr_reg}] : prefix_str_rom[str_ptr_reg];
+                    m_axis_stat_tdata_next[3:0] = {1'b0, str_prfx_reg, str_ptr_reg};
+                    m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
+                    m_axis_stat_tvalid_next = 1'b1;
+                    m_axis_stat_tuser_next = 1'b1;
+                    str_ptr_next = str_ptr_reg + 1;
+                    if (str_ptr_reg == 2'b11) begin
+                        str_prfx_next = !str_prfx_reg;
+                        if (str_prfx_reg) begin
+                            str_sel_next = str_sel_reg + 1;
+                        end
+                    end
+                end
             end
 
             if (count_reg == CNT_W'(CNT-1)) begin
                 zero_next = 1'b0;
                 update_req_next = 1'b0;
                 update_next = update_req_reg;
+                if (update_req_reg) begin
+                    str_update_next = 1'b1;
+                end
                 count_next = '0;
             end else begin
                 count_next = count_reg + 1;
@@ -193,6 +263,7 @@ always_ff @(posedge clk) begin
     m_axis_stat_tdata_reg <= m_axis_stat_tdata_next;
     m_axis_stat_tid_reg <= m_axis_stat_tid_next;
     m_axis_stat_tvalid_reg <= m_axis_stat_tvalid_next;
+    m_axis_stat_tuser_reg <= m_axis_stat_tuser_next;
 
     count_reg <= count_next;
     update_period_reg <= update_period_next;
@@ -202,6 +273,11 @@ always_ff @(posedge clk) begin
     update_shift_reg <= update_shift_next;
     ch_reg <= ch_next;
 
+    str_sel_reg <= str_sel_next;
+    str_prfx_reg <= str_prfx_next;
+    str_ptr_reg <= str_ptr_next;
+    str_update_reg <= str_update_next;
+
     if (mem_wr_en) begin
         mem_reg[count_reg] <= mem_wr_data;
     end else if (mem_rd_en) begin
@@ -216,6 +292,11 @@ always_ff @(posedge clk) begin
         zero_reg <= 1'b1;
         update_req_reg <= 1'b0;
         update_reg <= 1'b0;
+
+        str_sel_reg <= '0;
+        str_prfx_reg <= 1'b0;
+        str_ptr_reg <= '0;
+        str_update_reg <= 1'b0;
     end
 end
 

tb/stats/taxi_stats_collect/Makefile

@@ -33,6 +33,8 @@ export PARAM_CNT := 8
 export PARAM_INC_W := 8
 export PARAM_ID_BASE := 0
 export PARAM_UPDATE_PERIOD := 128
+export PARAM_STR_EN := 1
+export PARAM_PREFIX_STR := "\"BLK\""
 export PARAM_STAT_INC_W := 16
 export PARAM_STAT_ID_W := $(shell python -c "print(($(PARAM_CNT)-1).bit_length())")
 

tb/stats/taxi_stats_collect/test_taxi_stats_collect.py

@@ -25,6 +25,10 @@ from cocotb.regression import TestFactory
 from cocotbext.axi import AxiStreamBus, AxiStreamSink
 
 
+def str2int(s):
+    return int.from_bytes(s.encode('utf-8'), 'big')
+
+
 class TB(object):
     def __init__(self, dut):
         self.dut = dut
@@ -39,6 +43,7 @@ class TB(object):
         for k in range(len(dut.stat_inc)):
             dut.stat_inc[k].setimmediatevalue(0)
             dut.stat_valid[k].setimmediatevalue(0)
+            dut.stat_str[k].setimmediatevalue(str2int(f"STR_{k}"))
 
         dut.gate.setimmediatevalue(1)
         dut.update.setimmediatevalue(0)
@@ -86,6 +91,7 @@ async def run_test_acc(dut, backpressure_inserter=None):
     while not tb.stat_sink.empty():
         stat = await tb.stat_sink.recv()
 
+        if not stat.tuser:
             assert stat.tdata[0] != 0
 
             data[stat.tid] += stat.tdata[0]
@@ -124,6 +130,7 @@ async def run_test_max(dut, backpressure_inserter=None):
     while not tb.stat_sink.empty():
         stat = await tb.stat_sink.recv()
 
+        if not stat.tuser:
             assert stat.tdata[0] != 0
 
             data[stat.tid] += stat.tdata[0]
@@ -137,6 +144,54 @@ async def run_test_max(dut, backpressure_inserter=None):
     await RisingEdge(dut.clk)
 
 
+async def run_test_str(dut, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    stat_count = len(dut.stat_valid)
+
+    await tb.cycle_reset()
+
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    strings = [bytearray() for x in range(stat_count)]
+    done_cnt = 0
+
+    while done_cnt < stat_count:
+        stat = await tb.stat_sink.recv()
+
+        print(stat)
+
+        val = stat.tdata[0]
+        index = stat.tid
+
+        ptr = (val & 0x7)*2
+        b = bytearray()
+        for k in range(2):
+            c = (val >> (k*6 + 4)) & 0x3f
+            if c & 0x20:
+                c = (c & 0x1f) | 0x40
+            else:
+                c = (c & 0x1f) | 0x20
+            b.append(c)
+        if len(strings[index]) == ptr:
+            strings[index].extend(b)
+
+        if ptr == 14:
+            done_cnt += 1
+
+    print(strings)
+
+    for i, s in enumerate(strings):
+        s = (s[0:8].strip() + b"." + s[8:].strip()).decode('ascii')
+        print(s)
+
+        assert s == f'BLK.STR_{i}'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
 async def run_stress_test(dut, backpressure_inserter=None):
 
     tb = TB(dut)
@@ -203,6 +258,7 @@ async def run_stress_test(dut, backpressure_inserter=None):
     while not tb.stat_sink.empty():
         stat = await tb.stat_sink.recv()
 
+        if not stat.tuser:
             assert stat.tdata[0] != 0
 
             data[stat.tid] += stat.tdata[0]
@@ -224,6 +280,7 @@ if cocotb.SIM_NAME:
     for test in [
                 run_test_acc,
                 run_test_max,
+                run_test_str,
                 run_stress_test,
             ]:
 
@@ -270,6 +327,8 @@ def test_taxi_stats_collect(request):
     parameters['INC_W'] = 8
     parameters['ID_BASE'] = 0
     parameters['UPDATE_PERIOD'] = 128
+    parameters['STR_EN'] = 1
+    parameters['PREFIX_STR'] = "\"BLK\""
     parameters['STAT_INC_W'] = 16
     parameters['STAT_ID_W'] = (parameters['CNT']-1).bit_length()
 

tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv

@@ -22,6 +22,8 @@ module test_taxi_stats_collect #
     parameter INC_W = 8,
     parameter ID_BASE = 0,
     parameter UPDATE_PERIOD = 128,
+    parameter logic STR_EN = 1'b1,
+    parameter logic [8*8-1:0] PREFIX_STR = "BLK",
     parameter STAT_INC_W = 16,
     parameter STAT_ID_W = $clog2(CNT)
     /* verilator lint_on WIDTHTRUNC */
@@ -33,13 +35,16 @@ logic rst;
 
 logic [INC_W-1:0] stat_inc[CNT];
 logic [0:0] stat_valid[CNT];
+logic [8*8-1:0] stat_str[CNT];
 
 taxi_axis_if #(
     .DATA_W(STAT_INC_W),
     .KEEP_EN(0),
     .KEEP_W(1),
     .ID_EN(1),
-    .ID_W(STAT_ID_W)
+    .ID_W(STAT_ID_W),
+    .USER_EN(1),
+    .USER_W(1)
 ) m_axis_stat();
 
 logic gate;
@@ -49,7 +54,9 @@ taxi_stats_collect #(
     .CNT(CNT),
     .INC_W(INC_W),
     .ID_BASE(ID_BASE),
-    .UPDATE_PERIOD(UPDATE_PERIOD)
+    .UPDATE_PERIOD(UPDATE_PERIOD),
+    .STR_EN(STR_EN),
+    .PREFIX_STR(PREFIX_STR)
 )
 uut (
     .clk(clk),
@@ -60,6 +67,7 @@ uut (
      */
     .stat_inc(stat_inc),
     .stat_valid(stat_valid),
+    .stat_str(stat_str),
 
     /*
      * Statistics increment output