eth: Add 1G Ethernet MAC module with FIFOs and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-09 17:08:38 -08:00 · 2025-02-11 22:12:57 -08:00
parent 8f8572bdee
commit 04b73e7ddf
5 changed files with 947 additions and 0 deletions
--- a/tb/eth/taxi_eth_mac_1g_fifo/Makefile
+++ b/tb/eth/taxi_eth_mac_1g_fifo/Makefile
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_eth_mac_1g_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_AXIS_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
--- a/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py
+++ b/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py
@@ -0,0 +1,273 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self._enable_generator_rx = None
+        self._enable_generator_tx = None
+        self._enable_cr_rx = None
+        self._enable_cr_tx = None
+
+        cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.rx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, 8, units="ns").start())
+
+        self.gmii_source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
+            dut.rx_clk, dut.rx_rst, dut.rx_clk_enable, dut.rx_mii_select)
+        self.gmii_sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en,
+            dut.tx_clk, dut.tx_rst, dut.tx_clk_enable, dut.tx_mii_select)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        dut.rx_clk_enable.setimmediatevalue(1)
+        dut.tx_clk_enable.setimmediatevalue(1)
+        dut.rx_mii_select.setimmediatevalue(0)
+        dut.tx_mii_select.setimmediatevalue(0)
+        dut.cfg_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+
+    def set_enable_generator_rx(self, generator=None):
+        if self._enable_cr_rx is not None:
+            self._enable_cr_rx.kill()
+            self._enable_cr_rx = None
+
+        self._enable_generator_rx = generator
+
+        if self._enable_generator_rx is not None:
+            self._enable_cr_rx = cocotb.start_soon(self._run_enable_rx())
+
+    def set_enable_generator_tx(self, generator=None):
+        if self._enable_cr_tx is not None:
+            self._enable_cr_tx.kill()
+            self._enable_cr_tx = None
+
+        self._enable_generator_tx = generator
+
+        if self._enable_generator_tx is not None:
+            self._enable_cr_tx = cocotb.start_soon(self._run_enable_tx())
+
+    def clear_enable_generator_rx(self):
+        self.set_enable_generator_rx(None)
+
+    def clear_enable_generator_tx(self):
+        self.set_enable_generator_tx(None)
+
+    async def _run_enable_rx(self):
+        for val in self._enable_generator_rx:
+            self.dut.rx_clk_enable.value = val
+            await RisingEdge(self.dut.rx_clk)
+
+    async def _run_enable_tx(self):
+        for val in self._enable_generator_tx:
+            self.dut.tx_clk_enable.value = val
+            await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data)
+        await tb.gmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert rx_frame.tuser == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.gmii_sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("enable_gen", [None, cycle_en])
+        factory.add_option("mii_sel", [False, True])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_mac_1g_fifo(request):
+    dut = "taxi_eth_mac_1g_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "eth", f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 8
+    parameters['AXIS_DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
--- a/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv
+++ b/tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_1g_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter TX_TAG_W = 16,
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+logic logic_clk;
+logic logic_rst;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+logic [DATA_W-1:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic rx_clk_enable;
+logic tx_clk_enable;
+logic rx_mii_select;
+logic tx_mii_select;
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+
+logic [7:0] cfg_ifg;
+logic cfg_tx_enable;
+logic cfg_rx_enable;
+
+taxi_eth_mac_1g_fifo #(
+    .DATA_W(DATA_W),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * Control
+     */
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(cfg_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall