diff --git a/src/lss/rtl/taxi_i2c_init.sv b/src/lss/rtl/taxi_i2c_init.sv index ff056aa..c2a074c 100644 --- a/src/lss/rtl/taxi_i2c_init.sv +++ b/src/lss/rtl/taxi_i2c_init.sv @@ -189,14 +189,15 @@ initial begin init_data[21] = cmd_halt(); // halt end -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_RUN = 3'd1, - STATE_TABLE_1 = 3'd2, - STATE_TABLE_2 = 3'd3, - STATE_TABLE_3 = 3'd4; +typedef enum logic [2:0] { + STATE_IDLE, + STATE_RUN, + STATE_TABLE_1, + STATE_TABLE_2, + STATE_TABLE_3 +} state_t; -logic [2:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; localparam AW = $clog2(INIT_DATA_LEN); diff --git a/src/lss/rtl/taxi_i2c_master.sv b/src/lss/rtl/taxi_i2c_master.sv index 63ba8bd..2e5269a 100644 --- a/src/lss/rtl/taxi_i2c_master.sv +++ b/src/lss/rtl/taxi_i2c_master.sv @@ -158,41 +158,43 @@ if (s_axis_cmd.DATA_W < 12) if (s_axis_tx.DATA_W != 8 || m_axis_rx.DATA_W != 8) $fatal(0, "Data interface width must be 8 bits (instance %m)"); -localparam [3:0] - STATE_IDLE = 4'd0, - STATE_ACTIVE_WRITE = 4'd1, - STATE_ACTIVE_READ = 4'd2, - STATE_START_WAIT = 4'd3, - STATE_START = 4'd4, - STATE_ADDRESS_1 = 4'd5, - STATE_ADDRESS_2 = 4'd6, - STATE_WRITE_1 = 4'd7, - STATE_WRITE_2 = 4'd8, - STATE_WRITE_3 = 4'd9, - STATE_READ = 4'd10, - STATE_STOP = 4'd11; +typedef enum logic [3:0] { + STATE_IDLE, + STATE_ACTIVE_WRITE, + STATE_ACTIVE_READ, + STATE_START_WAIT, + STATE_START, + STATE_ADDRESS_1, + STATE_ADDRESS_2, + STATE_WRITE_1, + STATE_WRITE_2, + STATE_WRITE_3, + STATE_READ, + STATE_STOP +} state_t; -logic [3:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; -localparam [3:0] - PHY_STATE_IDLE = 4'd0, - PHY_STATE_ACTIVE = 4'd1, - PHY_STATE_REPEATED_START_1 = 4'd2, - PHY_STATE_REPEATED_START_2 = 4'd3, - PHY_STATE_START_1 = 4'd4, - PHY_STATE_START_2 = 4'd5, - PHY_STATE_WRITE_BIT_1 = 4'd6, - PHY_STATE_WRITE_BIT_2 = 4'd7, - PHY_STATE_WRITE_BIT_3 = 4'd8, - PHY_STATE_READ_BIT_1 = 4'd9, - PHY_STATE_READ_BIT_2 = 4'd10, - PHY_STATE_READ_BIT_3 = 4'd11, - PHY_STATE_READ_BIT_4 = 4'd12, - PHY_STATE_STOP_1 = 4'd13, - PHY_STATE_STOP_2 = 4'd14, - PHY_STATE_STOP_3 = 4'd15; +typedef enum logic [3:0] { + PHY_STATE_IDLE, + PHY_STATE_ACTIVE, + PHY_STATE_REPEATED_START_1, + PHY_STATE_REPEATED_START_2, + PHY_STATE_START_1, + PHY_STATE_START_2, + PHY_STATE_WRITE_BIT_1, + PHY_STATE_WRITE_BIT_2, + PHY_STATE_WRITE_BIT_3, + PHY_STATE_READ_BIT_1, + PHY_STATE_READ_BIT_2, + PHY_STATE_READ_BIT_3, + PHY_STATE_READ_BIT_4, + PHY_STATE_STOP_1, + PHY_STATE_STOP_2, + PHY_STATE_STOP_3 +} phy_state_t; -logic [3:0] phy_state_reg = STATE_IDLE, phy_state_next; +phy_state_t phy_state_reg = PHY_STATE_IDLE, phy_state_next; logic phy_start_bit; logic phy_stop_bit; @@ -359,7 +361,7 @@ always_comb begin mode_stop_next = s_axis_cmd_stop; s_axis_cmd_ready_next = 1'b0; - + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin // address or mode mismatch or forced start - repeated start @@ -406,7 +408,7 @@ always_comb begin mode_stop_next = s_axis_cmd_stop; s_axis_cmd_ready_next = 1'b0; - + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin // address or mode mismatch or forced start - repeated start diff --git a/src/lss/rtl/taxi_i2c_single_reg.sv b/src/lss/rtl/taxi_i2c_single_reg.sv index 2beea4d..e5ba527 100644 --- a/src/lss/rtl/taxi_i2c_single_reg.sv +++ b/src/lss/rtl/taxi_i2c_single_reg.sv @@ -39,17 +39,18 @@ module taxi_i2c_single_reg #( output wire logic [7:0] data_out ); -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_ADDRESS = 3'd1, - STATE_ACK = 3'd2, - STATE_WRITE_1 = 3'd3, - STATE_WRITE_2 = 3'd4, - STATE_READ_1 = 3'd5, - STATE_READ_2 = 3'd6, - STATE_READ_3 = 3'd7; +typedef enum logic [2:0] { + STATE_IDLE, + STATE_ADDRESS, + STATE_ACK, + STATE_WRITE_1, + STATE_WRITE_2, + STATE_READ_1, + STATE_READ_2, + STATE_READ_3 +} state_t; -logic [2:0] state_reg = STATE_IDLE; +state_t state_reg = STATE_IDLE; logic [7:0] data_reg = '0; logic [7:0] shift_reg = '0; diff --git a/src/lss/rtl/taxi_i2c_slave.sv b/src/lss/rtl/taxi_i2c_slave.sv index 1eceb4a..2868e46 100644 --- a/src/lss/rtl/taxi_i2c_slave.sv +++ b/src/lss/rtl/taxi_i2c_slave.sv @@ -75,7 +75,7 @@ This module translates I2C read and write operations into AXI stream transfers. Bytes written over I2C will be delayed by one byte time so that the last byte in a write operation can be accurately marked. When reading, the module will stretch SCL by holding it low until a data byte is presented at the AXI stream -input. +input. Control: @@ -139,17 +139,18 @@ I/O pin. This would prevent devices from stretching the clock period. if (s_axis_tx.DATA_W != 8 || m_axis_rx.DATA_W != 8) $fatal(0, "Data interface width must be 8 bits (instance %m)"); -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_ADDRESS = 3'd1, - STATE_ACK = 3'd2, - STATE_WRITE_1 = 3'd3, - STATE_WRITE_2 = 3'd4, - STATE_READ_1 = 3'd5, - STATE_READ_2 = 3'd6, - STATE_READ_3 = 3'd7; +typedef enum logic [2:0] { + STATE_IDLE, + STATE_ADDRESS, + STATE_ACK, + STATE_WRITE_1, + STATE_WRITE_2, + STATE_READ_1, + STATE_READ_2, + STATE_READ_3 +} state_t; -logic [2:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; logic [6:0] addr_reg = '0, addr_next; logic [7:0] data_reg = '0, data_next; diff --git a/src/lss/rtl/taxi_i2c_slave_apb_master.sv b/src/lss/rtl/taxi_i2c_slave_apb_master.sv index 9ce9547..8188eba 100644 --- a/src/lss/rtl/taxi_i2c_slave_apb_master.sv +++ b/src/lss/rtl/taxi_i2c_slave_apb_master.sv @@ -178,15 +178,16 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES) if (8*2**$clog2(BYTE_SIZE/8) != BYTE_SIZE) $fatal(0, "Error: AXI word size must be a power of two multiple of 8 bits (instance %m)"); -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_ADDRESS = 3'd1, - STATE_READ_1 = 3'd2, - STATE_READ_2 = 3'd3, - STATE_WRITE_1 = 3'd4, - STATE_WRITE_2 = 3'd5; +typedef enum logic [2:0] { + STATE_IDLE, + STATE_ADDRESS, + STATE_READ_1, + STATE_READ_2, + STATE_WRITE_1, + STATE_WRITE_2 +} state_t; -logic [2:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; logic [7:0] count_reg = '0, count_next; logic last_cycle_reg = 1'b0; diff --git a/src/lss/rtl/taxi_i2c_slave_axil_master.sv b/src/lss/rtl/taxi_i2c_slave_axil_master.sv index 0cef161..0ac642a 100644 --- a/src/lss/rtl/taxi_i2c_slave_axil_master.sv +++ b/src/lss/rtl/taxi_i2c_slave_axil_master.sv @@ -181,15 +181,16 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES) if (8*2**$clog2(BYTE_SIZE/8) != BYTE_SIZE) $fatal(0, "Error: AXI word size must be a power of two multiple of 8 bits (instance %m)"); -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_ADDRESS = 3'd1, - STATE_READ_1 = 3'd2, - STATE_READ_2 = 3'd3, - STATE_WRITE_1 = 3'd4, - STATE_WRITE_2 = 3'd5; +typedef enum logic [2:0] { + STATE_IDLE, + STATE_ADDRESS, + STATE_READ_1, + STATE_READ_2, + STATE_WRITE_1, + STATE_WRITE_2 +} state_t; -logic [2:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; logic [7:0] count_reg = '0, count_next; logic last_cycle_reg = 1'b0; diff --git a/src/lss/rtl/taxi_mdio_master.sv b/src/lss/rtl/taxi_mdio_master.sv index 8f3b52a..a5c3e90 100644 --- a/src/lss/rtl/taxi_mdio_master.sv +++ b/src/lss/rtl/taxi_mdio_master.sv @@ -44,12 +44,13 @@ module taxi_mdio_master ( input wire logic [7:0] prescale ); -localparam [1:0] - STATE_IDLE = 2'd0, - STATE_PREAMBLE = 2'd1, - STATE_TRANSFER = 2'd2; +typedef enum logic [1:0] { + STATE_IDLE, + STATE_PREAMBLE, + STATE_TRANSFER +} state_t; -logic [1:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; logic [7:0] count_reg = '0, count_next; logic [5:0] bit_count_reg = '0, bit_count_next;