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axi: Makefile parameter cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-11 20:31:24 -08:00
parent cbbad58efb
commit 0a4da49c74
3 changed files with 6 additions and 6 deletions
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4
src/axi/tb/taxi_axi_interconnect/Makefile
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@@ -31,9 +31,9 @@ process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f)
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
REG_TYPE ?= 1
# module parameters # module parameters
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
export PARAM_DATA_W := 32 export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32 export PARAM_ADDR_W := 32
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )

4
src/axi/tb/taxi_axil_crossbar/Makefile
View File

@@ -31,9 +31,9 @@ process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f)
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
REG_TYPE ?= 1
# module parameters # module parameters
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
export PARAM_DATA_W := 32 export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32 export PARAM_ADDR_W := 32
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )

4
src/axi/tb/taxi_axil_interconnect/Makefile
View File

@@ -31,9 +31,9 @@ process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f)
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
REG_TYPE ?= 1
# module parameters # module parameters
export PARAM_S_COUNT := 4
export PARAM_M_COUNT := 4
export PARAM_DATA_W := 32 export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32 export PARAM_ADDR_W := 32
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )