eth: Add 10G Ethernet MAC module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/eth/taxi_eth_mac_10g/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_eth_mac_10g
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_KEEP_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py

@@ -0,0 +1,754 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import struct
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if len(dut.xgmii_txd) == 64:
+            self.clk_period = 6.4
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
+
+        self.xgmii_source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
+        self.xgmii_sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.cfg_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.xgmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.xgmii_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < 0.01
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
+
+    dic_en = int(cocotb.top.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.axis_source.width // 8
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.tx_clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+        for test_data in test_frames:
+            rx_frame = await tb.xgmii_sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if dic_en:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.tx_clk)
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(64*16 // tb.axis_source.width):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.xgmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.xgmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.xgmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.xgmii_source.send(test_frame)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.xgmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+    dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.xgmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.xgmii_source.send(test_frame)
+
+    for i in range(8):
+        for k in range(200):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.xgmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt == 9
+
+    assert tb.axis_sink.empty()
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12, 0])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_tx_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
+@pytest.mark.parametrize("data_w", [32, 64])
+def test_taxi_eth_mac_10g(request, data_w, dic_en, pfc_en):
+    dut = "taxi_eth_mac_10g"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "eth", f"{dut}.f"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['KEEP_W'] = parameters['DATA_W'] // 8
+    parameters['CTRL_W'] = parameters['DATA_W'] // 8
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv

@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC testbench
+ */
+module test_taxi_eth_mac_10g #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter KEEP_W = (DATA_W/8),
+    parameter CTRL_W = (DATA_W/8),
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] xgmii_rxd;
+logic [CTRL_W-1:0] xgmii_rxc;
+logic [DATA_W-1:0] xgmii_txd;
+logic [CTRL_W-1:0] xgmii_txc;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic [1:0] tx_start_packet;
+logic tx_error_underflow;
+logic [1:0] rx_start_packet;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [7:0] cfg_ifg;
+logic cfg_tx_enable;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [8*16-1:0] cfg_tx_pfc_quanta;
+logic [8*16-1:0] cfg_tx_pfc_refresh;
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_10g #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * XGMII interface
+     */
+    .xgmii_rxd(xgmii_rxd),
+    .xgmii_rxc(xgmii_rxc),
+    .xgmii_txd(xgmii_txd),
+    .xgmii_txc(xgmii_txc),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .tx_error_underflow(tx_error_underflow),
+    .rx_start_packet(rx_start_packet),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(cfg_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall