From 0fe56c53904404f7a91006045432a5f7475486cd Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 5 Nov 2025 23:42:03 -0800 Subject: [PATCH] eth: Update Alveo example design to use 32-bit MACs at 10G Signed-off-by: Alex Forencich --- .../example/Alveo/fpga/fpga_AU200/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU200/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU200_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU200_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU250/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU250/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU250_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU250_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU280/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU280/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU280_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU280_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU45N/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU45N/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU45N_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU45N_10g/config.tcl | 22 ++++++++++++++++++ src/eth/example/Alveo/fpga/fpga_AU50/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU50/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU50_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU50_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU55C/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU55C/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU55C_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU55C_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_AU55N/Makefile | 2 +- .../example/Alveo/fpga/fpga_AU55N/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_AU55N_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_AU55N_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_VCU1525/Makefile | 2 +- .../Alveo/fpga/fpga_VCU1525/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_VCU1525_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_VCU1525_10g/config.tcl | 22 ++++++++++++++++++ .../example/Alveo/fpga/fpga_X3522/Makefile | 2 +- .../example/Alveo/fpga/fpga_X3522/config.tcl | 22 ++++++++++++++++++ .../Alveo/fpga/fpga_X3522_10g/Makefile | 4 ++-- .../Alveo/fpga/fpga_X3522_10g/config.tcl | 22 ++++++++++++++++++ src/eth/example/Alveo/fpga/rtl/fpga_au200.sv | 14 +++++++++-- src/eth/example/Alveo/fpga/rtl/fpga_au280.sv | 14 +++++++++-- src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv | 15 ++++++++++-- src/eth/example/Alveo/fpga/rtl/fpga_au50.sv | 15 ++++++++++-- src/eth/example/Alveo/fpga/rtl/fpga_au55.sv | 15 ++++++++++-- src/eth/example/Alveo/fpga/rtl/fpga_core.sv | 20 ++++++++++++---- src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv | 15 ++++++++++-- .../example/Alveo/fpga/tb/fpga_core/Makefile | 3 +++ .../Alveo/fpga/tb/fpga_core/test_fpga_core.py | 23 +++++++++++++++---- 45 files changed, 535 insertions(+), 49 deletions(-) create mode 100644 src/eth/example/Alveo/fpga/fpga_AU200/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU200_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU250/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU250_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU280/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU280_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU45N/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU45N_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU50/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU50_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU55C/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU55C_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU55N/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_AU55N_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_VCU1525/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_VCU1525_10g/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_X3522/config.tcl create mode 100644 src/eth/example/Alveo/fpga/fpga_X3522_10g/config.tcl diff --git a/src/eth/example/Alveo/fpga/fpga_AU200/Makefile b/src/eth/example/Alveo/fpga/fpga_AU200/Makefile index ccd64d3..a001d9b 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU200/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU200/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU200/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU200/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU200/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile index c652db3..bcff29f 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU200_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU200_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU200_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU250/Makefile b/src/eth/example/Alveo/fpga/fpga_AU250/Makefile index 66be138..a339755 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU250/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU250/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU250/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU250/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU250/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile index 3c73cce..67a60b5 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU250_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU250_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU250_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU280/Makefile b/src/eth/example/Alveo/fpga/fpga_AU280/Makefile index 0992342..fa93db3 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU280/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU280/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU280/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU280/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU280/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile index 0992342..5f3bcd7 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU280_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU280_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU280_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile b/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile index e424989..712aaf9 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU45N/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU45N/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU45N/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU45N/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile index c689380..baa16ca 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU45N_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU45N_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU50/Makefile b/src/eth/example/Alveo/fpga/fpga_AU50/Makefile index 9e60ac0..585ca0d 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU50/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU50/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU50/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU50/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU50/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile index 9febd53..e874758 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU50_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU50_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU50_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile index dfc500b..085bb45 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55C/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU55C/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU55C/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU55C/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile index 1ac4968..04d2e06 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU55C_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU55C_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile index f59ca7b..655d2f0 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55N/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU55N/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU55N/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU55N/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile index c221757..8f3114d 100644 --- a/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_AU55N_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_AU55N_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile b/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile index c953c67..07beb0f 100644 --- a/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_VCU1525/config.tcl b/src/eth/example/Alveo/fpga/fpga_VCU1525/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile index 63f7863..3644cc2 100644 --- a/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_VCU1525_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_X3522/Makefile b/src/eth/example/Alveo/fpga/fpga_X3522/Makefile index c7d3301..e9e515c 100644 --- a/src/eth/example/Alveo/fpga/fpga_X3522/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_X3522/Makefile @@ -38,7 +38,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_X3522/config.tcl b/src/eth/example/Alveo/fpga/fpga_X3522/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_X3522/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile b/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile index 8fe3563..40bbd74 100644 --- a/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile +++ b/src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile @@ -35,10 +35,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -#CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/Alveo/fpga/fpga_X3522_10g/config.tcl b/src/eth/example/Alveo/fpga/fpga_X3522_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/Alveo/fpga/fpga_X3522_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv index 5541c8a..b5e4412 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv @@ -17,9 +17,16 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -255,7 +262,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv index 72c578b..bebd73f 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv @@ -17,9 +17,16 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -218,7 +225,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv index d28e962..bd2cf2e 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv @@ -17,11 +17,19 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter QSFP_CNT = 2, - parameter UART_CNT = 1 + parameter UART_CNT = 1, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -198,7 +206,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv index d25789a..407d31e 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv @@ -17,11 +17,19 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter QSFP_CNT = 1, - parameter UART_CNT = 3 + parameter UART_CNT = 3, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -193,7 +201,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv index 9f73e12..255f586 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv @@ -17,11 +17,19 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter QSFP_CNT = 2, - parameter UART_CNT = 3 + parameter UART_CNT = 3, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -210,7 +218,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index cc68b01..b11b1a1 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -17,9 +17,13 @@ Authors: */ module fpga_core # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter SW_CNT = 4, parameter LED_CNT = 3, parameter UART_CNT = 1, @@ -27,7 +31,11 @@ module fpga_core # parameter PORT_LED_CNT = PORT_CNT, parameter GTY_QUAD_CNT = PORT_CNT, parameter GTY_CNT = GTY_QUAD_CNT*4, - parameter GTY_CLK_CNT = GTY_QUAD_CNT + parameter GTY_CLK_CNT = GTY_QUAD_CNT, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -223,12 +231,12 @@ assign eth_port_lpmode = '0; wire eth_gty_tx_clk[GTY_CNT]; wire eth_gty_tx_rst[GTY_CNT]; -taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT](); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT](); wire eth_gty_rx_clk[GTY_CNT]; wire eth_gty_rx_rst[GTY_CNT]; -taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); wire eth_gty_rx_status[GTY_CNT]; @@ -300,12 +308,14 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .CNT(CNT), // GT config - .CFG_LOW_LATENCY(1), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), // GT type .GT_TYPE("GTY"), - // PHY parameters + // MAC/PHY config + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), .PADDING_EN(1'b1), .DIC_EN(1'b1), .MIN_FRAME_LEN(64), diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv b/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv index 675727a..581e647 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv @@ -17,11 +17,19 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter PORT_CNT = 4, - parameter UART_CNT = 1 + parameter UART_CNT = 1, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -195,7 +203,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile b/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile index 0e4ed6d..5f303d5 100644 --- a/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/Makefile @@ -50,6 +50,9 @@ export PARAM_PORT_LED_CNT := $(PARAM_PORT_CNT) export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT) export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) ))) export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT) +export PARAM_CFG_LOW_LATENCY := "1'b1" +export PARAM_COMBINED_MAC_PCS := "1'b1" +export PARAM_MAC_DATA_W := "64" ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index 3094c4a..a30fded 100644 --- a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -56,12 +56,20 @@ class TB: for ch in inst.mac_inst.ch: gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) @@ -116,6 +124,8 @@ async def mac_test(tb, source, sink): for k in range(1200): await RisingEdge(tb.dut.clk_125mhz) + sink.clear() + tb.log.info("Multiple small packets") count = 64 @@ -226,6 +236,9 @@ def test_fpga_core(request): parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT'] parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4 parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT'] + parameters['CFG_LOW_LATENCY'] = "1'b1" + parameters['COMBINED_MAC_PCS'] = "1'b1" + parameters['MAC_DATA_W'] = 64 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}