mirror of
https://github.com/fpganinja/taxi.git
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axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
64
tb/axi/taxi_axil_register/Makefile
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64
tb/axi/taxi_axil_register/Makefile
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@@ -0,0 +1,64 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_axil_register
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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REG_TYPE ?= 1
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# module parameters
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export PARAM_DATA_W := 32
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export PARAM_ADDR_W := 32
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export PARAM_AWUSER_EN := 0
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export PARAM_AWUSER_W := 1
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export PARAM_WUSER_EN := 0
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export PARAM_WUSER_W := 1
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export PARAM_BUSER_EN := 0
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export PARAM_BUSER_W := 1
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export PARAM_ARUSER_EN := 0
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export PARAM_ARUSER_W := 1
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export PARAM_RUSER_EN := 0
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export PARAM_RUSER_W := 1
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export PARAM_AW_REG_TYPE := $(REG_TYPE)
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export PARAM_W_REG_TYPE := $(REG_TYPE)
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export PARAM_B_REG_TYPE := $(REG_TYPE)
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export PARAM_AR_REG_TYPE := $(REG_TYPE)
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export PARAM_R_REG_TYPE := $(REG_TYPE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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243
tb/axi/taxi_axil_register/test_taxi_axil_register.py
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243
tb/axi/taxi_axil_register/test_taxi_axil_register.py
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@@ -0,0 +1,243 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
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self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
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def set_idle_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.aw_channel.set_pause_generator(generator())
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self.axil_master.write_if.w_channel.set_pause_generator(generator())
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self.axil_master.read_if.ar_channel.set_pause_generator(generator())
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self.axil_ram.write_if.b_channel.set_pause_generator(generator())
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self.axil_ram.read_if.r_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.b_channel.set_pause_generator(generator())
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self.axil_master.read_if.r_channel.set_pause_generator(generator())
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self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
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self.axil_ram.write_if.w_channel.set_pause_generator(generator())
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self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
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await tb.axil_master.write(addr, test_data)
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tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
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assert tb.axil_ram.read(addr, length) == test_data
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assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
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assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axil_ram.write(addr, test_data)
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data = await tb.axil_master.read(addr, length)
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assert data.data == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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async def worker(master, offset, aperture, count=16):
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for k in range(count):
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length = random.randint(1, min(32, aperture))
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addr = offset+random.randint(0, aperture-length)
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test_data = bytearray([x % 256 for x in range(length)])
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await Timer(random.randint(1, 100), 'ns')
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await master.write(addr, test_data)
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await Timer(random.randint(1, 100), 'ns')
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data = await master.read(addr, length)
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assert data.data == test_data
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workers = []
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for k in range(16):
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workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
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while workers:
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await workers.pop(0)
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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for test in [run_test_write, run_test_read, run_stress_test]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("reg_type", [0, 1, 2])
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@pytest.mark.parametrize("data_w", [8, 16, 32])
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def test_taxi_axil_register(request, data_w, reg_type):
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dut = "taxi_axil_register"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "axi", f"{dut}.f"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['DATA_W'] = data_w
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parameters['ADDR_W'] = 32
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parameters['AWUSER_EN'] = 0
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parameters['AWUSER_W'] = 1
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parameters['WUSER_EN'] = 0
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parameters['WUSER_W'] = 1
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parameters['BUSER_EN'] = 0
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parameters['BUSER_W'] = 1
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parameters['ARUSER_EN'] = 0
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parameters['ARUSER_W'] = 1
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parameters['RUSER_EN'] = 0
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parameters['RUSER_W'] = 1
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parameters['AW_REG_TYPE'] = reg_type
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parameters['W_REG_TYPE'] = reg_type
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parameters['B_REG_TYPE'] = reg_type
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parameters['AR_REG_TYPE'] = reg_type
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parameters['R_REG_TYPE'] = reg_type
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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86
tb/axi/taxi_axil_register/test_taxi_axil_register.sv
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86
tb/axi/taxi_axil_register/test_taxi_axil_register.sv
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@@ -0,0 +1,86 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite register testbench
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*/
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module test_taxi_axil_register #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter DATA_W = 32,
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parameter ADDR_W = 32,
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parameter logic AWUSER_EN = 1'b0,
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parameter AWUSER_W = 1,
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parameter logic WUSER_EN = 1'b0,
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parameter WUSER_W = 1,
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parameter logic BUSER_EN = 1'b0,
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parameter BUSER_W = 1,
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parameter logic ARUSER_EN = 1'b0,
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parameter ARUSER_W = 1,
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parameter logic RUSER_EN = 1'b0,
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parameter RUSER_W = 1,
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parameter AW_REG_TYPE = 1,
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parameter W_REG_TYPE = 1,
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parameter B_REG_TYPE = 1,
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parameter AR_REG_TYPE = 1,
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parameter R_REG_TYPE = 1
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axil_if #(
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.DATA_W(DATA_W),
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.ADDR_W(ADDR_W),
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.AWUSER_EN(AWUSER_EN),
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.AWUSER_W(AWUSER_W),
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.WUSER_EN(WUSER_EN),
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.WUSER_W(WUSER_W),
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.BUSER_EN(BUSER_EN),
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.BUSER_W(BUSER_W),
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.ARUSER_EN(ARUSER_EN),
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.ARUSER_W(ARUSER_W),
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.RUSER_EN(RUSER_EN),
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.RUSER_W(RUSER_W)
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) s_axil(), m_axil();
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taxi_axil_register #(
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.AW_REG_TYPE(AW_REG_TYPE),
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.W_REG_TYPE(W_REG_TYPE),
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.B_REG_TYPE(B_REG_TYPE),
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.AR_REG_TYPE(AR_REG_TYPE),
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.R_REG_TYPE(R_REG_TYPE)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Lite slave interface
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*/
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.s_axil_wr(s_axil),
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.s_axil_rd(s_axil),
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/*
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* AXI4-Lite master interface
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*/
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.m_axil_wr(m_axil),
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.m_axil_rd(m_axil)
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);
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endmodule
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`resetall
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