bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

Update readme

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-16 22:22:43 -08:00
parent 94dba88560
commit 1112545d0a
1 changed files with 21 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
README.md
View File

@@ -36,6 +36,12 @@ To facilitate the dual-license model, contributions to the project can only be a
* Pipeline register * Pipeline register
* Pipeline FIFO * Pipeline FIFO
* Ethernet * Ethernet
* 10/100 MII MAC
* 10/100 MII MAC + FIFO
* 10/100/1000 GMII MAC
* 10/100/1000 GMII MAC + FIFO
* 10/100/1000 RGMII MAC
* 10/100/1000 RGMII MAC + FIFO
* 1G MAC * 1G MAC
* 1G MAC + FIFO * 1G MAC + FIFO
* 10G MAC * 10G MAC
@@ -43,6 +49,21 @@ To facilitate the dual-license model, contributions to the project can only be a
* 10G MAC/PHY * 10G MAC/PHY
* 10G MAC/PHY + FIFO * 10G MAC/PHY + FIFO
* 10G PHY * 10G PHY
* MII PHY interface
* GMII PHY interface
* RGMII PHY interface
* General input/output
* Switch debouncer
* Generic IDDR
* Generic ODDR
* Source-synchronous DDR input
* Source-synchronous DDR differential input
* Source-synchronous DDR output
* Source-synchronous DDR differential output
* Source-synchronous SDR input
* Source-synchronous SDR differential input
* Source-synchronous SDR output
* Source-synchronous SDR differential output
* Linear-feedback shift register * Linear-feedback shift register
* Parametrizable combinatorial LFSR/CRC module * Parametrizable combinatorial LFSR/CRC module
* CRC computation module * CRC computation module