docs: Add sphinx infrastructure

Signed-off-by: Alex Forencich <alex@alexforencich.com>

docs/source/glossary.rst

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+.. _glossary:
+
+========
+Glossary
+========
+
+.. glossary::
+    
+    AXI
+        Advanced eXtensible Interface
+
+    BAR
+        Base Address Register
+
+    CDC
+        Clock Domain Crossing
+
+    CRC
+        Cyclic Redundancy Check
+
+    DMA
+        Direct Memory Access
+
+    FPGA
+        Field-Programmable Gate Array
+
+    I2C
+        Inter-Intergrated Circuit
+
+    JTAG
+        Joint Test Action Group
+
+    LFSR
+        Linear Feedback Shift Register
+
+    MAC
+        Media Access Control(ler)
+
+    MSI
+        Message-Signaled Interrupt
+
+    NIC
+        Network Interface Controller
+
+    PCI
+        Peripheral Component Interconnect
+
+    PCIe
+        PCI Express
+
+    PHY
+        PHYsical layer (interface)
+
+    PRBS
+        Pseudorandom Binary Sequence
+
+    PTP
+        Precision Time Protocol (IEEE 1588)
+
+    RSS
+        Receive Side Scaling
+
+    UART
+        Universal Asynchronous Receiver/Transmitter