From 1530f8cecf08becb9dfc93a79371c4c77a8d4c0d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 27 Feb 2026 17:11:30 -0800 Subject: [PATCH] axis: Use SV enums in AXI stream components Signed-off-by: Alex Forencich --- src/axis/rtl/taxi_axis_cobs_decode.sv | 11 ++++++----- src/axis/rtl/taxi_axis_cobs_encode.sv | 22 ++++++++++++---------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/axis/rtl/taxi_axis_cobs_decode.sv b/src/axis/rtl/taxi_axis_cobs_decode.sv index c752055..251b043 100644 --- a/src/axis/rtl/taxi_axis_cobs_decode.sv +++ b/src/axis/rtl/taxi_axis_cobs_decode.sv @@ -36,12 +36,13 @@ if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8) $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); // state register -localparam [1:0] - STATE_IDLE = 2'd0, - STATE_SEGMENT = 2'd1, - STATE_NEXT_SEGMENT = 2'd2; +typedef enum logic [1:0] { + STATE_IDLE, + STATE_SEGMENT, + STATE_NEXT_SEGMENT +} state_t; -logic [1:0] state_reg = STATE_IDLE, state_next; +state_t state_reg = STATE_IDLE, state_next; logic [7:0] count_reg = 8'd0, count_next; logic suppress_zero_reg = 1'b0, suppress_zero_next; diff --git a/src/axis/rtl/taxi_axis_cobs_encode.sv b/src/axis/rtl/taxi_axis_cobs_encode.sv index f425b1a..cb033e6 100644 --- a/src/axis/rtl/taxi_axis_cobs_encode.sv +++ b/src/axis/rtl/taxi_axis_cobs_encode.sv @@ -40,19 +40,21 @@ if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8) $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); // state register -localparam [1:0] - INPUT_STATE_IDLE = 2'd0, - INPUT_STATE_SEGMENT = 2'd1, - INPUT_STATE_FINAL_ZERO = 2'd2, - INPUT_STATE_APPEND_ZERO = 2'd3; +typedef enum logic [1:0] { + INPUT_STATE_IDLE, + INPUT_STATE_SEGMENT, + INPUT_STATE_FINAL_ZERO, + INPUT_STATE_APPEND_ZERO +} input_state_t; -logic [1:0] input_state_reg = INPUT_STATE_IDLE, input_state_next; +input_state_t input_state_reg = INPUT_STATE_IDLE, input_state_next; -localparam [0:0] - OUTPUT_STATE_IDLE = 1'd0, - OUTPUT_STATE_SEGMENT = 1'd1; +typedef enum logic [0:0] { + OUTPUT_STATE_IDLE, + OUTPUT_STATE_SEGMENT +} output_state_t; -logic [0:0] output_state_reg = OUTPUT_STATE_IDLE, output_state_next; +output_state_t output_state_reg = OUTPUT_STATE_IDLE, output_state_next; logic [7:0] input_count_reg = 8'd0, input_count_next; logic [7:0] output_count_reg = 8'd0, output_count_next;