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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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219
src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv
View File

@@ -19,118 +19,67 @@ module fpga_core #
(
parameter logic SIM = 1'b0,
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtexuplus"
parameter string FAMILY = "virtexuplus",
parameter PORT_CNT = 4,
parameter GTY_QUAD_CNT = PORT_CNT,
parameter GTY_CNT = GTY_QUAD_CNT*4,
parameter GTY_CLK_CNT = GTY_QUAD_CNT
)
(
/*
* Clock: 125 MHz
* Synchronous reset
*/
input wire logic clk_125mhz,
input wire logic rst_125mhz,
input wire logic clk_125mhz,
input wire logic rst_125mhz,
/*
* GPIO
*/
output wire logic led,
output wire logic led,
/*
* UART: 3000000 bps, 8N1
*/
input wire logic uart_rxd,
output wire logic uart_txd,
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* I2C
*/
input wire logic eeprom_i2c_scl_i,
output wire logic eeprom_i2c_scl_o,
input wire logic eeprom_i2c_sda_i,
output wire logic eeprom_i2c_sda_o,
input wire logic eeprom_i2c_scl_i,
output wire logic eeprom_i2c_scl_o,
input wire logic eeprom_i2c_sda_i,
output wire logic eeprom_i2c_sda_o,
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic qsfp0_resetl,
input wire logic qsfp0_modprsl,
input wire logic qsfp0_intl,
output wire logic qsfp0_lpmode,
output wire logic [PORT_CNT-1:0] eth_port_resetl,
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
input wire logic [PORT_CNT-1:0] eth_port_intl,
output wire logic [PORT_CNT-1:0] eth_port_lpmode,
input wire logic qsfp0_i2c_scl_i,
output wire logic qsfp0_i2c_scl_o,
input wire logic qsfp0_i2c_sda_i,
output wire logic qsfp0_i2c_sda_o,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
output wire logic qsfp1_resetl,
input wire logic qsfp1_modprsl,
input wire logic qsfp1_intl,
output wire logic qsfp1_lpmode,
input wire logic qsfp1_i2c_scl_i,
output wire logic qsfp1_i2c_scl_o,
input wire logic qsfp1_i2c_sda_i,
output wire logic qsfp1_i2c_sda_o,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
output wire logic qsfp2_resetl,
input wire logic qsfp2_modprsl,
input wire logic qsfp2_intl,
output wire logic qsfp2_lpmode,
input wire logic qsfp2_i2c_scl_i,
output wire logic qsfp2_i2c_scl_o,
input wire logic qsfp2_i2c_sda_i,
output wire logic qsfp2_i2c_sda_o,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
output wire logic qsfp3_resetl,
input wire logic qsfp3_modprsl,
input wire logic qsfp3_intl,
output wire logic qsfp3_lpmode,
input wire logic qsfp3_i2c_scl_i,
output wire logic qsfp3_i2c_scl_o,
input wire logic qsfp3_i2c_sda_i,
output wire logic qsfp3_i2c_sda_o
input wire logic [PORT_CNT-1:0] eth_port_i2c_scl_i,
output wire logic [PORT_CNT-1:0] eth_port_i2c_scl_o,
input wire logic [PORT_CNT-1:0] eth_port_i2c_sda_i,
output wire logic [PORT_CNT-1:0] eth_port_i2c_sda_o
);
assign eeprom_i2c_scl_o = 1'b1;
assign eeprom_i2c_sda_o = 1'b1;
assign qsfp0_i2c_scl_o = 1'b1;
assign qsfp0_i2c_sda_o = 1'b1;
assign qsfp1_i2c_scl_o = 1'b1;
assign qsfp1_i2c_sda_o = 1'b1;
assign qsfp2_i2c_scl_o = 1'b1;
assign qsfp2_i2c_sda_o = 1'b1;
assign qsfp3_i2c_scl_o = 1'b1;
assign qsfp3_i2c_sda_o = 1'b1;
assign eth_port_i2c_scl_o = '1;
assign eth_port_i2c_sda_o = '1;
// XFCP
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
@@ -211,7 +160,7 @@ xfcp_stats_inst (
.s_axis_stat(axis_stat)
);
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[4]();
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
taxi_axis_arb_mux #(
.S_COUNT($size(axis_eth_stat)),
@@ -235,52 +184,26 @@ stat_mux_inst (
);
// QSFP28
assign qsfp0_resetl = 1'b1;
assign qsfp0_lpmode = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
assign qsfp2_resetl = 1'b1;
assign qsfp2_lpmode = 1'b0;
assign qsfp3_resetl = 1'b1;
assign qsfp3_lpmode = 1'b0;
assign eth_port_resetl = '1;
assign eth_port_lpmode = '0;
localparam GTY_QUAD_CNT = 4;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire [GTY_CNT-1:0] eth_gty_tx_p;
wire [GTY_CNT-1:0] eth_gty_tx_n;
wire [GTY_CNT-1:0] eth_gty_rx_p = {qsfp3_rx_p, qsfp2_rx_p, qsfp1_rx_p, qsfp0_rx_p};
wire [GTY_CNT-1:0] eth_gty_rx_n = {qsfp3_rx_n, qsfp2_rx_n, qsfp1_rx_n, qsfp0_rx_n};
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p = {qsfp3_mgt_refclk_b0_p, qsfp2_mgt_refclk_b0_p, qsfp1_mgt_refclk_b0_p, qsfp0_mgt_refclk_b0_p};
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n = {qsfp3_mgt_refclk_b0_n, qsfp2_mgt_refclk_b0_n, qsfp1_mgt_refclk_b0_n, qsfp0_mgt_refclk_b0_n};
assign qsfp0_tx_p = eth_gty_tx_p[3:0];
assign qsfp0_tx_n = eth_gty_tx_n[3:0];
assign qsfp1_tx_p = eth_gty_tx_p[7:4];
assign qsfp1_tx_n = eth_gty_tx_n[7:4];
assign qsfp2_tx_p = eth_gty_tx_p[11:8];
assign qsfp2_tx_n = eth_gty_tx_n[11:8];
assign qsfp3_tx_p = eth_gty_tx_p[15:12];
assign qsfp3_tx_n = eth_gty_tx_n[15:12];
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -417,12 +340,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -439,24 +362,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -464,8 +387,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -510,7 +433,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -535,42 +458,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

160
src/eth/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv
View File

@@ -50,10 +50,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
// input wire logic qsfp0_mgt_refclk_b1_p,
@@ -69,10 +69,10 @@ module fpga #
inout wire logic qsfp0_i2c_scl,
inout wire logic qsfp0_i2c_sda,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
// input wire logic qsfp1_mgt_refclk_b1_p,
@@ -88,10 +88,10 @@ module fpga #
inout wire logic qsfp1_i2c_scl,
inout wire logic qsfp1_i2c_sda,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
// input wire logic qsfp2_mgt_refclk_b2_p,
@@ -107,10 +107,10 @@ module fpga #
inout wire logic qsfp2_i2c_scl,
inout wire logic qsfp2_i2c_sda,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
output wire logic qsfp3_tx_p[4],
output wire logic qsfp3_tx_n[4],
input wire logic qsfp3_rx_p[4],
input wire logic qsfp3_rx_n[4],
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
// input wire logic qsfp3_mgt_refclk_b3_p,
@@ -336,10 +336,56 @@ assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
localparam PORT_CNT = 4;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign qsfp2_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp2_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp2_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp2_rx_n;
assign qsfp3_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp3_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp3_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp3_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[2] = qsfp2_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[2] = qsfp2_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[3] = qsfp3_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[3] = qsfp3_mgt_refclk_b0_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY)
.FAMILY(FAMILY),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -371,73 +417,23 @@ core_inst (
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_p(qsfp0_tx_p),
.qsfp0_tx_n(qsfp0_tx_n),
.qsfp0_rx_p(qsfp0_rx_p),
.qsfp0_rx_n(qsfp0_rx_n),
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.eth_port_resetl({qsfp3_resetl, qsfp2_resetl, qsfp1_resetl, qsfp0_resetl}),
.eth_port_modprsl({qsfp3_modprsl, qsfp2_modprsl, qsfp1_modprsl, qsfp0_modprsl}),
.eth_port_intl({qsfp3_intl, qsfp2_intl, qsfp1_intl, qsfp0_intl}),
.eth_port_lpmode({qsfp3_lpmode, qsfp2_lpmode, qsfp1_lpmode, qsfp0_lpmode}),
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
.qsfp1_tx_p(qsfp1_tx_p),
.qsfp1_tx_n(qsfp1_tx_n),
.qsfp1_rx_p(qsfp1_rx_p),
.qsfp1_rx_n(qsfp1_rx_n),
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
.qsfp2_tx_p(qsfp2_tx_p),
.qsfp2_tx_n(qsfp2_tx_n),
.qsfp2_rx_p(qsfp2_rx_p),
.qsfp2_rx_n(qsfp2_rx_n),
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
.qsfp2_modprsl(qsfp2_modprsl_int),
.qsfp2_resetl(qsfp2_resetl),
.qsfp2_intl(qsfp2_intl_int),
.qsfp2_lpmode(qsfp2_lpmode),
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
.qsfp3_tx_p(qsfp3_tx_p),
.qsfp3_tx_n(qsfp3_tx_n),
.qsfp3_rx_p(qsfp3_rx_p),
.qsfp3_rx_n(qsfp3_rx_n),
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
.qsfp3_modprsl(qsfp3_modprsl_int),
.qsfp3_resetl(qsfp3_resetl),
.qsfp3_intl(qsfp3_intl_int),
.qsfp3_lpmode(qsfp3_lpmode),
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
.eth_port_i2c_scl_i({qsfp3_i2c_scl_i, qsfp2_i2c_scl_i, qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
.eth_port_i2c_scl_o({qsfp3_i2c_scl_o, qsfp2_i2c_scl_o, qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
.eth_port_i2c_sda_i({qsfp3_i2c_sda_i, qsfp2_i2c_sda_i, qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
.eth_port_i2c_sda_o({qsfp3_i2c_sda_o, qsfp2_i2c_sda_o, qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
);
endmodule

160
src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
View File

@@ -50,10 +50,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
// input wire logic qsfp0_mgt_refclk_b1_p,
@@ -69,10 +69,10 @@ module fpga #
inout wire logic qsfp0_i2c_scl,
inout wire logic qsfp0_i2c_sda,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
// input wire logic qsfp1_mgt_refclk_b1_p,
@@ -88,10 +88,10 @@ module fpga #
inout wire logic qsfp1_i2c_scl,
inout wire logic qsfp1_i2c_sda,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
// input wire logic qsfp2_mgt_refclk_b2_p,
@@ -107,10 +107,10 @@ module fpga #
inout wire logic qsfp2_i2c_scl,
inout wire logic qsfp2_i2c_sda,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
output wire logic qsfp3_tx_p[4],
output wire logic qsfp3_tx_n[4],
input wire logic qsfp3_rx_p[4],
input wire logic qsfp3_rx_n[4],
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
// input wire logic qsfp3_mgt_refclk_b3_p,
@@ -336,10 +336,56 @@ assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
localparam PORT_CNT = 4;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign qsfp2_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp2_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp2_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp2_rx_n;
assign qsfp3_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp3_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp3_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp3_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[2] = qsfp2_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[2] = qsfp2_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[3] = qsfp3_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[3] = qsfp3_mgt_refclk_b0_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY)
.FAMILY(FAMILY),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -371,73 +417,23 @@ core_inst (
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_p(qsfp0_tx_p),
.qsfp0_tx_n(qsfp0_tx_n),
.qsfp0_rx_p(qsfp0_rx_p),
.qsfp0_rx_n(qsfp0_rx_n),
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.eth_port_resetl({qsfp3_resetl, qsfp2_resetl, qsfp1_resetl, qsfp0_resetl}),
.eth_port_modprsl({qsfp3_modprsl, qsfp2_modprsl, qsfp1_modprsl, qsfp0_modprsl}),
.eth_port_intl({qsfp3_intl, qsfp2_intl, qsfp1_intl, qsfp0_intl}),
.eth_port_lpmode({qsfp3_lpmode, qsfp2_lpmode, qsfp1_lpmode, qsfp0_lpmode}),
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
.qsfp1_tx_p(qsfp1_tx_p),
.qsfp1_tx_n(qsfp1_tx_n),
.qsfp1_rx_p(qsfp1_rx_p),
.qsfp1_rx_n(qsfp1_rx_n),
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
.qsfp2_tx_p(qsfp2_tx_p),
.qsfp2_tx_n(qsfp2_tx_n),
.qsfp2_rx_p(qsfp2_rx_p),
.qsfp2_rx_n(qsfp2_rx_n),
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
.qsfp2_modprsl(qsfp2_modprsl_int),
.qsfp2_resetl(qsfp2_resetl),
.qsfp2_intl(qsfp2_intl_int),
.qsfp2_lpmode(qsfp2_lpmode),
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
.qsfp3_tx_p(qsfp3_tx_p),
.qsfp3_tx_n(qsfp3_tx_n),
.qsfp3_rx_p(qsfp3_rx_p),
.qsfp3_rx_n(qsfp3_rx_n),
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
.qsfp3_modprsl(qsfp3_modprsl_int),
.qsfp3_resetl(qsfp3_resetl),
.qsfp3_intl(qsfp3_intl_int),
.qsfp3_lpmode(qsfp3_lpmode),
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
.eth_port_i2c_scl_i({qsfp3_i2c_scl_i, qsfp2_i2c_scl_i, qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
.eth_port_i2c_scl_o({qsfp3_i2c_scl_o, qsfp2_i2c_scl_o, qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
.eth_port_i2c_sda_i({qsfp3_i2c_sda_i, qsfp2_i2c_sda_i, qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
.eth_port_i2c_sda_o({qsfp3_i2c_sda_o, qsfp2_i2c_sda_o, qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
);
endmodule

4
src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile
View File

@@ -41,6 +41,10 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
export PARAM_SIM := "1'b1"
export PARAM_VENDOR := "\"XILINX\""
export PARAM_FAMILY := "\"virtexuplus\""
export PARAM_PORT_CNT := 4
export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

11
src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -42,10 +42,6 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp0_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp1_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp2_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp3_mgt_refclk_b0_p, 3.102, units="ns").start())
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
@@ -53,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -216,6 +215,10 @@ def test_fpga_core(request):
parameters['SIM'] = "1'b1"
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"virtexuplus\""
parameters['PORT_CNT'] = 4
parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}