From 17b4c37a1ed2dafee87a799412559a2583ddef6e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 13 Feb 2025 10:52:27 -0800 Subject: [PATCH] ptp: Add PTP clock module and testbench Signed-off-by: Alex Forencich --- rtl/ptp/taxi_ptp_clock.sv | 343 ++++++++++++++++ tb/ptp/taxi_ptp_clock/Makefile | 50 +++ tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py | 401 +++++++++++++++++++ 3 files changed, 794 insertions(+) create mode 100644 rtl/ptp/taxi_ptp_clock.sv create mode 100644 tb/ptp/taxi_ptp_clock/Makefile create mode 100644 tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py diff --git a/rtl/ptp/taxi_ptp_clock.sv b/rtl/ptp/taxi_ptp_clock.sv new file mode 100644 index 0000000..5a3badb --- /dev/null +++ b/rtl/ptp/taxi_ptp_clock.sv @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * PTP clock module + */ +module taxi_ptp_clock # +( + parameter PERIOD_NS_W = 4, + parameter OFFSET_NS_W = 4, + parameter FNS_W = 16, + parameter PERIOD_NS_NUM = 32, + parameter PERIOD_NS_DENOM = 5, + parameter PIPELINE_OUTPUT = 0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * Timestamp inputs for synchronization + */ + input wire logic [95:0] input_ts_tod, + input wire logic input_ts_tod_valid, + input wire logic [63:0] input_ts_rel, + input wire logic input_ts_rel_valid, + + /* + * Period adjustment + */ + input wire logic [PERIOD_NS_W-1:0] input_period_ns, + input wire logic [FNS_W-1:0] input_period_fns, + input wire logic input_period_valid, + + /* + * Offset adjustment + */ + input wire logic [OFFSET_NS_W-1:0] input_adj_ns, + input wire logic [FNS_W-1:0] input_adj_fns, + input wire logic [15:0] input_adj_count, + input wire logic input_adj_valid, + output wire logic input_adj_active, + + /* + * Drift adjustment + */ + input wire logic [FNS_W-1:0] input_drift_num, + input wire logic [15:0] input_drift_denom, + input wire logic input_drift_valid, + + /* + * Timestamp outputs + */ + output wire logic [95:0] output_ts_tod, + output wire logic output_ts_tod_step, + output wire logic [63:0] output_ts_rel, + output wire logic output_ts_rel_step, + + /* + * PPS output + */ + output wire logic output_pps, + output wire logic output_pps_str +); + +localparam PERIOD_NS = PERIOD_NS_NUM / PERIOD_NS_DENOM; +localparam PERIOD_NS_REM = PERIOD_NS_NUM - PERIOD_NS*PERIOD_NS_DENOM; +localparam PERIOD_FNS = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) / (32+FNS_W)'(PERIOD_NS_DENOM); +localparam PERIOD_FNS_REM = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) - PERIOD_FNS*PERIOD_NS_DENOM; + +localparam INC_NS_W = $clog2(2**PERIOD_NS_W + 2**OFFSET_NS_W); + +localparam [30:0] NS_PER_S = 31'd1_000_000_000; + +logic [PERIOD_NS_W-1:0] period_ns_reg = PERIOD_NS_W'(PERIOD_NS); +logic [FNS_W-1:0] period_fns_reg = FNS_W'(PERIOD_FNS); + +logic [OFFSET_NS_W-1:0] adj_ns_reg = '0; +logic [FNS_W-1:0] adj_fns_reg = '0; +logic [15:0] adj_count_reg = '0; +logic adj_active_reg = '0; + +logic [FNS_W-1:0] drift_num_reg = FNS_W'(PERIOD_FNS_REM); +logic [15:0] drift_denom_reg = 16'(PERIOD_NS_DENOM); +logic [15:0] drift_cnt_reg = '0; +logic drift_apply_reg = 1'b0; + +logic [INC_NS_W-1:0] ts_inc_ns_reg = '0; +logic [FNS_W-1:0] ts_inc_fns_reg = '0; +logic [INC_NS_W-1:0] ts_inc_ns_delay_reg = '0; +logic [FNS_W-1:0] ts_inc_fns_delay_reg = '0; +logic [30:0] ts_inc_ns_ovf_reg = '0; +logic [FNS_W-1:0] ts_inc_fns_ovf_reg = '0; + +logic [47:0] ts_tod_s_reg = '0; +logic [29:0] ts_tod_ns_reg = '0; +logic [FNS_W-1:0] ts_tod_fns_reg = '0; +logic [29:0] ts_tod_ns_inc_reg = '0; +logic [FNS_W-1:0] ts_tod_fns_inc_reg = '0; +logic [30:0] ts_tod_ns_ovf_reg = '1; +logic [FNS_W-1:0] ts_tod_fns_ovf_reg = '1; + +logic [47:0] ts_rel_ns_reg = '0; +logic [FNS_W-1:0] ts_rel_fns_reg = '0; + +logic ts_tod_step_reg = 1'b0; +logic ts_rel_step_reg = 1'b0; + +logic [47:0] temp; + +logic pps_reg = 0; +logic pps_str_reg = 0; + +assign input_adj_active = adj_active_reg; + +if (PIPELINE_OUTPUT > 0) begin + + // pipeline + (* shreg_extract = "no" *) + logic [95:0] output_ts_tod_reg[0:PIPELINE_OUTPUT-1]; + (* shreg_extract = "no" *) + logic output_ts_tod_step_reg[0:PIPELINE_OUTPUT-1]; + (* shreg_extract = "no" *) + logic [63:0] output_ts_rel_reg[0:PIPELINE_OUTPUT-1]; + (* shreg_extract = "no" *) + logic output_ts_rel_step_reg[0:PIPELINE_OUTPUT-1]; + (* shreg_extract = "no" *) + logic output_pps_reg[0:PIPELINE_OUTPUT-1]; + (* shreg_extract = "no" *) + logic output_pps_str_reg[0:PIPELINE_OUTPUT-1]; + + assign output_ts_tod = output_ts_tod_reg[PIPELINE_OUTPUT-1]; + assign output_ts_tod_step = output_ts_tod_step_reg[PIPELINE_OUTPUT-1]; + + assign output_ts_rel = output_ts_rel_reg[PIPELINE_OUTPUT-1]; + assign output_ts_rel_step = output_ts_rel_step_reg[PIPELINE_OUTPUT-1]; + + assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1]; + assign output_pps_str = output_pps_str_reg[PIPELINE_OUTPUT-1]; + + initial begin + for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin + output_ts_tod_reg[i] = '0; + output_ts_tod_step_reg[i] = 1'b0; + + output_ts_rel_reg[i] = '0; + output_ts_rel_step_reg[i] = 1'b0; + + output_pps_reg[i] = 1'b0; + output_pps_str_reg[i] = 1'b0; + end + end + + always_ff @(posedge clk) begin + output_ts_tod_reg[0][95:48] <= ts_tod_s_reg; + output_ts_tod_reg[0][47:46] <= 2'b00; + output_ts_tod_reg[0][45:16] <= ts_tod_ns_reg; + output_ts_tod_reg[0][15:0] <= {ts_tod_fns_reg, 16'd0} >> FNS_W; + output_ts_tod_step_reg[0] <= ts_tod_step_reg; + + output_ts_rel_reg[0][63:16] <= ts_rel_ns_reg; + output_ts_rel_reg[0][15:0] <= {ts_rel_fns_reg, 16'd0} >> FNS_W; + output_ts_rel_step_reg[0] <= ts_rel_step_reg; + + output_pps_reg[0] <= pps_reg; + output_pps_str_reg[0] <= pps_str_reg; + + for (integer i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin + output_ts_tod_reg[i+1] <= output_ts_tod_reg[i]; + output_ts_tod_step_reg[i+1] <= output_ts_tod_step_reg[i]; + + output_ts_rel_reg[i+1] <= output_ts_rel_reg[i]; + output_ts_rel_step_reg[i+1] <= output_ts_rel_step_reg[i]; + + output_pps_reg[i+1] <= output_pps_reg[i]; + output_pps_str_reg[i+1] <= output_pps_str_reg[i]; + end + + if (rst) begin + for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin + output_ts_tod_reg[i] <= '0; + output_ts_tod_step_reg[i] <= 1'b0; + + output_ts_rel_reg[i] <= '0; + output_ts_rel_step_reg[i] <= 1'b0; + + output_pps_reg[i] <= 1'b0; + output_pps_str_reg[i] <= 1'b0; + end + end + end + +end else begin + + assign output_ts_tod[95:48] = ts_tod_s_reg; + assign output_ts_tod[47:46] = 2'b00; + assign output_ts_tod[45:16] = ts_tod_ns_reg; + assign output_ts_tod[15:0] = 16'({ts_tod_fns_reg, 16'd0} >> FNS_W); + assign output_ts_tod_step = ts_tod_step_reg; + + assign output_ts_rel[63:16] = ts_rel_ns_reg; + assign output_ts_rel[15:0] = 16'({ts_rel_fns_reg, 16'd0} >> FNS_W); + assign output_ts_rel_step = ts_rel_step_reg; + + assign output_pps = pps_reg; + assign output_pps_str = pps_str_reg; + +end + +always_ff @(posedge clk) begin + ts_tod_step_reg <= 1'b0; + ts_rel_step_reg <= 1'b0; + drift_apply_reg <= 1'b0; + pps_reg <= 1'b0; + + // latch parameters + if (input_period_valid) begin + period_ns_reg <= input_period_ns; + period_fns_reg <= input_period_fns; + end + + if (input_adj_valid) begin + adj_ns_reg <= input_adj_ns; + adj_fns_reg <= input_adj_fns; + adj_count_reg <= input_adj_count; + end + + if (input_drift_valid) begin + drift_num_reg <= input_drift_num; + drift_denom_reg <= input_drift_denom; + end + + // timestamp increment calculation + {ts_inc_ns_reg, ts_inc_fns_reg} <= $signed({1'b0, period_ns_reg, period_fns_reg}) + + (adj_active_reg ? (INC_NS_W+FNS_W)'($signed({adj_ns_reg, adj_fns_reg})) : '0) + + (drift_apply_reg ? (INC_NS_W+FNS_W)'($signed(drift_num_reg)) : '0); + + // offset adjust counter + if (adj_count_reg != 0) begin + adj_count_reg <= adj_count_reg - 1; + adj_active_reg <= 1; + ts_tod_step_reg <= 1; + ts_rel_step_reg <= 1; + end else begin + adj_active_reg <= 0; + end + + // drift counter + if (drift_cnt_reg != 0) begin + drift_cnt_reg <= drift_cnt_reg - 1; + end else begin + drift_cnt_reg <= drift_denom_reg-1; + drift_apply_reg <= 1'b1; + end + + // 96 bit timestamp + {ts_inc_ns_delay_reg, ts_inc_fns_delay_reg} <= {ts_inc_ns_reg, ts_inc_fns_reg}; + {ts_inc_ns_ovf_reg, ts_inc_fns_ovf_reg} <= {NS_PER_S, {FNS_W{1'b0}}} - (31+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg}); + + {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} + (30+FNS_W)'({ts_inc_ns_delay_reg, ts_inc_fns_delay_reg}); + {ts_tod_ns_ovf_reg, ts_tod_fns_ovf_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} - (31+FNS_W)'({ts_inc_ns_ovf_reg[29:0], ts_inc_fns_ovf_reg}); + {ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg}; + + if (ts_tod_ns_reg[29]) begin + pps_str_reg <= 1'b0; + end + + if (!ts_tod_ns_ovf_reg[30]) begin + // if the overflow lookahead did not borrow, one second has elapsed + // increment seconds field, pre-compute normal increment, force overflow lookahead borrow bit set + {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= (30+FNS_W)'({ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg} + {ts_inc_ns_delay_reg, ts_inc_fns_delay_reg}); + ts_tod_ns_ovf_reg[30] <= 1'b1; + {ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg}; + ts_tod_s_reg <= ts_tod_s_reg + 1; + pps_reg <= 1'b1; + pps_str_reg <= 1'b1; + end + + if (input_ts_tod_valid) begin + // load timestamp + ts_tod_s_reg <= input_ts_tod[95:48]; + ts_tod_ns_reg <= input_ts_tod[45:16]; + ts_tod_ns_inc_reg <= input_ts_tod[45:16]; + ts_tod_ns_ovf_reg[30] <= 1'b1; + ts_tod_fns_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W); + ts_tod_fns_inc_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W); + ts_tod_step_reg <= 1; + end + + // 64 bit timestamp + {ts_rel_ns_reg, ts_rel_fns_reg} <= {ts_rel_ns_reg, ts_rel_fns_reg} + (48+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg}); + + if (input_ts_rel_valid) begin + // load timestamp + {ts_rel_ns_reg, ts_rel_fns_reg} <= input_ts_rel; + ts_rel_step_reg <= 1; + end + + if (rst) begin + period_ns_reg <= PERIOD_NS_W'(PERIOD_NS); + period_fns_reg <= FNS_W'(PERIOD_FNS); + + adj_ns_reg <= '0; + adj_fns_reg <= '0; + adj_count_reg <= '0; + adj_active_reg <= '0; + + drift_num_reg <= FNS_W'(PERIOD_FNS_REM); + drift_denom_reg <= 16'(PERIOD_NS_DENOM); + drift_cnt_reg <= '0; + drift_apply_reg <= 1'b0; + + ts_tod_s_reg <= '0; + ts_tod_ns_reg <= '0; + ts_tod_fns_reg <= '0; + ts_tod_ns_inc_reg <= '0; + ts_tod_fns_inc_reg <= '0; + ts_tod_ns_ovf_reg[30] <= 1'b1; + ts_tod_step_reg <= '0; + + ts_rel_ns_reg <= '0; + ts_rel_fns_reg <= '0; + ts_rel_step_reg <= '0; + + pps_reg <= '0; + pps_str_reg <= '0; + end +end + +endmodule + +`resetall diff --git a/tb/ptp/taxi_ptp_clock/Makefile b/tb/ptp/taxi_ptp_clock/Makefile new file mode 100644 index 0000000..2fdc8a9 --- /dev/null +++ b/tb/ptp/taxi_ptp_clock/Makefile @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_ptp_clock +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_PERIOD_NS_W := 4 +export PARAM_OFFSET_NS_W := 4 +export PARAM_FNS_W := 16 +export PARAM_PERIOD_NS_NUM := 32 +export PARAM_PERIOD_NS_DENOM := 5 +export PARAM_PIPELINE_OUTPUT := 0 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py b/tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py new file mode 100644 index 0000000..3fface0 --- /dev/null +++ b/tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py @@ -0,0 +1,401 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +from decimal import Decimal + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.utils import get_sim_time + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + dut.input_ts_tod.setimmediatevalue(0) + dut.input_ts_tod_valid.setimmediatevalue(0) + dut.input_ts_rel.setimmediatevalue(0) + dut.input_ts_rel_valid.setimmediatevalue(0) + + dut.input_period_ns.setimmediatevalue(0) + dut.input_period_fns.setimmediatevalue(0) + dut.input_period_valid.setimmediatevalue(0) + + dut.input_adj_ns.setimmediatevalue(0) + dut.input_adj_fns.setimmediatevalue(0) + dut.input_adj_count.setimmediatevalue(0) + dut.input_adj_valid.setimmediatevalue(0) + dut.input_adj_active.setimmediatevalue(0) + + dut.input_drift_num.setimmediatevalue(0) + dut.input_drift_denom.setimmediatevalue(0) + dut.input_drift_valid.setimmediatevalue(0) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + def get_output_ts_tod_ns(self): + ts = self.dut.output_ts_tod.value.integer + return Decimal(ts >> 48).scaleb(9) + (Decimal(ts & 0xffffffffffff) / Decimal(2**16)) + + def get_output_ts_tod_s(self): + return self.get_output_ts_tod_ns().scaleb(-9) + + def get_output_ts_rel_ns(self): + ts = self.dut.output_ts_rel.value.integer + return Decimal(ts) / Decimal(2**16) + + def get_output_ts_rel_s(self): + return self.get_output_ts_rel_ns().scaleb(-9) + + +@cocotb.test() +async def run_default_rate(dut): + + tb = TB(dut) + + await tb.reset() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + start_time = Decimal(get_sim_time('fs')).scaleb(-6) + start_ts_tod = tb.get_output_ts_tod_ns() + start_ts_rel = tb.get_output_ts_rel_ns() + + for k in range(10000): + await RisingEdge(dut.clk) + + stop_time = Decimal(get_sim_time('fs')).scaleb(-6) + stop_ts_tod = tb.get_output_ts_tod_ns() + stop_ts_rel = tb.get_output_ts_rel_ns() + + time_delta = stop_time-start_time + ts_tod_delta = stop_ts_tod-start_ts_tod + ts_rel_delta = stop_ts_rel-start_ts_rel + + tb.log.info("sim time delta : %s ns", time_delta) + tb.log.info("ToD ts delta : %s ns", ts_tod_delta) + tb.log.info("Rel ts delta : %s ns", ts_rel_delta) + + ts_tod_diff = time_delta - ts_tod_delta + ts_rel_diff = time_delta - ts_rel_delta + + tb.log.info("ToD ts diff : %s ns", ts_tod_diff) + tb.log.info("Rel ts diff : %s ns", ts_rel_diff) + + assert abs(ts_tod_diff) < 1e-3 + assert abs(ts_rel_diff) < 1e-3 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +@cocotb.test() +async def run_load_timestamps(dut): + + tb = TB(dut) + + await tb.reset() + + await RisingEdge(dut.clk) + + dut.input_ts_tod.value = 12345678 + dut.input_ts_tod_valid.value = 1 + dut.input_ts_rel.value = 12345678 + dut.input_ts_rel_valid.value = 1 + + await RisingEdge(dut.clk) + + dut.input_ts_tod_valid.value = 0 + dut.input_ts_rel_valid.value = 0 + + await RisingEdge(dut.clk) + + assert dut.output_ts_tod.value.integer == 12345678 + assert dut.output_ts_tod_step.value.integer == 1 + assert dut.output_ts_rel.value.integer == 12345678 + assert dut.output_ts_rel_step.value.integer == 1 + + await RisingEdge(dut.clk) + + start_time = Decimal(get_sim_time('fs')).scaleb(-6) + start_ts_tod = tb.get_output_ts_tod_ns() + start_ts_rel = tb.get_output_ts_rel_ns() + + for k in range(2000): + await RisingEdge(dut.clk) + + stop_time = Decimal(get_sim_time('fs')).scaleb(-6) + stop_ts_tod = tb.get_output_ts_tod_ns() + stop_ts_rel = tb.get_output_ts_rel_ns() + + time_delta = stop_time-start_time + ts_tod_delta = stop_ts_tod-start_ts_tod + ts_rel_delta = stop_ts_rel-start_ts_rel + + tb.log.info("sim time delta : %s ns", time_delta) + tb.log.info("ToD ts delta : %s ns", ts_tod_delta) + tb.log.info("Rel ts delta : %s ns", ts_rel_delta) + + ts_tod_diff = time_delta - ts_tod_delta + ts_rel_diff = time_delta - ts_rel_delta + + tb.log.info("ToD ts diff : %s ns", ts_tod_diff) + tb.log.info("Rel ts diff : %s ns", ts_rel_diff) + + assert abs(ts_tod_diff) < 1e-3 + assert abs(ts_rel_diff) < 1e-3 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +@cocotb.test() +async def run_seconds_increment(dut): + + tb = TB(dut) + + await tb.reset() + + await RisingEdge(dut.clk) + + dut.input_ts_tod.value = 999990000 << 16 + dut.input_ts_tod_valid.value = 1 + dut.input_ts_rel.value = 999990000 << 16 + dut.input_ts_rel_valid.value = 1 + + await RisingEdge(dut.clk) + + dut.input_ts_tod_valid.value = 0 + dut.input_ts_rel_valid.value = 0 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + start_time = Decimal(get_sim_time('fs')).scaleb(-6) + start_ts_tod = tb.get_output_ts_tod_ns() + start_ts_rel = tb.get_output_ts_rel_ns() + + saw_pps = False + + for k in range(3000): + await RisingEdge(dut.clk) + + if dut.output_pps.value.integer: + saw_pps = True + tb.log.info("Got PPS with sink ToD TS %s", tb.get_output_ts_tod_ns()) + assert (tb.get_output_ts_tod_s() - 1) < 6.4e-9 + + assert saw_pps + + stop_time = Decimal(get_sim_time('fs')).scaleb(-6) + stop_ts_tod = tb.get_output_ts_tod_ns() + stop_ts_rel = tb.get_output_ts_rel_ns() + + time_delta = stop_time-start_time + ts_tod_delta = stop_ts_tod-start_ts_tod + ts_rel_delta = stop_ts_rel-start_ts_rel + + tb.log.info("sim time delta : %s ns", time_delta) + tb.log.info("ToD ts delta : %s ns", ts_tod_delta) + tb.log.info("Rel ts delta : %s ns", ts_rel_delta) + + ts_tod_diff = time_delta - ts_tod_delta + ts_rel_diff = time_delta - ts_rel_delta + + tb.log.info("ToD ts diff : %s ns", ts_tod_diff) + tb.log.info("Rel ts diff : %s ns", ts_rel_diff) + + assert abs(ts_tod_diff) < 1e-3 + assert abs(ts_rel_diff) < 1e-3 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +@cocotb.test() +async def run_frequency_adjustment(dut): + + tb = TB(dut) + + await tb.reset() + + await RisingEdge(dut.clk) + + dut.input_period_ns.value = 0x6 + dut.input_period_fns.value = 0x6624 + dut.input_period_valid.value = 1 + + await RisingEdge(dut.clk) + + dut.input_period_valid.value = 0 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + await RisingEdge(dut.clk) + start_time = Decimal(get_sim_time('fs')).scaleb(-6) + start_ts_tod = tb.get_output_ts_tod_ns() + start_ts_rel = tb.get_output_ts_rel_ns() + + for k in range(10000): + await RisingEdge(dut.clk) + + stop_time = Decimal(get_sim_time('fs')).scaleb(-6) + stop_ts_tod = tb.get_output_ts_tod_ns() + stop_ts_rel = tb.get_output_ts_rel_ns() + + time_delta = stop_time-start_time + ts_tod_delta = stop_ts_tod-start_ts_tod + ts_rel_delta = stop_ts_rel-start_ts_rel + + tb.log.info("sim time delta : %s ns", time_delta) + tb.log.info("ToD ts delta : %s ns", ts_tod_delta) + tb.log.info("Rel ts delta : %s ns", ts_rel_delta) + + ts_tod_diff = time_delta - ts_tod_delta * Decimal(6.4/(6+(0x6624+2/5)/2**16)) + ts_rel_diff = time_delta - ts_rel_delta * Decimal(6.4/(6+(0x6624+2/5)/2**16)) + + tb.log.info("ToD ts diff : %s ns", ts_tod_diff) + tb.log.info("Rel ts diff : %s ns", ts_rel_diff) + + assert abs(ts_tod_diff) < 1e-3 + assert abs(ts_rel_diff) < 1e-3 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +@cocotb.test() +async def run_drift_adjustment(dut): + + tb = TB(dut) + + await tb.reset() + + dut.input_drift_num.value = 20 + dut.input_drift_denom.value = 5 + dut.input_drift_valid.value = 1 + + await RisingEdge(dut.clk) + + dut.input_drift_valid.value = 0 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + await RisingEdge(dut.clk) + start_time = Decimal(get_sim_time('fs')).scaleb(-6) + start_ts_tod = tb.get_output_ts_tod_ns() + start_ts_rel = tb.get_output_ts_rel_ns() + + for k in range(10000): + await RisingEdge(dut.clk) + + stop_time = Decimal(get_sim_time('fs')).scaleb(-6) + stop_ts_tod = tb.get_output_ts_tod_ns() + stop_ts_rel = tb.get_output_ts_rel_ns() + + time_delta = stop_time-start_time + ts_tod_delta = stop_ts_tod-start_ts_tod + ts_rel_delta = stop_ts_rel-start_ts_rel + + tb.log.info("sim time delta : %s ns", time_delta) + tb.log.info("ToD ts delta : %s ns", ts_tod_delta) + tb.log.info("Rel ts delta : %s ns", ts_rel_delta) + + ts_tod_diff = time_delta - ts_tod_delta * Decimal(6.4/(6+(0x6666+20/5)/2**16)) + ts_rel_diff = time_delta - ts_rel_delta * Decimal(6.4/(6+(0x6666+20/5)/2**16)) + + tb.log.info("ToD ts diff : %s ns", ts_tod_diff) + tb.log.info("Rel ts diff : %s ns", ts_rel_diff) + + assert abs(ts_tod_diff) < 1e-3 + assert abs(ts_rel_diff) < 1e-3 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_ptp_clock(request): + dut = "taxi_ptp_clock" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, "ptp", f"{dut}.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['PERIOD_NS_W'] = 4 + parameters['OFFSET_NS_W'] = 4 + parameters['FNS_W'] = 16 + parameters['PERIOD_NS_NUM'] = 32 + parameters['PERIOD_NS_DENOM'] = 5 + parameters['PIPELINE_OUTPUT'] = 0 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )