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cndm_proto: Use SV enums for state machines

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-03 12:05:35 -08:00
parent 0ab7538e24
commit 191f7940b3
4 changed files with 27 additions and 23 deletions
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11
src/cndm_proto/rtl/cndm_proto_cpl_wr.sv
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@@ -66,12 +66,13 @@ taxi_axis_if #(
) cpl_comb(); ) cpl_comb();
// Completion write control state machine // Completion write control state machine
localparam [2:0] typedef enum logic [1:0] {
STATE_IDLE = 0, STATE_IDLE,
STATE_RX_CPL = 1, STATE_RX_CPL,
STATE_WRITE_DATA = 2; STATE_WRITE_DATA
} state_t;
logic [2:0] state_reg = STATE_IDLE; state_t state_reg = STATE_IDLE;
logic [15:0] txcq_prod_ptr_reg = '0; logic [15:0] txcq_prod_ptr_reg = '0;
logic [15:0] rxcq_prod_ptr_reg = '0; logic [15:0] rxcq_prod_ptr_reg = '0;

13
src/cndm_proto/rtl/cndm_proto_desc_rd.sv
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@@ -69,13 +69,14 @@ taxi_dma_desc_if #(
) dma_desc(); ) dma_desc();
// Descriptor read control state machine // Descriptor read control state machine
localparam [2:0] typedef enum logic [1:0] {
STATE_IDLE = 0, STATE_IDLE,
STATE_READ_DESC = 1, STATE_READ_DESC,
STATE_READ_DATA = 2, STATE_READ_DATA,
STATE_TX_DESC = 3; STATE_TX_DESC
} state_t;
logic [2:0] state_reg = STATE_IDLE; state_t state_reg = STATE_IDLE;
logic [1:0] desc_req_reg = '0; logic [1:0] desc_req_reg = '0;

13
src/cndm_proto/rtl/cndm_proto_rx.sv
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@@ -64,13 +64,14 @@ taxi_dma_desc_if #(
) dma_desc(); ) dma_desc();
// Receive datapath control state machine // Receive datapath control state machine
localparam [2:0] typedef enum logic [1:0] {
STATE_IDLE = 0, STATE_IDLE,
STATE_RX_DATA = 1, STATE_RX_DATA,
STATE_READ_DESC = 2, STATE_READ_DESC,
STATE_WRITE_DATA = 3; STATE_WRITE_DATA
} state_t;
logic [2:0] state_reg = STATE_IDLE; state_t state_reg = STATE_IDLE;
logic desc_req_reg = 1'b0; logic desc_req_reg = 1'b0;

13
src/cndm_proto/rtl/cndm_proto_tx.sv
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@@ -64,13 +64,14 @@ taxi_dma_desc_if #(
) dma_desc(); ) dma_desc();
// Transmit datapath control state machine // Transmit datapath control state machine
localparam [2:0] typedef enum logic [1:0] {
STATE_IDLE = 0, STATE_IDLE,
STATE_READ_DESC = 1, STATE_READ_DESC,
STATE_READ_DATA = 2, STATE_READ_DATA,
STATE_TX_DATA = 3; STATE_TX_DATA
} state_t;
logic [2:0] state_reg = STATE_IDLE; state_t state_reg = STATE_IDLE;
logic desc_req_reg = 1'b0; logic desc_req_reg = 1'b0;