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eth: Fix sync signal width

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-08-24 21:06:15 -07:00
parent f19a6a8439
commit 1a9e3f20d1
4 changed files with 6 additions and 6 deletions
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4
src/eth/rtl/taxi_axis_baser_tx_32.sv
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@@ -62,7 +62,7 @@ module taxi_axis_baser_tx_32 #
* PTP
*/
input wire logic [PTP_TS_W-1:0] ptp_ts,
output wire logic ptp_ts_cor_sync,
output wire logic [GBX_CNT-1:0] ptp_ts_cor_sync,
input wire logic [PTP_TS_COR_W-1:0] ptp_ts_cor_val = '0,
/*
@@ -270,7 +270,7 @@ assign m_axis_tx_cpl.tuser = '0;
assign tx_os_ready = tx_os_ready_reg;
assign ptp_ts_cor_sync = (GBX_IF_EN && PTP_TS_COR_EN) ? tx_gbx_req_sync : 1'b0;
assign ptp_ts_cor_sync = (GBX_IF_EN && PTP_TS_COR_EN) ? tx_gbx_req_sync : '0;
assign tx_start_packet = start_packet_reg;

4
src/eth/rtl/taxi_axis_baser_tx_64.sv
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@@ -63,7 +63,7 @@ module taxi_axis_baser_tx_64 #
* PTP
*/
input wire logic [PTP_TS_W-1:0] ptp_ts,
output wire logic ptp_ts_cor_sync,
output wire logic [GBX_CNT-1:0] ptp_ts_cor_sync,
input wire logic [PTP_TS_COR_W-1:0] ptp_ts_cor_val = '0,
/*
@@ -286,7 +286,7 @@ assign m_axis_tx_cpl.tuser = '0;
assign tx_os_ready = tx_os_ready_reg;
assign ptp_ts_cor_sync = (GBX_IF_EN && PTP_TS_COR_EN) ? tx_gbx_req_sync : 1'b0;
assign ptp_ts_cor_sync = (GBX_IF_EN && PTP_TS_COR_EN) ? tx_gbx_req_sync : '0;
assign tx_start_packet = start_packet_reg;

2
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv
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@@ -57,7 +57,7 @@ logic tx_os_valid;
logic tx_os_ready;
logic [PTP_TS_W-1:0] ptp_ts;
logic ptp_ts_cor_sync;
logic [GBX_CNT-1:0] ptp_ts_cor_sync;
logic [PTP_TS_COR_W-1:0] ptp_ts_cor_val;
logic [15:0] cfg_tx_max_pkt_len;

2
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
View File

@@ -57,7 +57,7 @@ logic tx_os_valid;
logic tx_os_ready;
logic [PTP_TS_W-1:0] ptp_ts;
logic ptp_ts_cor_sync;
logic [GBX_CNT-1:0] ptp_ts_cor_sync;
logic [PTP_TS_COR_W-1:0] ptp_ts_cor_val;
logic [15:0] cfg_tx_max_pkt_len;