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lss: Refactor UART module to split out and share baud rate generation logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 23:09:19 -07:00
parent 7df14e54e5
commit 1c686391ab
5 changed files with 172 additions and 91 deletions
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117
rtl/lss/taxi_uart_rx.sv
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@@ -17,111 +17,120 @@ Authors:
*/
module taxi_uart_rx
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
input wire logic rxd,
/*
* Status
*/
output wire logic busy,
output wire logic overrun_error,
output wire logic frame_error,
output wire logic busy,
output wire logic overrun_error,
output wire logic frame_error,
/*
* Configuration
* Baud rate pulse in
*/
input wire logic [15:0] prescale
input wire logic baud_clk
);
localparam DATA_W = m_axis_rx.DATA_W;
logic [DATA_W-1:0] m_axis_tdata_reg = 0;
logic m_axis_tvalid_reg = 0;
logic m_axis_tvalid_reg = 1'b0;
logic rxd_reg = 1;
logic rxd_reg = 1'b1;
logic busy_reg = 0;
logic overrun_error_reg = 0;
logic frame_error_reg = 0;
logic overrun_error_reg = 1'b0;
logic frame_error_reg = 1'b0;
logic [DATA_W-1:0] data_reg = 0;
logic [18:0] prescale_reg = 0;
logic [3:0] bit_cnt_reg = 0;
logic [2:0] baud_cnt_reg = 0;
logic run_reg = 1'b0;
logic start_reg = 1'b0;
logic stop_reg = 1'b0;
assign m_axis_rx.tdata = m_axis_tdata_reg;
assign m_axis_rx.tkeep = 1'b1;
assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_rx.tvalid = m_axis_tvalid_reg;
assign m_axis_rx.tlast = 1'b1;
assign m_axis_rx.tid = '0;
assign m_axis_rx.tdest = '0;
assign m_axis_rx.tuser = '0;
assign busy = busy_reg;
assign busy = run_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always_ff @(posedge clk) begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
overrun_error_reg <= 1'b0;
frame_error_reg <= 1'b0;
if (m_axis_rx.tvalid && m_axis_rx.tready) begin
m_axis_tvalid_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt_reg > 0) begin
if (bit_cnt_reg > DATA_W+1) begin
if (!rxd_reg) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
end else begin
bit_cnt_reg <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt_reg > 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
data_reg <= {rxd_reg, data_reg[DATA_W-1:1]};
end else if (bit_cnt_reg == 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
if (!baud_clk) begin
// wait
end else if (baud_cnt_reg != 0) begin
baud_cnt_reg <= baud_cnt_reg - 1;
end else if (run_reg) begin
start_reg <= 1'b0;
if (start_reg) begin
// wait bit period for start bit
baud_cnt_reg <= '1;
if (rxd_reg) begin
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1;
overrun_error_reg <= m_axis_tvalid_reg;
// start bit high, clear run bit
run_reg <= 1'b0;
frame_error_reg <= 1'b1;
end
end else begin
{data_reg, stop_reg} <= {rxd_reg, data_reg};
if (stop_reg) begin
run_reg <= 1'b0;
if (rxd_reg) begin
// stop bit high, transfer data
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1'b1;
overrun_error_reg <= m_axis_tvalid_reg;
end else begin
// stop bit low
frame_error_reg <= 1'b1;
end
end else begin
frame_error_reg <= 1;
baud_cnt_reg <= '1;
end
end
end else begin
busy_reg <= 0;
data_reg <= {1'b1, {DATA_W-1{1'b0}}}; // marker bit
start_reg <= 1'b1;
stop_reg <= 1'b0;
if (!rxd_reg) begin
prescale_reg <= {prescale, 2'd0}-2;
bit_cnt_reg <= DATA_W+2;
data_reg <= 0;
busy_reg <= 1;
// falling edge of start bit
// wait half bit period
baud_cnt_reg <= 3'b011;
run_reg <= 1'b1;
end
end
if (rst) begin
m_axis_tdata_reg <= 0;
m_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt_reg <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
rxd_reg <= 1'b1;
run_reg <= 1'b0;
overrun_error_reg <= 1'b0;
frame_error_reg <= 1'b0;
end
end