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lss: Refactor UART module to split out and share baud rate generation logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 23:09:19 -07:00
parent 7df14e54e5
commit 1c686391ab
5 changed files with 172 additions and 91 deletions
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62
rtl/lss/taxi_uart_tx.sv
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@@ -17,40 +17,40 @@ Authors:
*/
module taxi_uart_tx
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
taxi_axis_if.snk s_axis_tx,
/*
* UART interface
*/
output wire logic txd,
output wire logic txd,
/*
* Status
*/
output wire logic busy,
output wire logic busy,
/*
* Configuration
* Baud rate pulse in
*/
input wire logic [15:0] prescale
input wire logic baud_clk
);
localparam DATA_W = s_axis_tx.DATA_W;
logic s_axis_tready_reg = 0;
logic s_axis_tready_reg = 1'b0;
logic txd_reg = 1;
logic txd_reg = 1'b1;
logic busy_reg = 0;
logic busy_reg = 1'b0;
logic [DATA_W:0] data_reg = 0;
logic [18:0] prescale_reg = 0;
logic [2:0] baud_cnt_reg = 0;
logic [3:0] bit_cnt_reg = 0;
assign s_axis_tx.tready = s_axis_tready_reg;
@@ -60,39 +60,35 @@ assign txd = txd_reg;
assign busy = busy_reg;
always_ff @(posedge clk) begin
if (prescale_reg > 0) begin
s_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
s_axis_tready_reg <= 1'b0;
if (!baud_clk) begin
// wait
end else if (baud_cnt_reg != 0) begin
baud_cnt_reg <= baud_cnt_reg - 1;
end else if (bit_cnt_reg == 0) begin
s_axis_tready_reg <= 1;
busy_reg <= 0;
busy_reg <= 1'b0;
if (s_axis_tx.tvalid) begin
s_axis_tready_reg <= !s_axis_tready_reg;
prescale_reg <= {prescale, 3'd0}-1;
s_axis_tready_reg <= 1'b1;
baud_cnt_reg <= '1;
bit_cnt_reg <= DATA_W+1;
data_reg <= {1'b1, s_axis_tx.tdata};
txd_reg <= 0;
busy_reg <= 1;
txd_reg <= 1'b0;
busy_reg <= 1'b1;
end
end else begin
if (bit_cnt_reg > 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt_reg == 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
txd_reg <= 1;
end
{data_reg, txd_reg} <= {1'b0, data_reg};
baud_cnt_reg <= '1;
bit_cnt_reg <= bit_cnt_reg - 1;
end
if (rst) begin
s_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
s_axis_tready_reg <= 1'b0;
txd_reg <= 1'b1;
baud_cnt_reg <= 0;
bit_cnt_reg <= 0;
busy_reg <= 0;
busy_reg <= 1'b0;
end
end