From 1fe508a6bf17edbb29bce9a8477be615b1012789 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 6 Apr 2026 23:59:16 -0700 Subject: [PATCH] Update readme Signed-off-by: Alex Forencich --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 184aac1..ad6e3ee 100644 --- a/README.md +++ b/README.md @@ -232,6 +232,10 @@ Example designs are provided for several different FPGA boards, showcasing many * HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * Opal Kelley XEM8320 (Xilinx Artix UltraScale+ XCAU25P) +* Napatech NT20E3 (Xilinx Virtex 7 XC7V330T) +* Napatech NT40E3 (Xilinx Virtex 7 XC7V330T) +* Napatech NT200A01 (Xilinx Virtex UltraScale XCVU095) +* Napatech NT200A02 (Xilinx Virtex UltraScale+ XCVU5P) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)