From 20f14ace974f0f9c75e94ddaf4d3bbc3b98b9757 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 6 Sep 2025 07:06:50 -0700 Subject: [PATCH] Update readme Signed-off-by: Alex Forencich --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 634b7ad..9ddb736 100644 --- a/README.md +++ b/README.md @@ -142,6 +142,8 @@ Example designs are provided for several different FPGA boards, showcasing many * Digilent Arty A7 (Xilinx Artix 7 XC7A35T) * HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) * HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) +* HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) +* HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)