From 23279469c99ec0318319d369a3ab53c8982221e9 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 13 Mar 2026 00:21:58 -0700 Subject: [PATCH] cndm: Add support for DNPCIe-40G-KU-LL-2QSFP Signed-off-by: Alex Forencich --- .../DNPCIe_40G_KU_LL_2QSFP/fpga/README.md | 35 + .../fpga/common/vivado.mk | 153 +++ .../DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc | 532 ++++++++++ .../fpga/fpga_ku040/Makefile | 97 ++ .../fpga/fpga_ku040/config.tcl | 131 +++ .../fpga/fpga_ku060/Makefile | 97 ++ .../fpga/fpga_ku060/config.tcl | 131 +++ .../fpga/ip/pcie3_ultrascale_0.tcl | 29 + .../DNPCIe_40G_KU_LL_2QSFP/fpga/lib/taxi | 1 + .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.sv | 936 ++++++++++++++++++ .../fpga/rtl/fpga_core.sv | 846 ++++++++++++++++ .../fpga/tb/fpga_core/Makefile | 73 ++ .../fpga/tb/fpga_core/baser.py | 1 + .../fpga/tb/fpga_core/cndm.py | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 495 +++++++++ .../fpga/tb/fpga_core/test_fpga_core.sv | 345 +++++++ 16 files changed, 3903 insertions(+) create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/common/vivado.mk create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl create mode 120000 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/lib/taxi create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.sv create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile create mode 120000 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/baser.py create mode 120000 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/cndm.py create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py create mode 100644 src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.sv diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md new file mode 100644 index 0000000..0b97be9 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md @@ -0,0 +1,35 @@ +# Corundum for DNPCIe-40G-KU-LL-2QSFP + +## Introduction + +This design targets the Dini Group DNPCIe-40G-KU-LL-2QSFP FPGA board. + +* USB UART + * XFCP (3 Mbaud) +* QSFP+ + * 10GBASE-R MACs via GTH transceivers + +## Board details + +* FPGA: xcku040-ffva1156-2-e or xcku060-ffva1156-2-e +* USB UART: FTDI FT2232HQ +* PCIe: gen 3 x8 (~64 Gbps) +* Reference oscillator: Fixed 156.25 MHz from Si534 +* 10GBASE-R PHY: Soft PCS with GTH transceivers + +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +On the host system, run `make` in `modules/cndm` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled. + +## How to test + +Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm.ko`. Check `dmesg` for output from driver initialization. Run `cndm_ddcmd.sh =p` to enable all debug messages. diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/common/vivado.mk b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc new file mode 100644 index 0000000..29bd281 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc @@ -0,0 +1,532 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2014-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the DNPCIe_40G_KU_LL_2QSFP +# part: xcku040-ffva1156-2-e +# part: xcku060-ffva1156-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] +set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# LEDs +set_property -dict {LOC H22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[0]}] +set_property -dict {LOC E20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[1]}] +set_property -dict {LOC F22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[2]}] +set_property -dict {LOC G22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[3]}] +set_property -dict {LOC F12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[4]}] +set_property -dict {LOC F10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[5]}] +set_property -dict {LOC D10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[6]}] +set_property -dict {LOC AK33 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {user_led[7]}] + +set_property -dict {LOC AG14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_led_green}] +set_property -dict {LOC AP14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_led_red}] +set_property -dict {LOC AH29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_led_green}] +set_property -dict {LOC AL33 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_led_red}] + +set_false_path -to [get_ports {user_led[*] qsfp0_led_green qsfp0_led_red qsfp1_led_green qsfp1_led_red}] +set_output_delay 0 [get_ports {user_led[*] qsfp0_led_green qsfp0_led_red qsfp1_led_green qsfp1_led_red}] + +# Reset button +#set_property -dict {LOC N21 IOSTANDARD LVCMOS12} [get_ports reset] + +#set_false_path -from [get_ports {reset}] +#set_input_delay 0 [get_ports {reset}] + +# GPIO + +# DNCPU +#set_property -dict {LOC Y26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[0]] ;# J10.1 +#set_property -dict {LOC AA22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[1]] ;# J10.2 +#set_property -dict {LOC Y27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[2]] ;# J10.3 +#set_property -dict {LOC AB22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[3]] ;# J10.4 +#set_property -dict {LOC AD25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[4]] ;# J10.5 +#set_property -dict {LOC AC22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[5]] ;# J10.6 +#set_property -dict {LOC AD26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[6]] ;# J10.7 +#set_property -dict {LOC AC23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[7]] ;# J10.8 +#set_property -dict {LOC AB24 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[8]] ;# J10.9 +#set_property -dict {LOC AA20 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[9]] ;# J10.10 +#set_property -dict {LOC AC24 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[10]] ;# J10.11 +#set_property -dict {LOC AB20 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[11]] ;# J10.12 +#set_property -dict {LOC AC26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[12]] ;# J10.13 +#set_property -dict {LOC AB21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[13]] ;# J10.14 +#set_property -dict {LOC AC27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[14]] ;# J10.15 +#set_property -dict {LOC AC21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[15]] ;# J10.16 +#set_property -dict {LOC AA27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[16]] ;# J10.17 +#set_property -dict {LOC Y23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[17]] ;# J10.18 +#set_property -dict {LOC AB27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[18]] ;# J10.19 +#set_property -dict {LOC AA23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[19]] ;# J10.20 +#set_property -dict {LOC AB25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[20]] ;# J10.21 +#set_property -dict {LOC AA24 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[21]] ;# J10.22 +#set_property -dict {LOC AB26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[22]] ;# J10.23 +#set_property -dict {LOC AA25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[23]] ;# J10.24 +#set_property -dict {LOC AA28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[24]] ;# J10.25 +#set_property -dict {LOC Y22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[25]] ;# J10.26 +#set_property -dict {LOC W23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[26]] ;# J10.27 +#set_property -dict {LOC V27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[27]] ;# J10.28 +#set_property -dict {LOC W24 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[28]] ;# J10.29 +#set_property -dict {LOC V28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[29]] ;# J10.30 +#set_property -dict {LOC W25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[30]] ;# J10.31 +#set_property -dict {LOC U24 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[31]] ;# J10.32 +#set_property -dict {LOC Y25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[32]] ;# J10.33 +#set_property -dict {LOC U25 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[33]] ;# J10.34 +#set_property -dict {LOC U21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[34]] ;# J10.35 +#set_property -dict {LOC W28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[35]] ;# J10.36 +#set_property -dict {LOC U22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[36]] ;# J10.37 +#set_property -dict {LOC Y28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[37]] ;# J10.38 +#set_property -dict {LOC V22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[38]] ;# J10.39 +#set_property -dict {LOC U26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[39]] ;# J10.40 +#set_property -dict {LOC V23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[40]] ;# J10.41 +#set_property -dict {LOC U27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[41]] ;# J10.42 +#set_property -dict {LOC T22 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[42]] ;# J10.43 +#set_property -dict {LOC V29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[43]] ;# J10.44 +#set_property -dict {LOC T23 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[44]] ;# J10.45 +#set_property -dict {LOC W29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[45]] ;# J10.46 +#set_property -dict {LOC V21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[46]] ;# J10.47 +#set_property -dict {LOC V26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[47]] ;# J10.48 +#set_property -dict {LOC W21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[48]] ;# J10.49 +#set_property -dict {LOC W26 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[49]] ;# J10.50 +#set_property -dict {LOC Y21 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[50]] ;# J10.51 +#set_property -dict {LOC U29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_a[51]] ;# J10.52 + +#set_property -dict {LOC AE27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[0]] ;# J10.121 +#set_property -dict {LOC AG31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[1]] ;# J10.122 +#set_property -dict {LOC AF27 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[2]] ;# J10.123 +#set_property -dict {LOC AG32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[3]] ;# J10.124 +#set_property -dict {LOC AE28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[4]] ;# J10.125 +#set_property -dict {LOC AF33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[5]] ;# J10.126 +#set_property -dict {LOC AF28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[6]] ;# J10.127 +#set_property -dict {LOC AG34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[7]] ;# J10.128 +#set_property -dict {LOC AC28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[8]] ;# J10.129 +#set_property -dict {LOC AE32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[9]] ;# J10.130 +#set_property -dict {LOC AD28 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[10]] ;# J10.131 +#set_property -dict {LOC AF32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[11]] ;# J10.132 +#set_property -dict {LOC AF29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[12]] ;# J10.133 +#set_property -dict {LOC AE33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[13]] ;# J10.134 +#set_property -dict {LOC AG29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[14]] ;# J10.135 +#set_property -dict {LOC AF34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[15]] ;# J10.136 +#set_property -dict {LOC AD29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[16]] ;# J10.137 +#set_property -dict {LOC AD30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[17]] ;# J10.138 +#set_property -dict {LOC AE30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[18]] ;# J10.139 +#set_property -dict {LOC AD31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[19]] ;# J10.140 +#set_property -dict {LOC AF30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[20]] ;# J10.141 +#set_property -dict {LOC AC31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[21]] ;# J10.142 +#set_property -dict {LOC AG30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[22]] ;# J10.143 +#set_property -dict {LOC AC32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[23]] ;# J10.144 +#set_property -dict {LOC AC29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[24]] ;# J10.145 +#set_property -dict {LOC AE31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[25]] ;# J10.146 +#set_property -dict {LOC AA32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[26]] ;# J10.147 +#set_property -dict {LOC W33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[27]] ;# J10.148 +#set_property -dict {LOC AB32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[28]] ;# J10.149 +#set_property -dict {LOC Y33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[29]] ;# J10.150 +#set_property -dict {LOC AB30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[30]] ;# J10.151 +#set_property -dict {LOC W30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[31]] ;# J10.152 +#set_property -dict {LOC AB31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[32]] ;# J10.153 +#set_property -dict {LOC Y30 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[33]] ;# J10.154 +#set_property -dict {LOC AC34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[34]] ;# J10.155 +#set_property -dict {LOC V33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[35]] ;# J10.156 +#set_property -dict {LOC AD34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[36]] ;# J10.157 +#set_property -dict {LOC W34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[37]] ;# J10.158 +#set_property -dict {LOC AA29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[38]] ;# J10.159 +#set_property -dict {LOC Y31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[39]] ;# J10.160 +#set_property -dict {LOC AB29 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[40]] ;# J10.161 +#set_property -dict {LOC Y32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[41]] ;# J10.162 +#set_property -dict {LOC AA34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[42]] ;# J10.163 +#set_property -dict {LOC U34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[43]] ;# J10.164 +#set_property -dict {LOC AB34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[44]] ;# J10.165 +#set_property -dict {LOC V34 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[45]] ;# J10.166 +#set_property -dict {LOC AC33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[46]] ;# J10.167 +#set_property -dict {LOC V31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[47]] ;# J10.168 +#set_property -dict {LOC AD33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[48]] ;# J10.169 +#set_property -dict {LOC W31 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[49]] ;# J10.170 +#set_property -dict {LOC AA33 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[50]] ;# J10.171 +#set_property -dict {LOC V32 IOSTANDARD LVCMOS12} [get_ports gpio_j10_b[51]] ;# J10.172 + +# UART +set_property -dict {LOC F20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC G20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] + +set_false_path -to [get_ports {uart_txd}] +set_output_delay 0 [get_ports {uart_txd}] +set_false_path -from [get_ports {uart_rxd}] +set_input_delay 0 [get_ports {uart_rxd}] + +# QSFP Interfaces +set_property -dict {LOC Y2 } [get_ports {qsfp0_rx_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC Y1 } [get_ports {qsfp0_rx_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC AA4 } [get_ports {qsfp0_tx_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC AA3 } [get_ports {qsfp0_tx_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC V2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTHRXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC V1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTHRXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC W4 } [get_ports {qsfp0_tx_p[1]}] ;# MGTHTXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC W3 } [get_ports {qsfp0_tx_n[1]}] ;# MGTHTXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports {qsfp0_rx_p[2]}] ;# MGTHRXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports {qsfp0_rx_n[2]}] ;# MGTHRXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC U4 } [get_ports {qsfp0_tx_p[2]}] ;# MGTHTXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports {qsfp0_tx_n[2]}] ;# MGTHTXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTHRXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTHRXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports {qsfp0_tx_p[3]}] ;# MGTHTXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports {qsfp0_tx_n[3]}] ;# MGTHTXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11 +set_property -dict {LOC V6 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_226 from Y5.4 +set_property -dict {LOC V5 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_226 from Y5.5 +set_property -dict {LOC AJ11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {qsfp0_fs[0]}] ;# to Y5.8 +set_property -dict {LOC AF10 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {qsfp0_fs[1]}] ;# to Y5.7 +set_property -dict {LOC AJ13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp0_modsell] +set_property -dict {LOC AE12 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp0_resetl] +set_property -dict {LOC AE26 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] +set_property -dict {LOC AE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] +set_property -dict {LOC AF12 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp0_lpmode] +#set_property -dict {LOC AD11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp0_i2c_scl] +#set_property -dict {LOC AE11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp0_i2c_sda] + +# 156.25 MHz MGT reference clock (from Y5 Si534 FB000184G, FS = 0b00) +create_clock -period 6.400 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p] + +# 200 MHz MGT reference clock (from Y5 Si534 FB000184G, FS = 0b01) +#create_clock -period 5.000 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p] + +# 250 MHz MGT reference clock (from Y5 Si534 FB000184G, FS = 0b10) +#create_clock -period 4.000 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p] + +# 312.5 MHz MGT reference clock (from Y5 Si534 FB000184G, FS = 0b11) +#create_clock -period 3.200 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_fs[*]}] +set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_fs[*]}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] + +#set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +#set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +#set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] +#set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}] + +set_property -dict {LOC M2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC M1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC N4 } [get_ports {qsfp1_tx_p[0]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC N3 } [get_ports {qsfp1_tx_n[0]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC K2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC K1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC L4 } [get_ports {qsfp1_tx_p[1]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC L3 } [get_ports {qsfp1_tx_n[1]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC H2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC H1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC J4 } [get_ports {qsfp1_tx_p[2]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC J3 } [get_ports {qsfp1_tx_n[2]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC F2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC F1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC G4 } [get_ports {qsfp1_tx_p[3]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2 +set_property -dict {LOC G3 } [get_ports {qsfp1_tx_n[3]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2 +#set_property -dict {LOC P6 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_227 from Y4.4 +#set_property -dict {LOC P5 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_227 from Y4.5 +set_property -dict {LOC AG11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {qsfp1_fs[0]}] ;# to Y4.8 +set_property -dict {LOC AH11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {qsfp1_fs[1]}] ;# to Y4.7 +set_property -dict {LOC AK13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp1_modsell] +set_property -dict {LOC AL13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp1_resetl] +set_property -dict {LOC AM9 IOSTANDARD LVCMOS25 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC AH13 IOSTANDARD LVCMOS25 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC AK11 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp1_lpmode] +#set_property -dict {LOC AE13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp1_i2c_scl] +#set_property -dict {LOC AF13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp1_i2c_sda] + +# 156.25 MHz MGT reference clock (from Y4 Si534 FB000184G, FS = 0b00) +#create_clock -period 6.400 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p] + +# 200 MHz MGT reference clock (from Y4 Si534 FB000184G, FS = 0b01) +#create_clock -period 5.000 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p] + +# 250 MHz MGT reference clock (from Y4 Si534 FB000184G, FS = 0b10) +#create_clock -period 4.000 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p] + +# 312.5 MHz MGT reference clock (from Y4 Si534 FB000184G, FS = 0b11) +#create_clock -period 3.200 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_fs[*]}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_fs[*]}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +#set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +#set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +#set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] +#set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}] + +# I2C EEPROM +#set_property -dict {LOC AG9 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl] +#set_property -dict {LOC AE8 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda] + +#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] +#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] + +# QSPI flash +#set_property -dict {LOC AF8 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_clk}] +#set_property -dict {LOC AD10 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_dq[0]}] +#set_property -dict {LOC AH8 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_dq[1]}] +#set_property -dict {LOC AE10 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_dq[2]}] +#set_property -dict {LOC AD9 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_dq[3]}] +#set_property -dict {LOC AH9 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_cs}] +#set_property -dict {LOC AD8 IOSTANDARD LVCMOS25 DRIVE 12 PULLUP true} [get_ports {qspi_reset}] + +# PCIe Interface +set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AE4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AE3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AG4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AG3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AH6 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AH5 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AK6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AK5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AL4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AL3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AM6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AM5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AN4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AN3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AF6 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_224 from U80 ICS 1S1022EL +set_property -dict {LOC AF5 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_224 from U80 ICS 1S1022EL +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] + +set_false_path -from [get_ports {pcie_reset_n}] +set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 +# 9x MT40A512M8RH-083E +# Control +#set_property -dict {LOC AG17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] ;# IO_L15P_T2L_N4_AD11P_45 +#set_property -dict {LOC AH16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] ;# IO_L14P_T2L_N2_GC_45 +#set_property -dict {LOC AF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] ;# IO_L20P_T3L_N2_AD1P_45 +#set_property -dict {LOC AJ16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] ;# IO_L14N_T2L_N3_GC_45 +#set_property -dict {LOC AH19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] ;# IO_L17N_T2U_N9_AD10N_45 +#set_property -dict {LOC AJ15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] ;# IO_L16P_T2U_N6_QBC_AD3P_45 +#set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] ;# IO_L21P_T3L_N4_AD8P_45 +#set_property -dict {LOC AG15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] ;# IO_L18P_T2U_N10_AD2P_45 +#set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] ;# IO_L19N_T3L_N1_DBC_AD9N_45 +#set_property -dict {LOC AF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] ;# IO_L20N_T3L_N3_AD1N_45 +#set_property -dict {LOC AJ18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] ;# IO_L11P_T1U_N8_GC_45 +#set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] ;# IO_L19P_T3L_N0_DBC_AD9P_45 +#set_property -dict {LOC AK16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] ;# IO_L12N_T1U_N11_GC_45 +#set_property -dict {LOC AG16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] ;# IO_L15N_T2L_N5_AD11N_45 +#set_property -dict {LOC AJ19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] ;# IO_T1U_N12_45 +#set_property -dict {LOC AL17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] ;# IO_L10N_T1U_N7_QBC_AD4N_45 +#set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] ;# IO_L7P_T1L_N0_QBC_AD13P_45 +#set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] ;# IO_L21N_T3L_N5_AD8N_45 +#set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_45 +#set_property -dict {LOC AG19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] ;# IO_L17P_T2U_N8_AD10P_45 +#set_property -dict {LOC AK15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[1]}] ;# IO_L9P_T1L_N4_AD12P_45 +#set_property -dict {LOC AE17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] ;# IO_L23P_T3U_N8_45 +#set_property -dict {LOC AF17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] ;# IO_L23N_T3U_N9_45 +#set_property -dict {LOC AL18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] ;# IO_L10P_T1U_N6_QBC_AD4P_45 +#set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] ;# IO_L9N_T1L_N5_AD12N_45 +#set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] ;# IO_L12P_T1U_N10_GC_45 +#set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] ;# IO_L8N_T1L_N3_AD5N_45 +#set_property -dict {LOC AE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] ;# IO_L22P_T3U_N6_DBC_AD0P_45 +#set_property -dict {LOC AD16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] ;# IO_L24P_T3U_N10_45 +#set_property -dict {LOC AD15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_alert_n}] ;# IO_L24N_T3U_N11_45 +#set_property -dict {LOC AD14 IOSTANDARD LVCMOS12 } [get_ports {ddr4_ten}] ;# IO_T3U_N12_45 +# U30 +#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# IO_L1P_T0L_N0_DBC_44 to U30.DM_DBI_n +#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# IO_L2P_T0L_N2_44 to U30.DQ[7:0] +#set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# IO_L2N_T0L_N3_44 to U30.DQ[7:0] +#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# IO_L3P_T0L_N4_AD15P_44 to U30.DQ[7:0] +#set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# IO_L3N_T0L_N5_AD15N_44 to U30.DQ[7:0] +#set_property -dict {LOC AG21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# IO_L4P_T0U_N6_DBC_AD7P_44 to U30.DQS_t +#set_property -dict {LOC AH21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# IO_L4N_T0U_N7_DBC_AD7N_44 to U30.DQS_c +#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# IO_L5P_T0U_N8_AD14P_44 to U30.DQ[7:0] +#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# IO_L5N_T0U_N9_AD14N_44 to U30.DQ[7:0] +#set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# IO_L6P_T0U_N10_AD6P_44 to U30.DQ[7:0] +#set_property -dict {LOC AG22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# IO_L6N_T0U_N11_AD6N_44 to U30.DQ[7:0] +# U31 +#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# IO_L13P_T2L_N0_GC_QBC_44 to U31.DM_DBI_n +#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# IO_L14P_T2L_N2_GC_44 to U31.DQ[7:0] +#set_property -dict {LOC AK23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# IO_L14N_T2L_N3_GC_44 to U31.DQ[7:0] +#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# IO_L15P_T2L_N4_AD11P_44 to U31.DQ[7:0] +#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# IO_L15N_T2L_N5_AD11N_44 to U31.DQ[7:0] +#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# IO_L16P_T2U_N6_QBC_AD3P_44 to U31.DQS_t +#set_property -dict {LOC AK20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_44 to U31.DQS_c +#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# IO_L17P_T2U_N8_AD10P_44 to U31.DQ[7:0] +#set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# IO_L17N_T2U_N9_AD10N_44 to U31.DQ[7:0] +#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# IO_L18P_T2U_N10_AD2P_44 to U31.DQ[7:0] +#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# IO_L18N_T2U_N11_AD2N_44 to U31.DQ[7:0] +# U32 +#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# IO_L1P_T0L_N0_DBC_46 to U32.DM_DBI_n +#set_property -dict {LOC AM26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# IO_L2P_T0L_N2_46 to U32.DQ[7:0] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# IO_L2N_T0L_N3_46 to U32.DQ[7:0] +#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# IO_L3P_T0L_N4_AD15P_46 to U32.DQ[7:0] +#set_property -dict {LOC AK27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# IO_L3N_T0L_N5_AD15N_46 to U32.DQ[7:0] +#set_property -dict {LOC AL27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# IO_L4P_T0U_N6_DBC_AD7P_46 to U32.DQS_t +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# IO_L4N_T0U_N7_DBC_AD7N_46 to U32.DQS_c +#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# IO_L5P_T0U_N8_AD14P_46 to U32.DQ[7:0] +#set_property -dict {LOC AH28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# IO_L5N_T0U_N9_AD14N_46 to U32.DQ[7:0] +#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# IO_L6P_T0U_N10_AD6P_46 to U32.DQ[7:0] +#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# IO_L6N_T0U_N11_AD6N_46 to U32.DQ[7:0] +# U33 +#set_property -dict {LOC AN26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# IO_L7P_T1L_N0_QBC_AD13P_46 to U33.DM_DBI_n +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# IO_L8P_T1L_N2_AD5P_46 to U33.DQ[7:0] +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# IO_L8N_T1L_N3_AD5N_46 to U33.DQ[7:0] +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# IO_L9P_T1L_N4_AD12P_46 to U33.DQ[7:0] +#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# IO_L9N_T1L_N5_AD12N_46 to U33.DQ[7:0] +#set_property -dict {LOC AN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# IO_L10P_T1U_N6_QBC_AD4P_46 to U33.DQS_t +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# IO_L10N_T1U_N7_QBC_AD4N_46 to U33.DQS_c +#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# IO_L11P_T1U_N8_GC_46 to U33.DQ[7:0] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# IO_L11N_T1U_N9_GC_46 to U33.DQ[7:0] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# IO_L12P_T1U_N10_GC_46 to U33.DQ[7:0] +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# IO_L12N_T1U_N11_GC_46 to U33.DQ[7:0] +# U83 +#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# IO_L1P_T0L_N0_DBC_45 to U83.DM_DBI_n +#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# IO_L2P_T0L_N2_45 to U83.DQ[7:0] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# IO_L2N_T0L_N3_45 to U83.DQ[7:0] +#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# IO_L3P_T0L_N4_AD15P_45 to U83.DQ[7:0] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# IO_L3N_T0L_N5_AD15N_45 to U83.DQ[7:0] +#set_property -dict {LOC AN18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] ;# IO_L4P_T0U_N6_DBC_AD7P_45 to U83.DQS_t +#set_property -dict {LOC AN17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] ;# IO_L4N_T0U_N7_DBC_AD7N_45 to U83.DQS_c +#set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# IO_L5P_T0U_N8_AD14P_45 to U83.DQ[7:0] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# IO_L5N_T0U_N9_AD14N_45 to U83.DQ[7:0] +#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# IO_L6P_T0U_N10_AD6P_45 to U83.DQ[7:0] +#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# IO_L6N_T0U_N11_AD6N_45 to U83.DQ[7:0] +# U86 +#set_property -dict {LOC AM21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# IO_L19P_T3L_N0_DBC_AD9P_44 to U86.DM_DBI_n +#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# IO_L20P_T3L_N2_AD1P_44 to U86.DQ[7:0] +#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# IO_L20N_T3L_N3_AD1N_44 to U86.DQ[7:0] +#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# IO_L21P_T3L_N4_AD8P_44 to U86.DQ[7:0] +#set_property -dict {LOC AN24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# IO_L21N_T3L_N5_AD8N_44 to U86.DQ[7:0] +#set_property -dict {LOC AP20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] ;# IO_L22P_T3U_N6_DBC_AD0P_44 to U86.DQS_t +#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] ;# IO_L22N_T3U_N7_DBC_AD0N_44 to U86.DQS_c +#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# IO_L23P_T3U_N8_44 to U86.DQ[7:0] +#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# IO_L23N_T3U_N9_44 to U86.DQ[7:0] +#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# IO_L24P_T3U_N10_44 to U86.DQ[7:0] +#set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# IO_L24N_T3U_N11_44 to U86.DQ[7:0] +# U87 +#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# IO_L7P_T1L_N0_QBC_AD13P_44 to U87.DM_DBI_n +#set_property -dict {LOC AF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# IO_L8P_T1L_N2_AD5P_44 to U87.DQ[7:0] +#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# IO_L8N_T1L_N3_AD5N_44 to U87.DQ[7:0] +#set_property -dict {LOC AG24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# IO_L9P_T1L_N4_AD12P_44 to U87.DQ[7:0] +#set_property -dict {LOC AG25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# IO_L9N_T1L_N5_AD12N_44 to U87.DQ[7:0] +#set_property -dict {LOC AH24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] ;# IO_L10P_T1U_N6_QBC_AD4P_44 to U87.DQS_t +#set_property -dict {LOC AJ25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] ;# IO_L10N_T1U_N7_QBC_AD4N_44 to U87.DQS_c +#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# IO_L11P_T1U_N8_GC_44 to U87.DQ[7:0] +#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# IO_L11N_T1U_N9_GC_44 to U87.DQ[7:0] +#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# IO_L12P_T1U_N10_GC_44 to U87.DQ[7:0] +#set_property -dict {LOC AH23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# IO_L12N_T1U_N11_GC_44 to U87.DQ[7:0] +# U88 +#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# IO_L13P_T2L_N0_GC_QBC_46 to U88.DM_DBI_n +#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# IO_L14P_T2L_N2_GC_46 to U88.DQ[7:0] +#set_property -dict {LOC AK32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# IO_L14N_T2L_N3_GC_46 to U88.DQ[7:0] +#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# IO_L15P_T2L_N4_AD11P_46 to U88.DQ[7:0] +#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# IO_L15N_T2L_N5_AD11N_46 to U88.DQ[7:0] +#set_property -dict {LOC AH33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] ;# IO_L16P_T2U_N6_QBC_AD3P_46 to U88.DQS_t +#set_property -dict {LOC AJ33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] ;# IO_L16N_T2U_N7_QBC_AD3N_46 to U88.DQS_c +#set_property -dict {LOC AH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# IO_L17P_T2U_N8_AD10P_46 to U88.DQ[7:0] +#set_property -dict {LOC AH32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# IO_L17N_T2U_N9_AD10N_46 to U88.DQ[7:0] +#set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# IO_L18P_T2U_N10_AD2P_46 to U88.DQ[7:0] +#set_property -dict {LOC AJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# IO_L18N_T2U_N11_AD2N_46 to U88.DQ[7:0] +# U89 +#set_property -dict {LOC AL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] ;# IO_L19P_T3L_N0_DBC_AD9P_46 to U89.DM_DBI_n +#set_property -dict {LOC AN33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] ;# IO_L20P_T3L_N2_AD1P_46 to U89.DQ[7:0] +#set_property -dict {LOC AP33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] ;# IO_L20N_T3L_N3_AD1N_46 to U89.DQ[7:0] +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] ;# IO_L21P_T3L_N4_AD8P_46 to U89.DQ[7:0] +#set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] ;# IO_L21N_T3L_N5_AD8N_46 to U89.DQ[7:0] +#set_property -dict {LOC AN34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}] ;# IO_L22P_T3U_N6_DBC_AD0P_46 to U89.DQS_t +#set_property -dict {LOC AP34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}] ;# IO_L22N_T3U_N7_DBC_AD0N_46 to U89.DQS_c +#set_property -dict {LOC AM32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] ;# IO_L23P_T3U_N8_46 to U89.DQ[7:0] +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] ;# IO_L23N_T3U_N9_46 to U89.DQ[7:0] +#set_property -dict {LOC AL34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] ;# IO_L24P_T3U_N10_46 to U89.DQ[7:0] +#set_property -dict {LOC AM34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] ;# IO_L24N_T3U_N11_46 to U89.DQ[7:0] + +# 200 MHz DDR4 clock (Si598 FCA000126G) (Y6) +set_property -dict {LOC AH18 IOSTANDARD LVDS} [get_ports clk_ddr4_p] ;# from Y6.4 +set_property -dict {LOC AH17 IOSTANDARD LVDS} [get_ports clk_ddr4_n] ;# from Y6.5 +create_clock -period 5.000 -name clk_ddr4 [get_ports clk_ddr4_p] + +#set_property -dict {LOC AG12 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports clk_ddr4_i2c_scl] +#set_property -dict {LOC AH12 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports clk_ddr4_i2c_sda] + +# 200 MHz RLD3 clock (Si598 FCA000126G) (Y3) +#set_property -dict {LOC D23 IOSTANDARD LVDS} [get_ports clk_rld3_p] ;# from Y3.4 +#set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_rld3_n] ;# from Y3.5 +#create_clock -period 5.000 -name clk_rld3 [get_ports clk_rld3_p] + +#set_property -dict {LOC AG10 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports clk_rld3_i2c_scl] +#set_property -dict {LOC AF9 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports clk_rld3_i2c_sda] + +# BPI flash +set_property -dict {LOC M20 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}] +set_property -dict {LOC L20 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}] +set_property -dict {LOC R21 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}] +set_property -dict {LOC R22 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}] +set_property -dict {LOC P20 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}] +set_property -dict {LOC P21 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}] +set_property -dict {LOC N22 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}] +set_property -dict {LOC M22 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}] +set_property -dict {LOC R23 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}] +set_property -dict {LOC P23 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}] +set_property -dict {LOC R25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}] +set_property -dict {LOC R26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}] +set_property -dict {LOC T24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}] +set_property -dict {LOC T25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}] +set_property -dict {LOC T27 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}] +set_property -dict {LOC R27 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}] +set_property -dict {LOC P24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}] +set_property -dict {LOC P25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}] +set_property -dict {LOC P26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}] +set_property -dict {LOC N26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}] +set_property -dict {LOC N24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}] +set_property -dict {LOC M24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}] +set_property -dict {LOC M25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}] +set_property -dict {LOC M26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}] +set_property -dict {LOC L25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}] +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}] +set_property -dict {LOC M27 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}] +set_property -dict {LOC L27 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}] +set_property -dict {LOC J23 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}] +set_property -dict {LOC H24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}] +set_property -dict {LOC J26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}] +set_property -dict {LOC H26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[23]}] +set_property -dict {LOC J24 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_region[0]}] +set_property -dict {LOC J25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_region[1]}] +set_property -dict {LOC G25 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}] +set_property -dict {LOC G26 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}] +set_property -dict {LOC N27 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}] + +set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_oe_n flash_we_n flash_adv_n}] +set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_oe_n flash_we_n flash_adv_n}] +set_false_path -from [get_ports {flash_dq[*]}] +set_input_delay 0 [get_ports {flash_dq[*]}] diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile new file mode 100644 index 0000000..b8a9bd2 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku040-ffva1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexu + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES += ../ip/pcie3_ultrascale_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl new file mode 100644 index 0000000..9943b6c --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x3822093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x17df] +set board_device_id [expr 0x1a00] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# PCIe IP core settings +set pcie [get_ips pcie3_ultrascale_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile new file mode 100644 index 0000000..78ef23b --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku060-ffva1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexu + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES += ../ip/pcie3_ultrascale_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl new file mode 100644 index 0000000..5677c1c --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x3919093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x17df] +set board_device_id [expr 0x1a00] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# PCIe IP core settings +set pcie [get_ips pcie3_ultrascale_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl new file mode 100644 index 0000000..6bc6e7b --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl @@ -0,0 +1,29 @@ + +create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ + CONFIG.pf0_class_code_base {02} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_class_code_interface {00} \ + CONFIG.PF0_DEVICE_ID {C001} \ + CONFIG.PF0_SUBSYSTEM_ID {1a00} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {17df} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_msi_enabled {true} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.en_msi_per_vec_masking {true} \ + CONFIG.ext_pcie_cfg_space_enabled {true} \ + CONFIG.vendor_id {1234} \ + CONFIG.mode_selection {Advanced} \ +] [get_ips pcie3_ultrascale_0] diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/lib/taxi b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.sv b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.sv new file mode 100644 index 0000000..bc17587 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.sv @@ -0,0 +1,936 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "kintexu", + + // FW ID + parameter FPGA_ID = 32'h3822093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h17df_1a00, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Clock: 200 MHz LVDS + */ + input wire logic clk_ddr4_p, + input wire logic clk_ddr4_n, + + /* + * GPIO + */ + output wire logic [7:0] user_led, + output wire logic qsfp0_led_green, + output wire logic qsfp0_led_red, + output wire logic qsfp1_led_green, + output wire logic qsfp1_led_red, + + /* + * UART: 500000 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + + /* + * Ethernet: QSFP28 + */ + input wire logic qsfp0_rx_p[4], + input wire logic qsfp0_rx_n[4], + output wire logic qsfp0_tx_p[4], + output wire logic qsfp0_tx_n[4], + input wire logic qsfp0_mgt_refclk_p, + input wire logic qsfp0_mgt_refclk_n, + output wire logic [1:0] qsfp0_fs, + output wire logic qsfp0_modsell, + output wire logic qsfp0_resetl, + input wire logic qsfp0_modprsl, + input wire logic qsfp0_intl, + output wire logic qsfp0_lpmode, + // inout wire logic qsfp0_i2c_scl, + // inout wire logic qsfp0_i2c_sda, + + input wire logic qsfp1_rx_p[4], + input wire logic qsfp1_rx_n[4], + output wire logic qsfp1_tx_p[4], + output wire logic qsfp1_tx_n[4], + // input wire logic qsfp1_mgt_refclk_p, + // input wire logic qsfp1_mgt_refclk_n, + output wire logic [1:0] qsfp1_fs, + output wire logic qsfp1_modsell, + output wire logic qsfp1_resetl, + input wire logic qsfp1_modprsl, + input wire logic qsfp1_intl, + output wire logic qsfp1_lpmode, + // inout wire logic qsfp1_i2c_scl, + // inout wire logic qsfp1_i2c_sda, + + /* + * PCIe + */ + input wire logic [7:0] pcie_rx_p, + input wire logic [7:0] pcie_rx_n, + output wire logic [7:0] pcie_tx_p, + output wire logic [7:0] pcie_tx_n, + input wire logic pcie_refclk_p, + input wire logic pcie_refclk_n, + input wire logic pcie_reset_n, + + /* + * BPI Flash + */ + inout wire logic [15:4] flash_dq, + output wire logic [23:0] flash_addr, + output wire logic [1:0] flash_region, + output wire logic flash_oe_n, + output wire logic flash_we_n, + output wire logic flash_adv_n, + input wire logic flash_wait +); + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_rst; + +wire clk_ddr4_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_rst; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_ddr4_ibufg_inst ( + .O (clk_ddr4_ibufg), + .I (clk_ddr4_p), + .IB (clk_ddr4_n) +); + +// MMCM instance +MMCME3_BASE #( + // 200 MHz input + .CLKIN1_PERIOD(8.0), + .REF_JITTER1(0.010), + // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1440 MHz) + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + // 1000 MHz / 8 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // Not used + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 200 MHz input + .CLKIN1(clk_ddr4_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // Not used + .CLKOUT1(), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +wire uart_rxd_int; + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_rxd}), + .out({uart_rxd_int}) +); + +// Flash +wire [3:0] flash_dq_int; +wire [15:0] flash_dq_i_int; +wire [15:0] flash_dq_o_int; +wire flash_dq_oe_int; +wire [23:0] flash_addr_int; +wire [1:0] flash_region_int; +wire flash_region_oe_int; +wire flash_ce_n_int; +wire flash_oe_n_int; +wire flash_we_n_int; +wire flash_adv_n_int; + +logic [15:0] flash_dq_o_reg; +logic flash_dq_oe_reg; +logic [23:0] flash_addr_reg; +logic [1:0] flash_region_reg; +logic flash_region_oe_reg; +logic flash_ce_n_reg; +logic flash_oe_n_reg; +logic flash_we_n_reg; +logic flash_adv_n_reg; + +always_ff @(posedge pcie_user_clk) begin + flash_dq_o_reg <= flash_dq_o_int; + flash_dq_oe_reg <= flash_dq_oe_int; + flash_addr_reg <= flash_addr_int; + flash_region_reg <= flash_region_int; + flash_region_oe_reg <= flash_region_oe_int; + flash_ce_n_reg <= flash_ce_n_int; + flash_oe_n_reg <= flash_oe_n_int; + flash_we_n_reg <= flash_we_n_int; + flash_adv_n_reg <= flash_adv_n_int; +end + +assign flash_dq[15:4] = flash_dq_oe_reg ? flash_dq_o_reg[15:4] : 12'hzzz; +assign flash_addr = flash_addr_reg; +assign flash_region = flash_region_oe_reg ? flash_region_reg : 2'bz; +assign flash_oe_n = flash_oe_n_reg; +assign flash_we_n = flash_we_n_reg; +assign flash_adv_n = flash_adv_n_reg; + +taxi_sync_signal #( + .WIDTH(16), + .N(2) +) +flash_sync_signal_inst ( + .clk(pcie_user_clk), + .in({flash_dq, flash_dq_int}), + .out(flash_dq_i_int) +); + +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(flash_dq_int), + .DO(flash_dq_o_reg[3:0]), + .DTS({4{~flash_dq_oe_reg}}), + .EOS(), + .FCSBO(flash_ce_n_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(1'b0), + .USRCCLKTS(1'b1), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; +wire fpga_boot_sync; + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +fpga_boot_sync_inst ( + .clk(clk_125mhz_int), + .in({fpga_boot}), + .out({fpga_boot_sync}) +); + +wire icap_avail; +logic [2:0] icap_state_reg = 0; +logic icap_csib_reg = 1'b1; +logic icap_rdwrb_reg = 1'b0; +logic [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always_ff @(posedge clk_125mhz_int) begin + case (icap_state_reg) + 0: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync && icap_avail) begin + icap_state_reg <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state_reg <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state_reg <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state_reg <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state_reg <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + +// PCIe +localparam AXIS_PCIE_DATA_W = 256; +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam AXIS_PCIE_RC_USER_W = 75; +localparam AXIS_PCIE_RQ_USER_W = 60; +localparam AXIS_PCIE_CQ_USER_W = 85; +localparam AXIS_PCIE_CC_USER_W = 33; +localparam RC_STRADDLE = 1'b0; // AXIS_PCIE_DATA_W >= 256; + +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; +localparam RQ_SEQ_NUM_EN = 1; + +localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256; +localparam BAR0_APERTURE = 24; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) axis_pcie_rc(); + +wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num; +wire pcie_rq_seq_num_vld; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [18:0] cfg_mgmt_addr; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire cfg_ext_read_received; +wire cfg_ext_write_received; +wire [9:0] cfg_ext_register_number; +wire [7:0] cfg_ext_function_number; +wire [31:0] cfg_ext_write_data; +wire [3:0] cfg_ext_write_byte_enable; +wire [31:0] cfg_ext_read_data; +wire cfg_ext_read_data_valid; + +// wire [3:0] cfg_interrupt_msix_enable; +// wire [3:0] cfg_interrupt_msix_mask; +// wire [251:0] cfg_interrupt_msix_vf_enable; +// wire [251:0] cfg_interrupt_msix_vf_mask; +// wire [63:0] cfg_interrupt_msix_address; +// wire [31:0] cfg_interrupt_msix_data; +// wire cfg_interrupt_msix_int; +// wire [1:0] cfg_interrupt_msix_vec_pending; +// wire cfg_interrupt_msix_vec_pending_status; +// wire cfg_interrupt_msix_sent; +// wire cfg_interrupt_msix_fail; +// wire [7:0] cfg_interrupt_msi_function_number; + +wire [3:0] cfg_interrupt_msi_enable; +wire [11:0] cfg_interrupt_msi_mmenable; +wire cfg_interrupt_msi_mask_update; +wire [31:0] cfg_interrupt_msi_data; +wire [3:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [3:0] cfg_interrupt_msi_pending_status_function_num; +wire cfg_interrupt_msi_sent; +wire cfg_interrupt_msi_fail; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [8:0] cfg_interrupt_msi_tph_st_tag; +wire [3:0] cfg_interrupt_msi_function_number; + +wire stat_err_cor = 1'b0; +wire stat_err_uncor = 1'b0; + +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE3 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte3_pcie_refclk_inst ( + .I (pcie_refclk_p), + .IB (pcie_refclk_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +pcie3_ultrascale_0 +pcie3_ultrascale_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_rst), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_pcie_rq.tdata), + .s_axis_rq_tkeep(axis_pcie_rq.tkeep), + .s_axis_rq_tlast(axis_pcie_rq.tlast), + .s_axis_rq_tready(axis_pcie_rq.tready), + .s_axis_rq_tuser(axis_pcie_rq.tuser), + .s_axis_rq_tvalid(axis_pcie_rq.tvalid), + + .m_axis_rc_tdata(axis_pcie_rc.tdata), + .m_axis_rc_tkeep(axis_pcie_rc.tkeep), + .m_axis_rc_tlast(axis_pcie_rc.tlast), + .m_axis_rc_tready(axis_pcie_rc.tready), + .m_axis_rc_tuser(axis_pcie_rc.tuser), + .m_axis_rc_tvalid(axis_pcie_rc.tvalid), + + .m_axis_cq_tdata(axis_pcie_cq.tdata), + .m_axis_cq_tkeep(axis_pcie_cq.tkeep), + .m_axis_cq_tlast(axis_pcie_cq.tlast), + .m_axis_cq_tready(axis_pcie_cq.tready), + .m_axis_cq_tuser(axis_pcie_cq.tuser), + .m_axis_cq_tvalid(axis_pcie_cq.tvalid), + + .s_axis_cc_tdata(axis_pcie_cc.tdata), + .s_axis_cc_tkeep(axis_pcie_cc.tkeep), + .s_axis_cc_tlast(axis_pcie_cc.tlast), + .s_axis_cc_tready(axis_pcie_cc.tready), + .s_axis_cc_tuser(axis_pcie_cc.tuser), + .s_axis_cc_tvalid(axis_pcie_cc.tvalid), + + .pcie_rq_seq_num(pcie_rq_seq_num), + .pcie_rq_seq_num_vld(pcie_rq_seq_num_vld), + .pcie_rq_tag(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld(), + + .pcie_tfc_nph_av(), + .pcie_tfc_npd_av(), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error(), + .cfg_ltr_enable(), + .cfg_ltssm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_dpa_substate_change(), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_per_func_status_control(3'd0), + .cfg_per_func_status_data(), + .cfg_per_function_number(4'd0), + .cfg_per_function_output_request(1'b0), + .cfg_per_function_update_done(), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(stat_err_cor), + .cfg_err_uncor_in(stat_err_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + .cfg_ds_function_number(3'd0), + + .cfg_subsys_vend_id(BOARD_ID >> 16), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + .pcie_perstn1_in(1'b0), + .pcie_perstn0_out(), + .pcie_perstn1_out(), + + .int_qpll1lock_out(), + .int_qpll1outrefclk_out(), + .int_qpll1outclk_out(), + .phy_rdy_out() +); + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .user_led(user_led), + .qsfp0_led_green(qsfp0_led_green), + .qsfp0_led_red(qsfp0_led_red), + .qsfp1_led_green(qsfp1_led_green), + .qsfp1_led_red(qsfp1_led_red), + + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd_int), + .uart_txd(uart_txd), + + /* + * Ethernet: QSFP+ + */ + .qsfp0_rx_p(qsfp0_rx_p), + .qsfp0_rx_n(qsfp0_rx_n), + .qsfp0_tx_p(qsfp0_tx_p), + .qsfp0_tx_n(qsfp0_tx_n), + .qsfp0_mgt_refclk_p(qsfp0_mgt_refclk_p), + .qsfp0_mgt_refclk_n(qsfp0_mgt_refclk_n), + .qsfp0_fs(qsfp0_fs), + .qsfp0_modsell(qsfp0_modsell), + .qsfp0_resetl(qsfp0_resetl), + .qsfp0_modprsl(qsfp0_modprsl), + .qsfp0_intl(qsfp0_intl), + .qsfp0_lpmode(qsfp0_lpmode), + + .qsfp1_rx_p(qsfp1_rx_p), + .qsfp1_rx_n(qsfp1_rx_n), + .qsfp1_tx_p(qsfp1_tx_p), + .qsfp1_tx_n(qsfp1_tx_n), + // .qsfp1_mgt_refclk_p(qsfp1_mgt_refclk_p), + // .qsfp1_mgt_refclk_n(qsfp1_mgt_refclk_n), + .qsfp1_fs(qsfp1_fs), + .qsfp1_modsell(qsfp1_modsell), + .qsfp1_resetl(qsfp1_resetl), + .qsfp1_modprsl(qsfp1_modprsl), + .qsfp1_intl(qsfp1_intl), + .qsfp1_lpmode(qsfp1_lpmode), + + /* + * PCIe + */ + .pcie_clk(pcie_user_clk), + .pcie_rst(pcie_user_rst), + .s_axis_pcie_cq(axis_pcie_cq), + .m_axis_pcie_cc(axis_pcie_cc), + .m_axis_pcie_rq(axis_pcie_rq), + .s_axis_pcie_rc(axis_pcie_rc), + + .pcie_rq_seq_num(pcie_rq_seq_num), + .pcie_rq_seq_num_vld(pcie_rq_seq_num_vld), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * BPI flash + */ + .fpga_boot(fpga_boot), + .flash_dq_i(flash_dq_i_int), + .flash_dq_o(flash_dq_o_int), + .flash_dq_oe(flash_dq_oe_int), + .flash_addr(flash_addr_int), + .flash_region(flash_region_int), + .flash_region_oe(flash_region_oe_int), + .flash_ce_n(flash_ce_n_int), + .flash_oe_n(flash_oe_n_int), + .flash_we_n(flash_we_n_int), + .flash_adv_n(flash_adv_n_int) +); + +endmodule + +`resetall diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..09cdd05 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "kintexu", + + // FW ID + parameter FPGA_ID = 32'h3822093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h17df_1a00, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + + // PCIe interface configuration + parameter RQ_SEQ_NUM_W = 6, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk_125mhz, + input wire logic rst_125mhz, + + /* + * GPIO + */ + output wire logic [7:0] user_led, + output wire logic qsfp0_led_green, + output wire logic qsfp0_led_red, + output wire logic qsfp1_led_green, + output wire logic qsfp1_led_red, + + /* + * UART: 115200 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + + /* + * Ethernet: QSFP+ + */ + input wire logic qsfp0_rx_p[4], + input wire logic qsfp0_rx_n[4], + output wire logic qsfp0_tx_p[4], + output wire logic qsfp0_tx_n[4], + input wire logic qsfp0_mgt_refclk_p, + input wire logic qsfp0_mgt_refclk_n, + output wire logic [1:0] qsfp0_fs, + output wire logic qsfp0_modsell, + output wire logic qsfp0_resetl, + input wire logic qsfp0_modprsl, + input wire logic qsfp0_intl, + output wire logic qsfp0_lpmode, + + input wire logic qsfp1_rx_p[4], + input wire logic qsfp1_rx_n[4], + output wire logic qsfp1_tx_p[4], + output wire logic qsfp1_tx_n[4], + // input wire logic qsfp1_mgt_refclk_p, + // input wire logic qsfp1_mgt_refclk_n, + output wire logic [1:0] qsfp1_fs, + output wire logic qsfp1_modsell, + output wire logic qsfp1_resetl, + input wire logic qsfp1_modprsl, + input wire logic qsfp1_intl, + output wire logic qsfp1_lpmode, + + /* + * PCIe + */ + input wire logic pcie_clk, + input wire logic pcie_rst, + taxi_axis_if.snk s_axis_pcie_cq, + taxi_axis_if.src m_axis_pcie_cc, + taxi_axis_if.src m_axis_pcie_rq, + taxi_axis_if.snk s_axis_pcie_rc, + + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num, + input wire logic pcie_rq_seq_num_vld, + + input wire logic [2:0] cfg_max_payload, + input wire logic [2:0] cfg_max_read_req, + input wire logic [3:0] cfg_rcb_status, + + output wire logic [18:0] cfg_mgmt_addr, + output wire logic cfg_mgmt_write, + output wire logic [31:0] cfg_mgmt_write_data, + output wire logic [3:0] cfg_mgmt_byte_enable, + output wire logic cfg_mgmt_read, + output wire logic [31:0] cfg_mgmt_read_data, + input wire logic cfg_mgmt_read_write_done, + + input wire logic [7:0] cfg_fc_ph, + input wire logic [11:0] cfg_fc_pd, + input wire logic [7:0] cfg_fc_nph, + input wire logic [11:0] cfg_fc_npd, + input wire logic [7:0] cfg_fc_cplh, + input wire logic [11:0] cfg_fc_cpld, + output wire logic [2:0] cfg_fc_sel, + + input wire logic cfg_ext_read_received, + input wire logic cfg_ext_write_received, + input wire logic [9:0] cfg_ext_register_number, + input wire logic [7:0] cfg_ext_function_number, + input wire logic [31:0] cfg_ext_write_data, + input wire logic [3:0] cfg_ext_write_byte_enable, + output wire logic [31:0] cfg_ext_read_data, + output wire logic cfg_ext_read_data_valid, + + input wire logic [3:0] cfg_interrupt_msi_enable, + input wire logic [11:0] cfg_interrupt_msi_mmenable, + input wire logic cfg_interrupt_msi_mask_update, + input wire logic [31:0] cfg_interrupt_msi_data, + output wire logic [3:0] cfg_interrupt_msi_select, + output wire logic [31:0] cfg_interrupt_msi_int, + output wire logic [31:0] cfg_interrupt_msi_pending_status, + output wire logic cfg_interrupt_msi_pending_status_data_enable, + output wire logic [3:0] cfg_interrupt_msi_pending_status_function_num, + input wire logic cfg_interrupt_msi_sent, + input wire logic cfg_interrupt_msi_fail, + output wire logic [2:0] cfg_interrupt_msi_attr, + output wire logic cfg_interrupt_msi_tph_present, + output wire logic [1:0] cfg_interrupt_msi_tph_type, + output wire logic [8:0] cfg_interrupt_msi_tph_st_tag, + output wire logic [3:0] cfg_interrupt_msi_function_number, + + /* + * BPI flash + */ + output wire logic fpga_boot, + input wire logic [15:0] flash_dq_i, + output wire logic [15:0] flash_dq_o, + output wire logic flash_dq_oe, + output wire logic [23:0] flash_addr, + output wire logic [1:0] flash_region, + output wire logic flash_region_oe, + output wire logic flash_ce_n, + output wire logic flash_oe_n, + output wire logic flash_we_n, + output wire logic flash_adv_n +); + +localparam logic PTP_TS_FMT_TOD = 1'b0; +localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48; + +// flashing via PCIe VSEC +pyrite_pcie_us_vsec_bpi #( + .EXT_CAP_ID(16'h000B), + .EXT_CAP_VERSION(4'h1), + .EXT_CAP_OFFSET(12'h480), + .EXT_CAP_NEXT(12'h000), + .EXT_CAP_VSEC_ID(16'h00DB), + .EXT_CAP_VSEC_REV(4'h1), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Flash + .FLASH_SEG_COUNT(4), + .FLASH_SEG_DEFAULT(1), + .FLASH_SEG_FALLBACK(0), + .FLASH_SEG0_SIZE(32'h00000000), + .FLASH_DATA_W(16), + .FLASH_ADDR_W(24), + .FLASH_RGN_W(2) +) +pyrite_inst ( + .clk(pcie_clk), + .rst(pcie_rst), + + /* + * PCIe + */ + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + /* + * BPI flash + */ + .fpga_boot(fpga_boot), + .flash_dq_i(flash_dq_i), + .flash_dq_o(flash_dq_o), + .flash_dq_oe(flash_dq_oe), + .flash_addr(flash_addr), + .flash_region(flash_region), + .flash_region_oe(flash_region_oe), + .flash_ce_n(flash_ce_n), + .flash_oe_n(flash_oe_n), + .flash_we_n(flash_we_n), + .flash_adv_n(flash_adv_n) +); + +// XFCP +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); + +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * UART interface + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd), + + /* + * XFCP downstream interface + */ + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), + + /* + * Configuration + */ + .prescale(16'(125000000/3000000)) +); + +localparam XFCP_PORTS = 3; + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("DNPCIe"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_stat) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2](); + +taxi_axis_arb_mux #( + .S_COUNT($size(axis_eth_stat)), + .UPDATE_TID(1'b0), + .ARB_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIO(1'b0) +) +stat_mux_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream inputs (sink) + */ + .s_axis(axis_eth_stat), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_stat) +); + +// QSFP+ +assign qsfp0_fs = 2'b00; + +assign qsfp0_modsell = 1'b0; +assign qsfp0_resetl = 1'b1; +assign qsfp0_lpmode = 1'b0; + +assign qsfp1_fs = 2'b00; + +assign qsfp1_modsell = 1'b0; +assign qsfp1_resetl = 1'b1; +assign qsfp1_lpmode = 1'b0; + +wire qsfp_tx_clk[8]; +wire qsfp_tx_rst[8]; +wire qsfp_rx_clk[8]; +wire qsfp_rx_rst[8]; + +wire qsfp_rx_status[8]; + +assign user_led[0] = qsfp_rx_status[0]; +assign user_led[1] = qsfp_rx_status[1]; +assign user_led[2] = qsfp_rx_status[2]; +assign user_led[3] = qsfp_rx_status[3]; +assign user_led[4] = qsfp_rx_status[4]; +assign user_led[5] = qsfp_rx_status[5]; +assign user_led[6] = qsfp_rx_status[6]; +// assign user_led[7] = qsfp_rx_status[7]; + +wire [1:0] qsfp_gtpowergood; + +wire qsfp0_mgt_refclk; +wire qsfp0_mgt_refclk_int; +wire qsfp0_mgt_refclk_bufg; + +wire qsfp_rst; + +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[8](); +taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1+PTP_TS_W)) axis_qsfp_rx[8](); + +if (SIM) begin + + assign qsfp0_mgt_refclk = qsfp0_mgt_refclk_p; + assign qsfp0_mgt_refclk_int = qsfp0_mgt_refclk_p; + assign qsfp0_mgt_refclk_bufg = qsfp0_mgt_refclk_int; + +end else begin + + IBUFDS_GTE3 ibuf0s_gte3_qsfp0_mgt_refclk_inst ( + .I (qsfp0_mgt_refclk_p), + .IB (qsfp0_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp0_mgt_refclk), + .ODIV2 (qsfp0_mgt_refclk_int) + ); + + BUFG_GT bufg0gt_qsfp0_mgt_refclk_inst ( + .CE (&qsfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp0_mgt_refclk_int), + .O (qsfp0_mgt_refclk_bufg) + ); + +end + +taxi_sync_reset #( + .N(4) +) +qsfp_sync_reset_inst ( + .clk(qsfp0_mgt_refclk_bufg), + .rst(rst_125mhz), + .out(qsfp_rst) +); + +wire qsfp_tx_p[8]; +wire qsfp_tx_n[8]; +wire qsfp_rx_p[8]; +wire qsfp_rx_n[8]; + +assign qsfp0_tx_p = qsfp_tx_p[4*0 +: 4]; +assign qsfp0_tx_n = qsfp_tx_n[4*0 +: 4]; +assign qsfp1_tx_p = qsfp_tx_p[4*1 +: 4]; +assign qsfp1_tx_n = qsfp_tx_n[4*1 +: 4]; + +assign qsfp_rx_p[4*0 +: 4] = qsfp0_rx_p; +assign qsfp_rx_n[4*0 +: 4] = qsfp0_rx_n; +assign qsfp_rx_p[4*1 +: 4] = qsfp1_rx_p; +assign qsfp_rx_n[4*1 +: 4] = qsfp1_rx_n; + +wire ptp_clk = qsfp0_mgt_refclk_bufg; +wire ptp_rst = qsfp_rst; +wire ptp_sample_clk = clk_125mhz; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; + +assign user_led[7] = ptp_pps_str; + +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; + +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad + + localparam CNT = 4; + + taxi_apb_if #( + .ADDR_W(18), + .DATA_W(16) + ) + gt_apb_ctrl(); + + taxi_xfcp_mod_apb #( + .XFCP_EXT_ID_STR("GTH CTRL") + ) + xfcp_mod_apb_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[n+1]), + .xfcp_usp_us(xfcp_sw_us[n+1]), + + /* + * APB master interface + */ + .m_apb(gt_apb_ctrl) + ); + + taxi_eth_mac_25g_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + .CNT(4), + + // GT config + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + + // GT type + .GT_TYPE("GTH"), + + // MAC/PHY config + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), + .PADDING_EN(1'b1), + .DIC_EN(1'b1), + .MIN_FRAME_LEN(64), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TD_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .PTP_TD_SDI_PIPELINE(2), + .PRBS31_EN(1'b0), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/6.4), + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(n*CNT*(16+16)), + .STAT_UPDATE_PERIOD(1024), + .STAT_STR_EN(1), + .STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP1 : STAT_PREFIX_STR_QSFP2) + ) + mac_inst ( + .xcvr_ctrl_clk(clk_125mhz), + .xcvr_ctrl_rst(qsfp_rst), + + /* + * Transceiver control + */ + .s_apb_ctrl(gt_apb_ctrl), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), + + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p[n*CNT +: CNT]), + .xcvr_txn(qsfp_tx_n[n*CNT +: CNT]), + .xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]), + .xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]), + + /* + * MAC clocks + */ + .rx_clk(qsfp_rx_clk[n*CNT +: CNT]), + .rx_rst_in('{CNT{1'b0}}), + .rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]), + .tx_clk(qsfp_tx_clk[n*CNT +: CNT]), + .tx_rst_in('{CNT{1'b0}}), + .tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]), + .m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sdi(ptp_td_sd), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req('{CNT{1'b0}}), + .tx_lfc_resend('{CNT{1'b0}}), + .rx_lfc_en('{CNT{1'b0}}), + .rx_lfc_req(), + .rx_lfc_ack('{CNT{1'b0}}), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req('{CNT{'0}}), + .tx_pfc_resend('{CNT{1'b0}}), + .rx_pfc_en('{CNT{'0}}), + .rx_pfc_req(), + .rx_pfc_ack('{CNT{'0}}), + + /* + * Pause interface + */ + .tx_lfc_pause_en('{CNT{1'b0}}), + .tx_pause_req('{CNT{1'b0}}), + .tx_pause_ack(), + + /* + * Statistics + */ + .stat_clk(clk_125mhz), + .stat_rst(rst_125mhz), + .m_axis_stat(axis_eth_stat[n]), + + /* + * Status + */ + .tx_start_packet(), + .stat_tx_byte(), + .stat_tx_pkt_len(), + .stat_tx_pkt_ucast(), + .stat_tx_pkt_mcast(), + .stat_tx_pkt_bcast(), + .stat_tx_pkt_vlan(), + .stat_tx_pkt_good(), + .stat_tx_pkt_bad(), + .stat_tx_err_oversize(), + .stat_tx_err_user(), + .stat_tx_err_underflow(), + .rx_start_packet(), + .rx_error_count(), + .rx_block_lock(), + .rx_high_ber(), + .rx_status(qsfp_rx_status[n*CNT +: CNT]), + .stat_rx_byte(), + .stat_rx_pkt_len(), + .stat_rx_pkt_fragment(), + .stat_rx_pkt_jabber(), + .stat_rx_pkt_ucast(), + .stat_rx_pkt_mcast(), + .stat_rx_pkt_bcast(), + .stat_rx_pkt_vlan(), + .stat_rx_pkt_good(), + .stat_rx_pkt_bad(), + .stat_rx_err_oversize(), + .stat_rx_err_bad_fcs(), + .stat_rx_err_bad_block(), + .stat_rx_err_framing(), + .stat_rx_err_preamble(), + .stat_rx_fifo_drop('{CNT{1'b0}}), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_tx_max_pkt_len('{CNT{16'd9218}}), + .cfg_tx_ifg('{CNT{8'd12}}), + .cfg_tx_enable('{CNT{1'b1}}), + .cfg_rx_max_pkt_len('{CNT{16'd9218}}), + .cfg_rx_enable('{CNT{1'b1}}), + .cfg_tx_prbs31_enable('{CNT{1'b0}}), + .cfg_rx_prbs31_enable('{CNT{1'b0}}), + .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}), + .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}), + .cfg_mcf_rx_eth_src('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_src('{CNT{1'b0}}), + .cfg_mcf_rx_eth_type('{CNT{16'h8808}}), + .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}), + .cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}), + .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}), + .cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}), + .cfg_mcf_rx_forward('{CNT{1'b0}}), + .cfg_mcf_rx_enable('{CNT{1'b0}}), + .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_lfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_lfc_opcode('{CNT{16'h0001}}), + .cfg_tx_lfc_en('{CNT{1'b0}}), + .cfg_tx_lfc_quanta('{CNT{16'hffff}}), + .cfg_tx_lfc_refresh('{CNT{16'h7fff}}), + .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_pfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_pfc_opcode('{CNT{16'h0101}}), + .cfg_tx_pfc_en('{CNT{1'b0}}), + .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}), + .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}), + .cfg_rx_lfc_opcode('{CNT{16'h0001}}), + .cfg_rx_lfc_en('{CNT{1'b0}}), + .cfg_rx_pfc_opcode('{CNT{16'h0101}}), + .cfg_rx_pfc_en('{CNT{1'b0}}) + ); + +end + +wire [1:0] cfg_interrupt_msi_pending_status_function_num_int; +wire [7:0] cfg_interrupt_msi_tph_st_tag_int; +wire [7:0] cfg_interrupt_msi_function_number_int; + +assign cfg_interrupt_msi_pending_status_function_num = 4'(cfg_interrupt_msi_pending_status_function_num_int); +assign cfg_interrupt_msi_tph_st_tag = 9'(cfg_interrupt_msi_tph_st_tag_int); +assign cfg_interrupt_msi_function_number = cfg_interrupt_msi_function_number_int[3:0]; + +cndm_micro_pcie_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .PORTS(8), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(1'b0), + .PTP_CLK_PER_NS_NUM(32), + .PTP_CLK_PER_NS_DEN(5), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W) +) +cndm_inst ( + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld), + .pcie_rq_seq_num1('0), + .pcie_rq_seq_num_vld1('0), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr[9:0]), + .cfg_mgmt_function_number(cfg_mgmt_addr[17:10]), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(2'(cfg_interrupt_msi_select)), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num_int), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag_int), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_int), + + /* + * PTP + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sdo(ptp_td_sd), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_sync_locked(), + .ptp_sync_ts_rel(), + .ptp_sync_ts_rel_step(), + .ptp_sync_ts_tod(), + .ptp_sync_ts_tod_step(), + .ptp_sync_pps(), + .ptp_sync_pps_str(), + + /* + * Ethernet + */ + .mac_tx_clk(qsfp_tx_clk), + .mac_tx_rst(qsfp_tx_rst), + .mac_axis_tx(axis_qsfp_tx), + .mac_axis_tx_cpl(axis_qsfp_tx_cpl), + + .mac_rx_clk(qsfp_rx_clk), + .mac_rx_rst(qsfp_rx_rst), + .mac_axis_rx(axis_qsfp_rx) +); + +endmodule + +`resetall diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..775670c --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"kintexu\"" + +# PTP configuration +export PARAM_PTP_TS_EN := 1 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_W := 32 +export PARAM_AXIL_CTRL_ADDR_W := 24 + +# MAC configuration +export PARAM_CFG_LOW_LATENCY := 1 +export PARAM_COMBINED_MAC_PCS := 1 +export PARAM_MAC_DATA_W := 32 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/baser.py b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/cndm.py b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/cndm.py new file mode 120000 index 0000000..c693df0 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/cndm.py @@ -0,0 +1 @@ +../../lib/taxi/src/cndm/tb/cndm.py \ No newline at end of file diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..c153ad7 --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,495 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +import sys + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import XgmiiFrame +from cocotbext.uart import UartSource, UartSink +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePcieDevice + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Clocks + cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=8, + user_clk_frequency=250e6, + alignment="dword", + rc_straddle=False, + pf_count=1, + max_payload_size=1024, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + pf0_msi_enable=True, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf0_msix_enable=False, + pf0_msix_table_size=31, + pf0_msix_table_bir=4, + pf0_msix_table_offset=0x00000000, + pf0_msix_pba_bir=4, + pf0_msix_pba_offset=0x00008000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + + # signals + # Clock and Reset Interface + user_clk=dut.pcie_clk, + user_reset=dut.pcie_rst, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq), + pcie_rq_seq_num=dut.pcie_rq_seq_num, + pcie_rq_seq_num_vld=dut.pcie_rq_seq_num_vld, + # pcie_rq_tag + # pcie_rq_tag_av + # pcie_rq_tag_vld + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=dut.cfg_mgmt_addr, + cfg_mgmt_write=dut.cfg_mgmt_write, + cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + cfg_mgmt_read=dut.cfg_mgmt_read, + cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + cfg_max_payload=dut.cfg_max_payload, + cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + cfg_rcb_status=dut.cfg_rcb_status, + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + # cfg_err_cor_in=dut.status_error_cor, + # cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, + # cfg_interrupt_msi_vf_enable=dut.cfg_interrupt_msi_vf_enable, + cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, + cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, + cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, + # cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, + # cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, + # cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, + # cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, + # cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, + # cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, + # cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, + # cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, + # cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, + cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W)) + + self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) + + # Ethernet + cocotb.start_soon(Clock(dut.qsfp0_mgt_refclk_p, 6.4, units="ns").start()) + + self.qsfp_sources = [] + self.qsfp_sinks = [] + + for inst in dut.uut.gt_quad: + for ch in inst.mac_inst.ch: + gt_inst = ch.ch_inst.gt.gt_inst + + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 6.206 + gbx_cfg = (66, [64, 65]) + else: + clk = 6.4 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None + + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.rst_125mhz.setimmediatevalue(0) + + await FallingEdge(self.dut.pcie_rst) + await Timer(100, 'ns') + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 0 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.pcie_clk) + + if self.loopback_enable: + for src, snk in zip(self.qsfp_sources, self.qsfp_sinks): + while not snk.empty(): + await src.send(await snk.recv()) + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Init driver model") + driver = cndm.Driver() + await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + + tb.log.info("Init complete") + + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + + for snk in tb.qsfp_sinks: + snk.clear() + + tb.log.info("Send and receive single packet on each port") + + for k in range(len(driver.ports)): + data = f"Corundum rocks on port {k}!".encode('ascii') + + await driver.ports[k].start_xmit(data) + + pkt = await tb.qsfp_sinks[k].recv() + tb.log.info("Got TX packet: %s", pkt) + + assert pkt.get_payload() == data.ljust(60, b'\x00') + assert pkt.check_fcs() + + await tb.qsfp_sources[k].send(pkt) + + pkt = await driver.ports[k].recv() + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == data.ljust(60, b'\x00') + + tb.log.info("Multiple small packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == pkts[k].ljust(60, b'\x00') + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == pkts[k].ljust(60, b'\x00') + + tb.loopback_enable = False + + await RisingEdge(dut.clk_125mhz) + await RisingEdge(dut.clk_125mhz) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "cndm", "rtl", "cndm_micro_pcie_us.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vsec_bpi.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"kintexu\"" + + # PTP configuration + parameters['PTP_TS_EN'] = 1 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_W'] = 32 + parameters['AXIL_CTRL_ADDR_W'] = 24 + + # MAC configuration + parameters['CFG_LOW_LATENCY'] = 1 + parameters['COMBINED_MAC_PCS'] = 1 + parameters['MAC_DATA_W'] = 32 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.sv b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.sv new file mode 100644 index 0000000..339a41b --- /dev/null +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.sv @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic testbench + */ +module test_fpga_core # +( + /* verilator lint_off WIDTHTRUNC */ + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "kintexu", + + // FW ID + parameter FPGA_ID = 32'h3822093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h17df_1a00, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_W = 256, + parameter AXIS_PCIE_RC_USER_W = 75, + parameter AXIS_PCIE_RQ_USER_W = 60, + parameter AXIS_PCIE_CQ_USER_W = 85, + parameter AXIS_PCIE_CC_USER_W = 33, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 32 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; + +logic clk_125mhz; +logic rst_125mhz; + +logic [7:0] user_led; +logic qsfp0_led_green; +logic qsfp0_led_red; +logic qsfp1_led_green; +logic qsfp1_led_red; + +logic uart_rxd; +logic uart_txd; + +logic qsfp0_mgt_refclk_p; +logic qsfp0_mgt_refclk_n; +logic [1:0] qsfp0_fs; +logic qsfp0_modsell; +logic qsfp0_resetl; +logic qsfp0_modprsl; +logic qsfp0_intl; +logic qsfp0_lpmode; + +// logic qsfp1_mgt_refclk_p; +// logic qsfp1_mgt_refclk_n; +logic [1:0] qsfp1_fs; +logic qsfp1_modsell; +logic qsfp1_resetl; +logic qsfp1_modprsl; +logic qsfp1_intl; +logic qsfp1_lpmode; + +logic pcie_clk; +logic pcie_rst; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) s_axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) m_axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) m_axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) s_axis_pcie_rc(); + +logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num; +logic pcie_rq_seq_num_vld; + +logic [2:0] cfg_max_payload; +logic [2:0] cfg_max_read_req; +logic [3:0] cfg_rcb_status; + +logic [18:0] cfg_mgmt_addr; +logic cfg_mgmt_write; +logic [31:0] cfg_mgmt_write_data; +logic [3:0] cfg_mgmt_byte_enable; +logic cfg_mgmt_read; +logic [31:0] cfg_mgmt_read_data; +logic cfg_mgmt_read_write_done; + +logic [7:0] cfg_fc_ph; +logic [11:0] cfg_fc_pd; +logic [7:0] cfg_fc_nph; +logic [11:0] cfg_fc_npd; +logic [7:0] cfg_fc_cplh; +logic [11:0] cfg_fc_cpld; +logic [2:0] cfg_fc_sel; + +logic cfg_ext_read_received; +logic cfg_ext_write_received; +logic [9:0] cfg_ext_register_number; +logic [7:0] cfg_ext_function_number; +logic [31:0] cfg_ext_write_data; +logic [3:0] cfg_ext_write_byte_enable; +logic [31:0] cfg_ext_read_data; +logic cfg_ext_read_data_valid; + +logic [3:0] cfg_interrupt_msi_enable; +logic [11:0] cfg_interrupt_msi_mmenable; +logic cfg_interrupt_msi_mask_update; +logic [31:0] cfg_interrupt_msi_data; +logic [3:0] cfg_interrupt_msi_select; +logic [31:0] cfg_interrupt_msi_int; +logic [31:0] cfg_interrupt_msi_pending_status; +logic cfg_interrupt_msi_pending_status_data_enable; +logic [3:0] cfg_interrupt_msi_pending_status_function_num; +logic cfg_interrupt_msi_sent; +logic cfg_interrupt_msi_fail; +logic [2:0] cfg_interrupt_msi_attr; +logic cfg_interrupt_msi_tph_present; +logic [1:0] cfg_interrupt_msi_tph_type; +logic [8:0] cfg_interrupt_msi_tph_st_tag; +logic [3:0] cfg_interrupt_msi_function_number; + +logic fpga_boot; +logic [15:0] flash_dq_i; +logic [15:0] flash_dq_o; +logic flash_dq_oe; +logic [23:0] flash_addr; +logic [1:0] flash_region; +logic flash_region_oe; +logic flash_ce_n; +logic flash_oe_n; +logic flash_we_n; +logic flash_adv_n; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +uut ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz), + .rst_125mhz(rst_125mhz), + + /* + * GPIO + */ + .user_led(user_led), + .qsfp0_led_green(qsfp0_led_green), + .qsfp0_led_red(qsfp0_led_red), + .qsfp1_led_green(qsfp1_led_green), + .qsfp1_led_red(qsfp1_led_red), + + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd), + + /* + * Ethernet: QSFP+ + */ + .qsfp0_rx_p('{4{1'b0}}), + .qsfp0_rx_n('{4{1'b0}}), + .qsfp0_tx_p(), + .qsfp0_tx_n(), + .qsfp0_mgt_refclk_p(qsfp0_mgt_refclk_p), + .qsfp0_mgt_refclk_n(qsfp0_mgt_refclk_n), + .qsfp0_fs(qsfp0_fs), + .qsfp0_modsell(qsfp0_modsell), + .qsfp0_resetl(qsfp0_resetl), + .qsfp0_modprsl(qsfp0_modprsl), + .qsfp0_intl(qsfp0_intl), + .qsfp0_lpmode(qsfp0_lpmode), + + .qsfp1_rx_p('{4{1'b0}}), + .qsfp1_rx_n('{4{1'b0}}), + .qsfp1_tx_p(), + .qsfp1_tx_n(), + // .qsfp1_mgt_refclk_p(qsfp1_mgt_refclk_p), + // .qsfp1_mgt_refclk_n(qsfp1_mgt_refclk_n), + .qsfp1_fs(qsfp1_fs), + .qsfp1_modsell(qsfp1_modsell), + .qsfp1_resetl(qsfp1_resetl), + .qsfp1_modprsl(qsfp1_modprsl), + .qsfp1_intl(qsfp1_intl), + .qsfp1_lpmode(qsfp1_lpmode), + + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num(pcie_rq_seq_num), + .pcie_rq_seq_num_vld(pcie_rq_seq_num_vld), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .flash_dq_i(flash_dq_i), + .flash_dq_o(flash_dq_o), + .flash_dq_oe(flash_dq_oe), + .flash_addr(flash_addr), + .flash_region(flash_region), + .flash_region_oe(flash_region_oe), + .flash_ce_n(flash_ce_n), + .flash_oe_n(flash_oe_n), + .flash_we_n(flash_we_n), + .flash_adv_n(flash_adv_n) +); + +endmodule + +`resetall