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eth: Add Ethernet example design for RK-XCKU5P-F board

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-02-20 21:31:46 -08:00
parent add1c7aec2
commit 2387aa793e
15 changed files with 2227 additions and 0 deletions
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src/eth/example/RK_XCKU5P_F/fpga/eth_rgmii.xdc Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# Ethernet constraints
# IDELAY from PHY chip (RGMII)
set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}]
# MMCM phase (RGMII)
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
# phy_txd[1] is on BITSLICE_0, which is a problem during delay calibration
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports phy_txd[1]]