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eth: Add Ethernet example design for RK-XCKU5P-F board

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-02-20 21:31:46 -08:00
parent add1c7aec2
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README.md
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@@ -220,6 +220,7 @@ Example designs are provided for several different FPGA boards, showcasing many
* Cisco Nexus K3P-S/ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) * Cisco Nexus K3P-S/ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
* Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P) * Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
* Alibaba AS02MC04 (Xilinx Kintex UltraScale+ XCKU3P) * Alibaba AS02MC04 (Xilinx Kintex UltraScale+ XCKU3P)
* RK-XCKU5P-F (Xilinx Kintex UltraScale+ XCKU5P)
* Digilent Arty A7 (Xilinx Artix 7 XC7A35T) * Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
* Digilent NetFPGA SUME (Xilinx Virtex 7 XC7V690T) * Digilent NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) * HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)

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src/eth/example/RK_XCKU5P_F/fpga/README.md Normal file
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# Taxi Example Design for RK-XCKU5P-F
## Introduction
This example design targets the RK-XCKU5P-F FPGA board.
The design places looped-back MACs on the QSFP28 cage.
* USB UART
* XFCP (3 Mbaud)
* RJ-45 Ethernet port with Realtek RTL8211F PHY
* Looped-back MAC via RGMII
* QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MAC via GTY transceiver
## Board details
* FPGA: xcku5p-ffvb676-2-e
* USB UART: FTDI FT2232
* 1000BASE-T PHY: Realtek RTL8211F via RGMII
* 25GBASE-R PHY: Soft PCS with GTY transceiver
## Licensing
* Toolchain
* Vivado Standard (enterprise license not required)
* IP
* No licensed vendor IP or 3rd party IP
## How to build
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
## How to test
Run `make program` to program the board with Vivado.
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.

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src/eth/example/RK_XCKU5P_F/fpga/common/vivado.mk Normal file
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# SPDX-License-Identifier: MIT
###################################################################
#
# Xilinx Vivado FPGA Makefile
#
# Copyright (c) 2016-2025 Alex Forencich
#
###################################################################
#
# Parameters:
# FPGA_TOP - Top module name
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
# SYN_FILES - list of source files
# INC_FILES - list of include files
# XDC_FILES - list of timing constraint files
# XCI_FILES - list of IP XCI files
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
#
# Note: both SYN_FILES and INC_FILES support file list files. File list
# files are files with a .f extension that contain a list of additional
# files to include, one path relative to the .f file location per line.
# The .f files are processed recursively, and then the complete file list
# is de-duplicated, with later files in the list taking precedence.
#
# Example:
#
# FPGA_TOP = fpga
# FPGA_FAMILY = VirtexUltrascale
# FPGA_DEVICE = xcvu095-ffva2104-2-e
# SYN_FILES = rtl/fpga.v
# XDC_FILES = fpga.xdc
# XCI_FILES = ip/pcspma.xci
# include ../common/vivado.mk
#
###################################################################
# phony targets
.PHONY: fpga vivado tmpclean clean distclean
# prevent make from deleting intermediate files and reports
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
.SECONDARY:
CONFIG ?= config.mk
-include $(CONFIG)
FPGA_TOP ?= fpga
PROJECT ?= $(FPGA_TOP)
XDC_FILES ?= $(PROJECT).xdc
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
###################################################################
# Main Targets
#
# all: build everything (fpga)
# fpga: build FPGA config
# vivado: open project in Vivado
# tmpclean: remove intermediate files
# clean: remove output files and project files
# distclean: remove archived output files
###################################################################
all: fpga
fpga: $(PROJECT).bit
vivado: $(PROJECT).xpr
vivado $(PROJECT).xpr
tmpclean::
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
clean:: tmpclean
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
distclean:: clean
-rm -rf rev
###################################################################
# Target implementations
###################################################################
# Vivado project file
# create fresh project if Makefile or IP files have changed
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
rm -rf defines.v
touch defines.v
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
# source config TCL scripts if any source file has changed
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
echo "open_project -quiet $(PROJECT).xpr" > $@
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
$(PROJECT).xpr: create_project.tcl update_config.tcl
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
# synthesis run
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
echo "open_project $(PROJECT).xpr" > run_synth.tcl
echo "reset_run synth_1" >> run_synth.tcl
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
echo "wait_on_run synth_1" >> run_synth.tcl
vivado -nojournal -nolog -mode batch -source run_synth.tcl
# implementation run
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
echo "open_project $(PROJECT).xpr" > run_impl.tcl
echo "reset_run impl_1" >> run_impl.tcl
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
echo "wait_on_run impl_1" >> run_impl.tcl
echo "open_run impl_1" >> run_impl.tcl
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
vivado -nojournal -nolog -mode batch -source run_impl.tcl
# output files (including potentially bit, bin, ltx, and xsa)
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
echo "open_run impl_1" >> generate_bit.tcl
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
mkdir -p rev
COUNT=100; \
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
do COUNT=$$((COUNT+1)); done; \
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# Ethernet constraints
# IDELAY from PHY chip (RGMII)
set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}]
# MMCM phase (RGMII)
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
# phy_txd[1] is on BITSLICE_0, which is a problem during delay calibration
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports phy_txd[1]]

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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the RK-XCKU5P-F
# part: xcku5p-ffvb676-2-e
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 200 MHz system clock (Y2)
set_property -dict {LOC T24 IOSTANDARD LVDS} [get_ports {clk_200mhz_p}]
set_property -dict {LOC U24 IOSTANDARD LVDS} [get_ports {clk_200mhz_n}]
create_clock -period 5.000 -name clk_200mhz [get_ports {clk_200mhz_p}]
# LEDs
set_property -dict {LOC H9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
set_property -dict {LOC J9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
set_property -dict {LOC G11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}]
set_property -dict {LOC H11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}]
set_false_path -to [get_ports {led[*]}]
set_output_delay 0 [get_ports {led[*]}]
# Buttons
set_property -dict {LOC K9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}]
set_property -dict {LOC K10 IOSTANDARD LVCMOS33} [get_ports {btn[1]}]
set_property -dict {LOC J10 IOSTANDARD LVCMOS33} [get_ports {btn[2]}]
set_property -dict {LOC J11 IOSTANDARD LVCMOS33} [get_ports {btn[3]}]
set_false_path -from [get_ports {btn[*]}]
set_input_delay 0 [get_ports {btn[*]}]
# GPIO
#set_property -dict {LOC D10 IOSTANDARD LVCMOS33} [get_ports {gpio[0]}] ;# 3
#set_property -dict {LOC D11 IOSTANDARD LVCMOS33} [get_ports {gpio[1]}] ;# 4
#set_property -dict {LOC E10 IOSTANDARD LVCMOS33} [get_ports {gpio[2]}] ;# 5
#set_property -dict {LOC E11 IOSTANDARD LVCMOS33} [get_ports {gpio[3]}] ;# 6
#set_property -dict {LOC B11 IOSTANDARD LVCMOS33} [get_ports {gpio[4]}] ;# 7
#set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {gpio[5]}] ;# 8
#set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {gpio[6]}] ;# 9
#set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {gpio[7]}] ;# 10
#set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports {gpio[8]}] ;# 11
#set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {gpio[9]}] ;# 12
#set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {gpio[10]}] ;# 13
#set_property -dict {LOC B10 IOSTANDARD LVCMOS33} [get_ports {gpio[11]}] ;# 14
#set_property -dict {LOC A12 IOSTANDARD LVCMOS33} [get_ports {gpio[12]}] ;# 15
#set_property -dict {LOC A13 IOSTANDARD LVCMOS33} [get_ports {gpio[13]}] ;# 16
#set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports {gpio[14]}] ;# 17
#set_property -dict {LOC B14 IOSTANDARD LVCMOS33} [get_ports {gpio[15]}] ;# 18
#set_property -dict {LOC C13 IOSTANDARD LVCMOS33} [get_ports {gpio[16]}] ;# 19
#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports {gpio[17]}] ;# 20
#set_property -dict {LOC B12 IOSTANDARD LVCMOS33} [get_ports {gpio[18]}] ;# 21
#set_property -dict {LOC C12 IOSTANDARD LVCMOS33} [get_ports {gpio[19]}] ;# 22
#set_property -dict {LOC D13 IOSTANDARD LVCMOS33} [get_ports {gpio[20]}] ;# 23
#set_property -dict {LOC D14 IOSTANDARD LVCMOS33} [get_ports {gpio[21]}] ;# 24
#set_property -dict {LOC E12 IOSTANDARD LVCMOS33} [get_ports {gpio[22]}] ;# 25
#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports {gpio[23]}] ;# 26
#set_property -dict {LOC F13 IOSTANDARD LVCMOS33} [get_ports {gpio[24]}] ;# 27
#set_property -dict {LOC F14 IOSTANDARD LVCMOS33} [get_ports {gpio[25]}] ;# 28
#set_property -dict {LOC F12 IOSTANDARD LVCMOS33} [get_ports {gpio[26]}] ;# 29
#set_property -dict {LOC G12 IOSTANDARD LVCMOS33} [get_ports {gpio[27]}] ;# 30
#set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports {gpio[28]}] ;# 31
#set_property -dict {LOC H14 IOSTANDARD LVCMOS33} [get_ports {gpio[29]}] ;# 32
#set_property -dict {LOC J14 IOSTANDARD LVCMOS33} [get_ports {gpio[30]}] ;# 33
#set_property -dict {LOC J15 IOSTANDARD LVCMOS33} [get_ports {gpio[31]}] ;# 34
#set_property -dict {LOC H13 IOSTANDARD LVCMOS33} [get_ports {gpio[32]}] ;# 35
#set_property -dict {LOC J13 IOSTANDARD LVCMOS33} [get_ports {gpio[33]}] ;# 36
# UART
set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}]
set_property -dict {LOC AD13 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}]
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]
set_false_path -from [get_ports {uart_rxd}]
set_input_delay 0 [get_ports {uart_rxd}]
# Micro SD
#set_property -dict {LOC Y15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_clk}] ;# 5 CLK SCLK
#set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_cmd}] ;# 3 CMD DI
#set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_dat[0]}] ;# 7 DAT0 DO
#set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_dat[1]}] ;# 8 DAT1
#set_property -dict {LOC AB16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_dat[2]}] ;# 1 DAT2
#set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_dat[3]}] ;# 2 CD/DAT3 CS
#set_property -dict {LOC Y16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {sdio_det}] ;# 9 DET
# Fan
#set_property -dict {LOC G9 IOSTANDARD LVCMOS18 QUIETIO SLOW DRIVE 8} [get_ports {fan}]
# Gigabit Ethernet RGMII PHY
set_property -dict {LOC K22 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from 28 RXC
set_property -dict {LOC L24 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from 26 RXD0
set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from 25 RXD1
set_property -dict {LOC K25 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from 24 RXD2
set_property -dict {LOC K26 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from 23 RXD3
set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from 27 RXCTL
set_property -dict {LOC M25 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from 21 TXC
set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from 19 TXD0
set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from 18 TXD1
set_property -dict {LOC L20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from 17 TXD2
set_property -dict {LOC K20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from 16 TXD3
set_property -dict {LOC M26 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from 20 TXCTL
create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}]
# QSFP28 Interface
set_property -dict {LOC Y2 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
set_property -dict {LOC Y1 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
set_property -dict {LOC AA5 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
set_property -dict {LOC AA4 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
set_property -dict {LOC V2 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
set_property -dict {LOC V1 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
set_property -dict {LOC W5 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
set_property -dict {LOC W4 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
set_property -dict {LOC T2 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
set_property -dict {LOC T1 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
set_property -dict {LOC U5 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
set_property -dict {LOC U4 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
set_property -dict {LOC P2 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
set_property -dict {LOC P1 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
set_property -dict {LOC R5 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
set_property -dict {LOC R4 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
set_property -dict {LOC V7 } [get_ports {qsfp_mgt_refclk_p}] ;# MGTREFCLK0P_225
set_property -dict {LOC V6 } [get_ports {qsfp_mgt_refclk_n}] ;# MGTREFCLK0N_225
set_property -dict {LOC W13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
set_property -dict {LOC W12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_modprsl]
set_property -dict {LOC Y13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_intl]
set_property -dict {LOC W14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
#set_property -dict {LOC AE15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {qsfp_i2c_scl}]
#set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {qsfp_i2c_sda}]
# 156.25 MHz MGT reference clock
create_clock -period 6.4 -name qsfp_mgt_refclk [get_ports {qsfp_mgt_refclk_p}]
set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
set_output_delay 0 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}]
#set_false_path -to [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
#set_output_delay 0 [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
#set_false_path -from [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
#set_input_delay 0 [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
# PCIe Interface
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
#set_property -dict {LOC AB7 } [get_ports pcie_refclk_p] ;# MGTREFCLK1P_224
#set_property -dict {LOC AB6 } [get_ports pcie_refclk_n] ;# MGTREFCLK1N_224
#set_property -dict {LOC T19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
#set_false_path -from [get_ports {pcie_reset_n}]
#set_input_delay 0 [get_ports {pcie_reset_n}]
# 100 MHz MGT reference clock
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
# FMC interface
# FMC HPC
#set_property -dict {LOC F10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {fmc_hpc_i2c_scl}] ;# C30 SCL
#set_property -dict {LOC F9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {fmc_hpc_i2c_sda}] ;# C31 SDA
#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[0]}] ;# G9 LA00_P_CC
#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[0]}] ;# G10 LA00_N_CC
#set_property -dict {LOC J23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[1]}] ;# D8 LA01_P_CC
#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[1]}] ;# D9 LA01_N_CC
#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[2]}] ;# H7 LA02_P
#set_property -dict {LOC H22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[2]}] ;# H8 LA02_N
#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[3]}] ;# G12 LA03_P
#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[3]}] ;# G13 LA03_N
#set_property -dict {LOC H26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[4]}] ;# H10 LA04_P
#set_property -dict {LOC G26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[4]}] ;# H11 LA04_N
#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[5]}] ;# D11 LA05_P
#set_property -dict {LOC F25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[5]}] ;# D12 LA05_N
#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[6]}] ;# C10 LA06_P
#set_property -dict {LOC G21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[6]}] ;# C11 LA06_N
#set_property -dict {LOC D24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[7]}] ;# H13 LA07_P
#set_property -dict {LOC D25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[7]}] ;# H14 LA07_N
#set_property -dict {LOC D26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[8]}] ;# G12 LA08_P
#set_property -dict {LOC C26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[8]}] ;# G13 LA08_N
#set_property -dict {LOC E25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[9]}] ;# D14 LA09_P
#set_property -dict {LOC E26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[9]}] ;# D15 LA09_N
#set_property -dict {LOC B25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[10]}] ;# C14 LA10_P
#set_property -dict {LOC B26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[10]}] ;# C15 LA10_N
#set_property -dict {LOC A24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[11]}] ;# H16 LA11_P
#set_property -dict {LOC A25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[11]}] ;# H17 LA11_N
#set_property -dict {LOC D23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[12]}] ;# G15 LA12_P
#set_property -dict {LOC C24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[12]}] ;# G16 LA12_N
#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[13]}] ;# D17 LA13_P
#set_property -dict {LOC E23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[13]}] ;# D18 LA13_N
#set_property -dict {LOC C23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[14]}] ;# C18 LA14_P
#set_property -dict {LOC B24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[14]}] ;# C19 LA14_N
#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[15]}] ;# H19 LA15_P
#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[15]}] ;# H20 LA15_N
#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[16]}] ;# G18 LA16_P
#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[16]}] ;# G19 LA16_N
#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[17]}] ;# D20 LA17_P_CC
#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[17]}] ;# D21 LA17_N_CC
#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[18]}] ;# C22 LA18_P_CC
#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[18]}] ;# C23 LA18_N_CC
#set_property -dict {LOC A22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[19]}] ;# H22 LA19_P
#set_property -dict {LOC A23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[19]}] ;# H23 LA19_N
#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[20]}] ;# G21 LA20_P
#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[20]}] ;# G22 LA20_N
#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[21]}] ;# H25 LA21_P
#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[21]}] ;# H26 LA21_N
#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[22]}] ;# G24 LA22_P
#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[22]}] ;# G25 LA22_N
#set_property -dict {LOC C22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[23]}] ;# D23 LA23_P
#set_property -dict {LOC B22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[23]}] ;# D24 LA23_N
#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[24]}] ;# H28 LA24_P
#set_property -dict {LOC A18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[24]}] ;# H29 LA24_N
#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[25]}] ;# G27 LA25_P
#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[25]}] ;# G28 LA25_N
#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[26]}] ;# D26 LA26_P
#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[26]}] ;# D27 LA26_N
#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[27]}] ;# C26 LA27_P
#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[27]}] ;# C27 LA27_N
#set_property -dict {LOC C17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[28]}] ;# H31 LA28_P
#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[28]}] ;# H32 LA28_N
#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[29]}] ;# G30 LA29_P
#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[29]}] ;# G31 LA29_N
#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[30]}] ;# H34 LA30_P
#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[30]}] ;# H35 LA30_N
#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[31]}] ;# G33 LA31_P
#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[31]}] ;# G34 LA31_N
#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[32]}] ;# H37 LA32_P
#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[32]}] ;# H38 LA32_N
#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_p[33]}] ;# G36 LA33_P
#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_la_n[33]}] ;# G37 LA33_N
#set_property -dict {LOC H23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_clk0_m2c_p}] ;# H4 CLK0_M2C_P
#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_clk0_m2c_n}] ;# H5 CLK0_M2C_N
#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_clk1_m2c_p}] ;# G2 CLK1_M2C_P
#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc_clk1_m2c_n}] ;# G3 CLK1_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[0]}] ;# MGTHTXP2_229 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2 from C2 DP0_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[0]}] ;# MGTHTXN2_229 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2 from C3 DP0_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[0]}] ;# MGTHRXP2_229 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2 from C6 DP0_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[0]}] ;# MGTHRXN2_229 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2 from C7 DP0_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[1]}] ;# MGTHTXP1_229 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2 from A22 DP1_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[1]}] ;# MGTHTXN1_229 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2 from A23 DP1_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[1]}] ;# MGTHRXP1_229 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2 from A2 DP1_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[1]}] ;# MGTHRXN1_229 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2 from A3 DP1_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[2]}] ;# MGTHTXP3_229 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2 from A26 DP2_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[2]}] ;# MGTHTXN3_229 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2 from A27 DP2_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[2]}] ;# MGTHRXP3_229 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2 from A6 DP2_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[2]}] ;# MGTHRXN3_229 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2 from A7 DP2_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[3]}] ;# MGTHTXP0_229 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2 from A30 DP3_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[3]}] ;# MGTHTXN0_229 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2 from A31 DP3_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[3]}] ;# MGTHRXP0_229 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2 from A10 DP3_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[3]}] ;# MGTHRXN0_229 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2 from A11 DP3_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[4]}] ;# MGTHTXP3_228 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1 from A34 DP4_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[4]}] ;# MGTHTXN3_228 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1 from A35 DP4_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[4]}] ;# MGTHRXP3_228 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1 from A14 DP4_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[4]}] ;# MGTHRXN3_228 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1 from A15 DP4_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[5]}] ;# MGTHTXP1_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from A38 DP5_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[5]}] ;# MGTHTXN1_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from A39 DP5_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[5]}] ;# MGTHRXP1_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from A18 DP5_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[5]}] ;# MGTHRXN1_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from A19 DP5_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[6]}] ;# MGTHTXP0_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from B36 DP6_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[6]}] ;# MGTHTXN0_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from B37 DP6_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[6]}] ;# MGTHRXP0_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from B16 DP6_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[6]}] ;# MGTHRXN0_228 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1 from B17 DP6_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_p[7]}] ;# MGTHTXP2_228 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1 from B32 DP7_C2M_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_c2m_n[7]}] ;# MGTHTXN2_228 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1 from B33 DP7_C2M_N
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_p[7]}] ;# MGTHRXP2_228 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1 from B12 DP7_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_dp_m2c_n[7]}] ;# MGTHRXN2_228 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1 from B13 DP7_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_mgt_refclk_0_p}] ;# MGTREFCLK0P_229 from D4 GBTCLK0_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_mgt_refclk_0_n}] ;# MGTREFCLK0N_229 from D5 GBTCLK0_M2C_N
#set_property -dict {LOC } [get_ports {fmc_hpc_mgt_refclk_1_p}] ;# MGTREFCLK0P_228 from B20 GBTCLK1_M2C_P
#set_property -dict {LOC } [get_ports {fmc_hpc_mgt_refclk_1_n}] ;# MGTREFCLK0N_228 from B21 GBTCLK1_M2C_N
# reference clock
#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_0 [get_ports {fmc_hpc_mgt_refclk_0_p}]
#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_1 [get_ports {fmc_hpc_mgt_refclk_1_p}]
# DDR4
# 2x MT40A512M16LY-062E:E
#set_property -dict {LOC Y22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}]
#set_property -dict {LOC Y25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}]
#set_property -dict {LOC W23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}]
#set_property -dict {LOC V26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}]
#set_property -dict {LOC R26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}]
#set_property -dict {LOC U26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}]
#set_property -dict {LOC R21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}]
#set_property -dict {LOC W25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}]
#set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}]
#set_property -dict {LOC Y26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}]
#set_property -dict {LOC R25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}]
#set_property -dict {LOC V23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}]
#set_property -dict {LOC AA24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}]
#set_property -dict {LOC W26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}]
#set_property -dict {LOC P23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}]
#set_property -dict {LOC AA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}]
#set_property -dict {LOC T25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}]
#set_property -dict {LOC P21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}]
#set_property -dict {LOC P26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}]
#set_property -dict {LOC R22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}]
#set_property -dict {LOC V24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}]
#set_property -dict {LOC W24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}]
#set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}]
#set_property -dict {LOC P25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}]
#set_property -dict {LOC P24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}]
#set_property -dict {LOC R23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}]
#set_property -dict {LOC P19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}]
#set_property -dict {LOC AB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
#set_property -dict {LOC AB25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
#set_property -dict {LOC AF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
#set_property -dict {LOC AD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
#set_property -dict {LOC AD24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
#set_property -dict {LOC AC24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
#set_property -dict {LOC AB24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
#set_property -dict {LOC AD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
#set_property -dict {LOC AC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
#set_property -dict {LOC AC22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
#set_property -dict {LOC AE21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
#set_property -dict {LOC AC21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
#set_property -dict {LOC AB21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
#set_property -dict {LOC AC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}]
#set_property -dict {LOC AD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}]
#set_property -dict {LOC AA22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}]
#set_property -dict {LOC AB22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}]
#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}]
#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}]
#set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
#set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
#set_property -dict {LOC AF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
#set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
#set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
#set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
#set_property -dict {LOC AE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
#set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
#set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
#set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
#set_property -dict {LOC AB20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
#set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
#set_property -dict {LOC AA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
#set_property -dict {LOC Y17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
#set_property -dict {LOC AA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
#set_property -dict {LOC Y18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
#set_property -dict {LOC AC18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}]
#set_property -dict {LOC AD18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}]
#set_property -dict {LOC AB17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}]
#set_property -dict {LOC AC17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}]
#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}]
#set_property -dict {LOC Y20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}]

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src/eth/example/RK_XCKU5P_F/fpga/fpga/Makefile Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# FPGA settings
FPGA_PART = xcku5p-ffvb676-2-e
FPGA_TOP = fpga
FPGA_ARCH = kintexuplus
RTL_DIR = ../rtl
LIB_DIR = ../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
# Files for synthesis
SYN_FILES = $(RTL_DIR)/fpga.sv
SYN_FILES += $(RTL_DIR)/fpga_core.sv
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
# XDC files
XDC_FILES = ../fpga.xdc
XDC_FILES += ../eth_rgmii.xdc
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/vivado.mk
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl
echo "connect_hw_server" >> program.tcl
echo "open_hw_target" >> program.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
echo "program_hw_devices [current_hw_device]" >> program.tcl
echo "exit" >> program.tcl
vivado -nojournal -nolog -mode batch -source program.tcl
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
echo "exit" >> generate_mcs.tcl
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
mkdir -p rev
COUNT=100; \
while [ -e rev/$*_rev$$COUNT.bit ]; \
do COUNT=$$((COUNT+1)); done; \
COUNT=$$((COUNT-1)); \
for x in .mcs .prm; \
do cp $*$$x rev/$*_rev$$COUNT$$x; \
echo "Output: rev/$*_rev$$COUNT$$x"; done;
flash: $(PROJECT).mcs $(PROJECT).prm
echo "open_hw" > flash.tcl
echo "connect_hw_server" >> flash.tcl
echo "open_hw_target" >> flash.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
echo "program_hw_devices [current_hw_device]" >> flash.tcl
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
echo "boot_hw_device [current_hw_device]" >> flash.tcl
echo "exit" >> flash.tcl
vivado -nojournal -nolog -mode batch -source flash.tcl

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src/eth/example/RK_XCKU5P_F/fpga/fpga/config.tcl Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "64"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

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src/eth/example/RK_XCKU5P_F/fpga/fpga_10g/Makefile Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# FPGA settings
FPGA_PART = xcku5p-ffvb676-2-e
FPGA_TOP = fpga
FPGA_ARCH = kintexuplus
RTL_DIR = ../rtl
LIB_DIR = ../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
# Files for synthesis
SYN_FILES = $(RTL_DIR)/fpga.sv
SYN_FILES += $(RTL_DIR)/fpga_core.sv
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
# XDC files
XDC_FILES = ../fpga.xdc
XDC_FILES += ../eth_rgmii.xdc
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/vivado.mk
program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl
echo "connect_hw_server" >> program.tcl
echo "open_hw_target" >> program.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
echo "program_hw_devices [current_hw_device]" >> program.tcl
echo "exit" >> program.tcl
vivado -nojournal -nolog -mode batch -source program.tcl
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
echo "exit" >> generate_mcs.tcl
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
mkdir -p rev
COUNT=100; \
while [ -e rev/$*_rev$$COUNT.bit ]; \
do COUNT=$$((COUNT+1)); done; \
COUNT=$$((COUNT-1)); \
for x in .mcs .prm; \
do cp $*$$x rev/$*_rev$$COUNT$$x; \
echo "Output: rev/$*_rev$$COUNT$$x"; done;
flash: $(PROJECT).mcs $(PROJECT).prm
echo "open_hw" > flash.tcl
echo "connect_hw_server" >> flash.tcl
echo "open_hw_target" >> flash.tcl
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
echo "program_hw_devices [current_hw_device]" >> flash.tcl
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
echo "boot_hw_device [current_hw_device]" >> flash.tcl
echo "exit" >> flash.tcl
vivado -nojournal -nolog -mode batch -source flash.tcl

22
src/eth/example/RK_XCKU5P_F/fpga/fpga_10g/config.tcl Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "32"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

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src/eth/example/RK_XCKU5P_F/fpga/lib/taxi Symbolic link
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../../../../../../

377
src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga.sv Normal file
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// SPDX-License-Identifier: MIT
/*
Copyright (c) 2014-2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "kintexuplus",
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
/*
* Clock: 200MHz LVDS
*/
input wire logic clk_200mhz_p,
input wire logic clk_200mhz_n,
/*
* GPIO
*/
input wire logic [3:0] btn,
output wire logic [3:0] led,
/*
* UART: 300000 bps, 8N1
*/
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire logic phy_rx_clk,
input wire logic [3:0] phy_rxd,
input wire logic phy_rx_ctl,
output wire logic phy_tx_clk,
output wire logic [3:0] phy_txd,
output wire logic phy_tx_ctl,
/*
* Ethernet: QSFP28
*/
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_mgt_refclk_p,
input wire logic qsfp_mgt_refclk_n,
output wire logic qsfp_modsell,
output wire logic qsfp_resetl,
input wire logic qsfp_modprsl,
input wire logic qsfp_intl,
output wire logic qsfp_lpmode//,
// inout wire logic qsfp_i2c_scl,
// inout wire logic qsfp_i2c_sda
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk90_125mhz_mmcm_out;
wire clk_125mhz_int;
wire clk90_125mhz_int;
wire rst_125mhz_int;
// Internal 312.5 MHz clock
wire clk_312mhz_mmcm_out;
wire clk_312mhz_int;
wire rst_312mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_200mhz_ibufg_inst (
.O (clk_200mhz_ibufg),
.I (clk_200mhz_p),
.IB (clk_200mhz_n)
);
// MMCM instance
MMCME4_BASE #(
// 200 MHz input
.CLKIN1_PERIOD(5.0),
.REF_JITTER1(0.010),
// 200 MHz input / 4 = 50 MHz PFD (range 10 MHz to 500 MHz)
.DIVCLK_DIVIDE(4),
// 50 MHz PFD * 25 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
.CLKFBOUT_MULT_F(25),
.CLKFBOUT_PHASE(0),
// 1250 MHz / 10 = 125 MHz, 0 degrees
.CLKOUT0_DIVIDE_F(10),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
// 1250 MHz / 10 = 125 MHz, 90 degrees
.CLKOUT1_DIVIDE(10),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(90),
// 1250 MHz / 4 = 312.5 MHz, 0 degrees
.CLKOUT2_DIVIDE(4),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
// Not used
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
// Not used
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT4_CASCADE("FALSE"),
// Not used
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
// Not used
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
// optimized bandwidth
.BANDWIDTH("OPTIMIZED"),
// don't wait for lock during startup
.STARTUP_WAIT("FALSE")
)
clk_mmcm_inst (
// 200 MHz input
.CLKIN1(clk_200mhz_ibufg),
// direct clkfb feeback
.CLKFBIN(mmcm_clkfb),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
// 125 MHz, 0 degrees
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
// 125 MHz, 90 degrees
.CLKOUT1(clk90_125mhz_mmcm_out),
.CLKOUT1B(),
// 312.5 MHz, 0 degrees
.CLKOUT2(clk_312mhz_mmcm_out),
.CLKOUT2B(),
// Not used
.CLKOUT3(),
.CLKOUT3B(),
// Not used
.CLKOUT4(),
// Not used
.CLKOUT5(),
// Not used
.CLKOUT6(),
// reset input
.RST(mmcm_rst),
// don't power down
.PWRDWN(1'b0),
// locked output
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
BUFG
clk90_125mhz_bufg_inst (
.I(clk90_125mhz_mmcm_out),
.O(clk90_125mhz_int)
);
BUFG
clk_312mhz_bufg_inst (
.I(clk_312mhz_mmcm_out),
.O(clk_312mhz_int)
);
taxi_sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
taxi_sync_reset #(
.N(4)
)
sync_reset_312mhz_inst (
.clk(clk_312mhz_int),
.rst(~mmcm_locked),
.out(rst_312mhz_int)
);
// GPIO
wire [3:0] btn_int;
taxi_debounce_switch #(
.WIDTH(4),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btn}),
.out({btn_int})
);
wire uart_rxd_int;
taxi_sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_int;
wire phy_rx_ctl_int;
IDELAYCTRL #(
.SIM_DEVICE("ULTRASCALE")
)
idelayctrl_inst (
.REFCLK(clk_312mhz_int),
.RST(rst_312mhz_int),
.RDY()
);
for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
IDELAYE3 #(
.DELAY_SRC("IDATAIN"),
.CASCADE("NONE"),
.DELAY_TYPE("FIXED"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(312.5),
.DELAY_FORMAT("TIME"),
.UPDATE_MODE("SYNC"),
.SIM_DEVICE("ULTRASCALE_PLUS")
)
idelay_inst (
.CASC_IN(1'b0),
.CASC_RETURN(1'b0),
.CASC_OUT(),
.IDATAIN(phy_rxd[n]),
.DATAIN(1'b0),
.DATAOUT(phy_rxd_int[n]),
.CLK(1'b0),
.EN_VTC(1'b1),
.CE(1'b0),
.INC(1'b0),
.LOAD(1'b0),
.RST(1'b0),
.CNTVALUEIN(9'd0),
.CNTVALUEOUT()
);
end
IDELAYE3 #(
.DELAY_SRC("IDATAIN"),
.CASCADE("NONE"),
.DELAY_TYPE("FIXED"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(312.5),
.DELAY_FORMAT("TIME"),
.UPDATE_MODE("SYNC"),
.SIM_DEVICE("ULTRASCALE_PLUS")
)
phy_rx_ctl_idelay (
.CASC_IN(1'b0),
.CASC_RETURN(1'b0),
.CASC_OUT(),
.IDATAIN(phy_rx_ctl),
.DATAIN(1'b0),
.DATAOUT(phy_rx_ctl_int),
.CLK(1'b0),
.EN_VTC(1'b1),
.CE(1'b0),
.INC(1'b0),
.LOAD(1'b0),
.RST(1'b0),
.CNTVALUEIN(9'd0),
.CNTVALUEOUT()
);
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.MAC_DATA_W(MAC_DATA_W)
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.clk90(clk90_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btn(btn_int),
.led(led),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rgmii_rx_clk(phy_rx_clk),
.phy_rgmii_rxd(phy_rxd_int),
.phy_rgmii_rx_ctl(phy_rx_ctl_int),
.phy_rgmii_tx_clk(phy_tx_clk),
.phy_rgmii_txd(phy_txd),
.phy_rgmii_tx_ctl(phy_tx_ctl),
/*
* Ethernet: QSFP28
*/
.qsfp_rx_p(qsfp_rx_p),
.qsfp_rx_n(qsfp_rx_n),
.qsfp_tx_p(qsfp_tx_p),
.qsfp_tx_n(qsfp_tx_n),
.qsfp_mgt_refclk_p(qsfp_mgt_refclk_p),
.qsfp_mgt_refclk_n(qsfp_mgt_refclk_n),
.qsfp_modsell(qsfp_modsell),
.qsfp_resetl(qsfp_resetl),
.qsfp_modprsl(qsfp_modprsl),
.qsfp_intl(qsfp_intl),
.qsfp_lpmode(qsfp_lpmode)
);
endmodule
`resetall

651
src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv Normal file
View File

@@ -0,0 +1,651 @@
// SPDX-License-Identifier: MIT
/*
Copyright (c) 2014-2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "kintexuplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1,
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire logic clk,
input wire logic clk90,
input wire logic rst,
/*
* GPIO
*/
input wire logic [3:0] btn,
output wire logic [3:0] led,
/*
* UART: 3000000 bps, 8N1
*/
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire logic phy_rgmii_rx_clk,
input wire logic [3:0] phy_rgmii_rxd,
input wire logic phy_rgmii_rx_ctl,
output wire logic phy_rgmii_tx_clk,
output wire logic [3:0] phy_rgmii_txd,
output wire logic phy_rgmii_tx_ctl,
/*
* Ethernet: QSFP28
*/
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_mgt_refclk_p,
input wire logic qsfp_mgt_refclk_n,
output wire logic qsfp_modsell,
output wire logic qsfp_resetl,
input wire logic qsfp_modprsl,
input wire logic qsfp_intl,
output wire logic qsfp_lpmode
);
// XFCP
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
taxi_xfcp_if_uart #(
.TX_FIFO_DEPTH(512),
.RX_FIFO_DEPTH(512)
)
xfcp_if_uart_inst (
.clk(clk),
.rst(rst),
/*
* UART interface
*/
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
/*
* XFCP downstream interface
*/
.xfcp_dsp_ds(xfcp_ds),
.xfcp_dsp_us(xfcp_us),
/*
* Configuration
*/
.prescale(16'(125000000/3000000))
);
localparam XFCP_PORTS = 2;
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
taxi_xfcp_switch #(
.XFCP_ID_STR("RK-XCKU5P-F"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("Taxi example"),
.PORTS($size(xfcp_sw_us))
)
xfcp_sw_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_ds),
.xfcp_usp_us(xfcp_us),
/*
* XFCP downstream ports
*/
.xfcp_dsp_ds(xfcp_sw_ds),
.xfcp_dsp_us(xfcp_sw_us)
);
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
taxi_xfcp_mod_stats #(
.XFCP_ID_STR("Statistics"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR(""),
.STAT_COUNT_W(64),
.STAT_PIPELINE(2)
)
xfcp_stats_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_sw_ds[0]),
.xfcp_usp_us(xfcp_sw_us[0]),
/*
* Statistics increment input
*/
.s_axis_stat(axis_stat)
);
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2]();
taxi_axis_arb_mux #(
.S_COUNT($size(axis_eth_stat)),
.UPDATE_TID(1'b0),
.ARB_ROUND_ROBIN(1'b1),
.ARB_LSB_HIGH_PRIO(1'b0)
)
stat_mux_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream inputs (sink)
*/
.s_axis(axis_eth_stat),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_stat)
);
// BASE-T PHY
taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
taxi_eth_mac_1g_rgmii_fifo #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.USE_CLK90(USE_CLK90),
.PADDING_EN(1),
.MIN_FRAME_LEN(64),
.STAT_EN(1),
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(0),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR("RGMII0"),
.TX_FIFO_DEPTH(16384),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(16384),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
/*
* Transmit interface (AXI stream)
*/
.s_axis_tx(axis_eth),
.m_axis_tx_cpl(axis_tx_cpl),
/*
* Receive interface (AXI stream)
*/
.m_axis_rx(axis_eth),
/*
* RGMII interface
*/
.rgmii_rx_clk(phy_rgmii_rx_clk),
.rgmii_rxd(phy_rgmii_rxd),
.rgmii_rx_ctl(phy_rgmii_rx_ctl),
.rgmii_tx_clk(phy_rgmii_tx_clk),
.rgmii_txd(phy_rgmii_txd),
.rgmii_tx_ctl(phy_rgmii_tx_ctl),
/*
* Statistics
*/
.stat_clk(clk),
.stat_rst(rst),
.m_axis_stat(axis_eth_stat[0]),
/*
* Status
*/
.tx_error_underflow(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.link_speed(),
/*
* Configuration
*/
.cfg_tx_max_pkt_len(16'd9218),
.cfg_tx_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_max_pkt_len(16'd9218),
.cfg_rx_enable(1'b1)
);
// QSFP28
assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire qsfp_tx_clk[4];
wire qsfp_tx_rst[4];
wire qsfp_rx_clk[4];
wire qsfp_rx_rst[4];
wire qsfp_rx_status[4];
assign led[0] = qsfp_rx_status[0];
assign led[1] = qsfp_rx_status[1];
assign led[2] = qsfp_rx_status[2];
assign led[3] = qsfp_rx_status[3];
wire qsfp_gtpowergood;
wire qsfp_mgt_refclk;
wire qsfp_mgt_refclk_int;
wire qsfp_mgt_refclk_bufg;
wire qsfp_rst;
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[4]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[4]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_rx[4]();
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat();
if (SIM) begin
assign qsfp_mgt_refclk = qsfp_mgt_refclk_p;
assign qsfp_mgt_refclk_int = qsfp_mgt_refclk_p;
assign qsfp_mgt_refclk_bufg = qsfp_mgt_refclk_int;
end else begin
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_inst (
.I (qsfp_mgt_refclk_p),
.IB (qsfp_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk),
.ODIV2 (qsfp_mgt_refclk_int)
);
BUFG_GT bufg_gt_qsfp_mgt_refclk_inst (
.CE (qsfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp_mgt_refclk_int),
.O (qsfp_mgt_refclk_bufg)
);
end
taxi_sync_reset #(
.N(4)
)
qsfp_sync_reset_inst (
.clk(qsfp_mgt_refclk_bufg),
.rst(rst),
.out(qsfp_rst)
);
taxi_apb_if #(
.ADDR_W(18),
.DATA_W(16)
)
gt_apb_ctrl();
taxi_xfcp_mod_apb #(
.XFCP_EXT_ID_STR("GTY CTRL")
)
xfcp_mod_apb_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_sw_ds[1]),
.xfcp_usp_us(xfcp_sw_us[1]),
/*
* APB master interface
*/
.m_apb(gt_apb_ctrl)
);
taxi_eth_mac_25g_us #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.CNT(4),
// GT config
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE("GTY"),
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),
.PTP_TS_FMT_TOD(1'b1),
.PTP_TS_W(96),
.PTP_TD_SDI_PIPELINE(2),
.PRBS31_EN(1'b0),
.TX_SERDES_PIPELINE(1),
.RX_SERDES_PIPELINE(1),
.COUNT_125US(125000/6.4),
.STAT_EN(1),
.STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1),
.STAT_ID_BASE(16+16),
.STAT_UPDATE_PERIOD(1024),
.STAT_STR_EN(1),
.STAT_PREFIX_STR('{"QSFP.1", "QSFP.2", "QSFP.3", "QSFP.4"})
)
qsfp_mac_inst (
.xcvr_ctrl_clk(clk),
.xcvr_ctrl_rst(qsfp_rst),
/*
* Transceiver control
*/
.s_apb_ctrl(gt_apb_ctrl),
/*
* Common
*/
.xcvr_gtpowergood_out(qsfp_gtpowergood),
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* Serial data
*/
.xcvr_txp(qsfp_tx_p),
.xcvr_txn(qsfp_tx_n),
.xcvr_rxp(qsfp_rx_p),
.xcvr_rxn(qsfp_rx_n),
/*
* MAC clocks
*/
.rx_clk(qsfp_rx_clk),
.rx_rst_in('{4{1'b0}}),
.rx_rst_out(qsfp_rx_rst),
.tx_clk(qsfp_tx_clk),
.tx_rst_in('{4{1'b0}}),
.tx_rst_out(qsfp_tx_rst),
/*
* Transmit interface (AXI stream)
*/
.s_axis_tx(axis_qsfp_tx),
.m_axis_tx_cpl(axis_qsfp_tx_cpl),
/*
* Receive interface (AXI stream)
*/
.m_axis_rx(axis_qsfp_rx),
/*
* PTP clock
*/
.ptp_clk(1'b0),
.ptp_rst(1'b0),
.ptp_sample_clk(1'b0),
.ptp_td_sdi(1'b0),
.tx_ptp_ts_in('{4{'0}}),
.tx_ptp_ts_out(),
.tx_ptp_ts_step_out(),
.tx_ptp_locked(),
.rx_ptp_ts_in('{4{'0}}),
.rx_ptp_ts_out(),
.rx_ptp_ts_step_out(),
.rx_ptp_locked(),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('{4{1'b0}}),
.tx_lfc_resend('{4{1'b0}}),
.rx_lfc_en('{4{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('{4{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('{4{1'b0}}),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{4{'0}}),
/*
* Pause interface
*/
.tx_lfc_pause_en('{4{1'b0}}),
.tx_pause_req('{4{1'b0}}),
.tx_pause_ack(),
/*
* Statistics
*/
.stat_clk(clk),
.stat_rst(rst),
.m_axis_stat(axis_eth_stat[1]),
/*
* Status
*/
.tx_start_packet(),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(),
.rx_start_packet(),
.rx_error_count(),
.rx_block_lock(),
.rx_high_ber(),
.rx_status(qsfp_rx_status),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('{4{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_tx_max_pkt_len('{4{16'd9218}}),
.cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}),
.cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
.cfg_mcf_rx_eth_src('{4{48'd0}}),
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
.cfg_mcf_rx_forward('{4{1'b0}}),
.cfg_mcf_rx_enable('{4{1'b0}}),
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
.cfg_tx_lfc_opcode('{4{16'h0001}}),
.cfg_tx_lfc_en('{4{1'b0}}),
.cfg_tx_lfc_quanta('{4{16'hffff}}),
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
.cfg_tx_pfc_opcode('{4{16'h0101}}),
.cfg_tx_pfc_en('{4{1'b0}}),
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{4{16'h0001}}),
.cfg_rx_lfc_en('{4{1'b0}}),
.cfg_rx_pfc_opcode('{4{16'h0101}}),
.cfg_rx_pfc_en('{4{1'b0}})
);
for (genvar n = 0; n < 4; n = n + 1) begin : qsfp_ch
taxi_axis_async_fifo #(
.DEPTH(16384),
.RAM_PIPELINE(2),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
ch_fifo (
/*
* AXI4-Stream input (sink)
*/
.s_clk(qsfp_rx_clk[n]),
.s_rst(qsfp_rx_rst[n]),
.s_axis(axis_qsfp_rx[n]),
/*
* AXI4-Stream output (source)
*/
.m_clk(qsfp_tx_clk[n]),
.m_rst(qsfp_tx_rst[n]),
.m_axis(axis_qsfp_tx[n]),
/*
* Pause
*/
.s_pause_req(1'b0),
.s_pause_ack(),
.m_pause_req(1'b0),
.m_pause_ack(),
/*
* Status
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),
.m_status_depth_commit(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end
endmodule
`resetall

63
src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/Makefile Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2020-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = fpga_core
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = $(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_SIM := "1'b1"
export PARAM_VENDOR := "\"XILINX\""
export PARAM_FAMILY := "\"kintexuplus\""
export PARAM_CFG_LOW_LATENCY := "1'b1"
export PARAM_COMBINED_MAC_PCS := "1'b1"
export PARAM_MAC_DATA_W := "64"
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

1
src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/baser.py Symbolic link
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../../lib/taxi/src/eth/tb/baser.py

309
src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: MIT
"""
Copyright (c) 2020-2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import logging
import os
import sys
import pytest
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer, Combine
from cocotbext.eth import GmiiFrame, RgmiiPhy
from cocotbext.eth import XgmiiFrame
from cocotbext.uart import UartSource, UartSink
try:
from baser import BaseRSerdesSource, BaseRSerdesSink
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from baser import BaseRSerdesSource, BaseRSerdesSink
finally:
del sys.path[0]
class TB:
def __init__(self, dut, speed=1000e6):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.qsfp_mgt_refclk_p, 6.4, units="ns").start())
self.baset_phy = RgmiiPhy(dut.phy_rgmii_txd, dut.phy_rgmii_tx_ctl, dut.phy_rgmii_tx_clk,
dut.phy_rgmii_rxd, dut.phy_rgmii_rx_ctl, dut.phy_rgmii_rx_clk, speed=speed)
self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
self.qsfp_sources = []
self.qsfp_sinks = []
for ch in dut.qsfp_mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64:
if ch.ch_inst.CFG_LOW_LATENCY.value:
clk = 2.482
gbx_cfg = (66, [64, 65])
else:
clk = 2.56
gbx_cfg = None
else:
if ch.ch_inst.CFG_LOW_LATENCY.value:
clk = 3.102
gbx_cfg = (66, [64, 65])
else:
clk = 3.2
gbx_cfg = None
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
self.qsfp_sources.append(BaseRSerdesSource(
data=gt_inst.serdes_rx_data,
data_valid=gt_inst.serdes_rx_data_valid,
hdr=gt_inst.serdes_rx_hdr,
hdr_valid=gt_inst.serdes_rx_hdr_valid,
clock=gt_inst.rx_clk,
slip=gt_inst.serdes_rx_bitslip,
reverse=True,
gbx_cfg=gbx_cfg
))
self.qsfp_sinks.append(BaseRSerdesSink(
data=gt_inst.serdes_tx_data,
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg
))
dut.btn.setimmediatevalue(0)
cocotb.start_soon(self._run_clk())
async def init(self):
self.dut.rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
for k in range(10):
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
for k in range(10):
await RisingEdge(self.dut.clk)
async def _run_clk(self):
t = Timer(2, 'ns')
while True:
self.dut.clk.value = 1
await t
self.dut.clk90.value = 1
await t
self.dut.clk.value = 0
await t
self.dut.clk90.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")
tb.log.info("Multiple small packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
for p in pkts:
await source.send(GmiiFrame.from_payload(p))
for k in range(count):
rx_frame = await sink.recv()
tb.log.info("RX frame: %s", rx_frame)
assert rx_frame.get_payload() == pkts[k]
assert rx_frame.check_fcs()
assert rx_frame.error is None
tb.log.info("Multiple large packets")
count = 32
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
for p in pkts:
await source.send(GmiiFrame.from_payload(p))
for k in range(count):
rx_frame = await sink.recv()
tb.log.info("RX frame: %s", rx_frame)
assert rx_frame.get_payload() == pkts[k]
assert rx_frame.check_fcs()
assert rx_frame.error is None
tb.log.info("MAC test done")
async def mac_test_25g(tb, source, sink):
tb.log.info("Test MAC")
tb.log.info("Wait for block lock")
for k in range(1200):
await RisingEdge(tb.dut.clk)
sink.clear()
tb.log.info("Multiple small packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
for p in pkts:
await source.send(XgmiiFrame.from_payload(p))
for k in range(count):
rx_frame = await sink.recv()
tb.log.info("RX frame: %s", rx_frame)
assert rx_frame.get_payload() == pkts[k]
assert rx_frame.check_fcs()
tb.log.info("Multiple large packets")
count = 32
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
for p in pkts:
await source.send(XgmiiFrame.from_payload(p))
for k in range(count):
rx_frame = await sink.recv()
tb.log.info("RX frame: %s", rx_frame)
assert rx_frame.get_payload() == pkts[k]
assert rx_frame.check_fcs()
tb.log.info("MAC test done")
@cocotb.test()
async def run_test(dut):
tb = TB(dut)
await tb.init()
tests = []
tb.log.info("Start BASE-T MAC loopback test")
tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
for k in range(len(tb.qsfp_sources)):
tb.log.info("Start QSFP %d MAC loopback test", k)
tests.append(cocotb.start_soon(mac_test_25g(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
await Combine(*tests)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("mac_data_w", [32, 64])
def test_fpga_core(request, mac_data_w):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
verilog_sources = [
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['SIM'] = "1'b1"
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"kintexuplus\""
parameters['CFG_LOW_LATENCY'] = "1'b1"
parameters['COMBINED_MAC_PCS'] = "1'b1"
parameters['MAC_DATA_W'] = mac_data_w
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)