cndm: Update boards

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -224,6 +224,15 @@ pyrite_inst (
     .qspi_1_cs(qspi_1_cs)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // QSFP28
 assign qsfp_0_sel_l = 1'b1;
 assign qsfp_1_sel_l = 1'b1;
@@ -573,7 +582,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(8),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -642,6 +654,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv

@@ -211,6 +211,15 @@ pyrite_inst (
     .qspi_1_cs()
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // SFP+
 wire sfp_tx_clk[2];
 wire sfp_tx_rst[2];
@@ -566,7 +575,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(2),
+    .PORTS($size(axis_sfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -635,6 +647,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/Alveo/fpga/rtl/fpga_core.sv

@@ -380,6 +380,15 @@ for (genvar n = 1; n < UART_CNT; n = n + 1) begin : uart_ch
 
 end
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // Ethernet
 assign eth_port_modsell = '1;
 assign eth_port_resetl = '1;
@@ -747,7 +756,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(GTY_CNT),
+    .PORTS($size(eth_gty_axis_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -816,6 +828,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv

@@ -343,6 +343,15 @@ stat_mux_inst (
     .m_axis(axis_stat)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // QSFP+
 assign qsfp0_fs = 2'b00;
 
@@ -742,7 +751,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(8),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -811,6 +823,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag_int),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_int),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/KCU105/fpga/rtl/fpga_core.sv

@@ -377,6 +377,15 @@ xfcp_mod_i2c_inst (
     .i2c_sda_o(i2c_sda_o)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // BASE-T PHY
 assign phy_reset_n = !rst_125mhz;
 
@@ -831,7 +840,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(2),
+    .PORTS($size(axis_sfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -900,6 +912,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag_int),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_int),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv

@@ -306,6 +306,15 @@ xfcp_stats_inst (
     .s_axis_stat(axis_stat)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // QSFP28
 assign qsfp_modsell = 1'b0;
 assign qsfp_resetl = 1'b1;
@@ -659,7 +668,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(4),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -728,6 +740,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/VCU108/fpga/rtl/fpga_core.sv

@@ -442,6 +442,15 @@ eth_mac_inst (
     .cfg_rx_enable(1'b1)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // QSFP28
 assign qsfp_modsell = 1'b0;
 assign qsfp_resetl = 1'b1;
@@ -810,7 +819,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(4),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -879,6 +891,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag_int),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_int),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/VCU118/fpga/rtl/fpga_core.sv

@@ -369,6 +369,15 @@ stat_mux_inst (
     .m_axis(axis_stat)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // BASE-T PHY
 assign phy_reset_n = !rst_125mhz;
 
@@ -997,7 +1006,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(8),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -1066,6 +1078,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv

@@ -255,6 +255,15 @@ xfcp_stats_inst (
     .s_axis_stat(axis_stat)
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // SFP+
 wire sfp_tx_clk[2];
 wire sfp_tx_rst[2];
@@ -609,7 +618,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(2),
+    .PORTS($size(axis_sfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -678,6 +690,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */

src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv

@@ -222,6 +222,15 @@ pyrite_inst (
     .qspi_1_cs()
 );
 
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
 // LED
 wire [7:0] led_g;
 wire [7:0] led_r;
@@ -616,7 +625,10 @@ cndm_micro_pcie_us #(
     .RELEASE_INFO(RELEASE_INFO),
 
     // Structural configuration
-    .PORTS(8),
+    .PORTS($size(axis_qsfp_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
 
     // PTP configuration
     .PTP_TS_EN(PTP_TS_EN),
@@ -685,6 +697,12 @@ cndm_inst (
     .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
     .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
 
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
     /*
      * PTP
      */