From 2616e3f3e3be2c1a8a48473d7ddc10942b00b040 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 8 Feb 2025 21:40:50 -0800 Subject: [PATCH] eth: Add 10G Ethernet combined MAC+PHY module and testbench Signed-off-by: Alex Forencich --- rtl/eth/taxi_eth_mac_phy_10g.f | 7 + rtl/eth/taxi_eth_mac_phy_10g.sv | 625 ++++++++++++++ rtl/eth/taxi_eth_mac_phy_10g_rx.f | 4 + rtl/eth/taxi_eth_mac_phy_10g_rx.sv | 167 ++++ rtl/eth/taxi_eth_mac_phy_10g_tx.f | 4 + rtl/eth/taxi_eth_mac_phy_10g_tx.sv | 149 ++++ tb/eth/taxi_eth_mac_phy_10g/Makefile | 65 ++ tb/eth/taxi_eth_mac_phy_10g/baser.py | 1 + .../test_taxi_eth_mac_phy_10g.py | 787 ++++++++++++++++++ .../test_taxi_eth_mac_phy_10g.sv | 304 +++++++ 10 files changed, 2113 insertions(+) create mode 100644 rtl/eth/taxi_eth_mac_phy_10g.f create mode 100644 rtl/eth/taxi_eth_mac_phy_10g.sv create mode 100644 rtl/eth/taxi_eth_mac_phy_10g_rx.f create mode 100644 rtl/eth/taxi_eth_mac_phy_10g_rx.sv create mode 100644 rtl/eth/taxi_eth_mac_phy_10g_tx.f create mode 100644 rtl/eth/taxi_eth_mac_phy_10g_tx.sv create mode 100644 tb/eth/taxi_eth_mac_phy_10g/Makefile create mode 120000 tb/eth/taxi_eth_mac_phy_10g/baser.py create mode 100644 tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py create mode 100644 tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g.f b/rtl/eth/taxi_eth_mac_phy_10g.f new file mode 100644 index 0000000..36ef62f --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g.f @@ -0,0 +1,7 @@ +taxi_eth_mac_phy_10g.sv +taxi_eth_mac_phy_10g_rx.f +taxi_eth_mac_phy_10g_tx.f +taxi_mac_ctrl_tx.sv +taxi_mac_ctrl_rx.sv +taxi_mac_pause_ctrl_tx.sv +taxi_mac_pause_ctrl_rx.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g.sv b/rtl/eth/taxi_eth_mac_phy_10g.sv new file mode 100644 index 0000000..8524657 --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g.sv @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2019-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet MAC/PHY combination + */ +module taxi_eth_mac_phy_10g # +( + parameter DATA_W = 64, + parameter HDR_W = (DATA_W/32), + parameter logic PADDING_EN = 1'b1, + parameter logic DIC_EN = 1'b1, + parameter MIN_FRAME_LEN = 64, + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 0, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4, + parameter logic PFC_EN = 1'b0, + parameter logic PAUSE_EN = PFC_EN +) +( + input wire logic rx_clk, + input wire logic rx_rst, + input wire logic tx_clk, + input wire logic tx_rst, + + /* + * Transmit interface (AXI stream) + */ + taxi_axis_if.snk s_axis_tx, + taxi_axis_if.src m_axis_tx_cpl, + + /* + * Receive interface (AXI stream) + */ + taxi_axis_if.src m_axis_rx, + + /* + * SERDES interface + */ + output wire logic [DATA_W-1:0] serdes_tx_data, + output wire logic [HDR_W-1:0] serdes_tx_hdr, + input wire logic [DATA_W-1:0] serdes_rx_data, + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + output wire logic serdes_rx_reset_req, + + /* + * PTP + */ + input wire logic [PTP_TS_W-1:0] tx_ptp_ts, + input wire logic [PTP_TS_W-1:0] rx_ptp_ts, + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire logic tx_lfc_req = 1'b0, + input wire logic tx_lfc_resend = 1'b0, + input wire logic rx_lfc_en = 1'b0, + output wire logic rx_lfc_req, + input wire logic rx_lfc_ack = 1'b0, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire logic [7:0] tx_pfc_req = '0, + input wire logic tx_pfc_resend = 1'b0, + input wire logic [7:0] rx_pfc_en = '0, + output wire logic [7:0] rx_pfc_req, + input wire logic [7:0] rx_pfc_ack = '0, + + /* + * Pause interface + */ + input wire logic tx_lfc_pause_en = 1'b0, + input wire logic tx_pause_req = 1'b0, + output wire logic tx_pause_ack, + + /* + * Status + */ + output wire logic [1:0] tx_start_packet, + output wire logic tx_error_underflow, + output wire logic [1:0] rx_start_packet, + output wire logic [6:0] rx_error_count, + output wire logic rx_error_bad_frame, + output wire logic rx_error_bad_fcs, + output wire logic rx_bad_block, + output wire logic rx_sequence_error, + output wire logic rx_block_lock, + output wire logic rx_high_ber, + output wire logic rx_status, + output wire logic stat_tx_mcf, + output wire logic stat_rx_mcf, + output wire logic stat_tx_lfc_pkt, + output wire logic stat_tx_lfc_xon, + output wire logic stat_tx_lfc_xoff, + output wire logic stat_tx_lfc_paused, + output wire logic stat_tx_pfc_pkt, + output wire logic [7:0] stat_tx_pfc_xon, + output wire logic [7:0] stat_tx_pfc_xoff, + output wire logic [7:0] stat_tx_pfc_paused, + output wire logic stat_rx_lfc_pkt, + output wire logic stat_rx_lfc_xon, + output wire logic stat_rx_lfc_xoff, + output wire logic stat_rx_lfc_paused, + output wire logic stat_rx_pfc_pkt, + output wire logic [7:0] stat_rx_pfc_xon, + output wire logic [7:0] stat_rx_pfc_xoff, + output wire logic [7:0] stat_rx_pfc_paused, + + /* + * Configuration + */ + input wire logic [7:0] cfg_ifg = 8'd12, + input wire logic cfg_tx_enable = 1'b1, + input wire logic cfg_rx_enable = 1'b1, + input wire logic cfg_tx_prbs31_enable = 1'b0, + input wire logic cfg_rx_prbs31_enable = 1'b0, + input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01, + input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1, + input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast = 48'd0, + input wire logic cfg_mcf_rx_check_eth_dst_ucast = 1'b0, + input wire logic [47:0] cfg_mcf_rx_eth_src = 48'd0, + input wire logic cfg_mcf_rx_check_eth_src = 1'b0, + input wire logic [15:0] cfg_mcf_rx_eth_type = 16'h8808, + input wire logic [15:0] cfg_mcf_rx_opcode_lfc = 16'h0001, + input wire logic cfg_mcf_rx_check_opcode_lfc = 1'b1, + input wire logic [15:0] cfg_mcf_rx_opcode_pfc = 16'h0101, + input wire logic cfg_mcf_rx_check_opcode_pfc = 1'b1, + input wire logic cfg_mcf_rx_forward = 1'b0, + input wire logic cfg_mcf_rx_enable = 1'b0, + input wire logic [47:0] cfg_tx_lfc_eth_dst = 48'h01_80_C2_00_00_01, + input wire logic [47:0] cfg_tx_lfc_eth_src = 48'h80_23_31_43_54_4C, + input wire logic [15:0] cfg_tx_lfc_eth_type = 16'h8808, + input wire logic [15:0] cfg_tx_lfc_opcode = 16'h0001, + input wire logic cfg_tx_lfc_en = 1'b0, + input wire logic [15:0] cfg_tx_lfc_quanta = 16'hffff, + input wire logic [15:0] cfg_tx_lfc_refresh = 16'h7fff, + input wire logic [47:0] cfg_tx_pfc_eth_dst = 48'h01_80_C2_00_00_01, + input wire logic [47:0] cfg_tx_pfc_eth_src = 48'h80_23_31_43_54_4C, + input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808, + input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101, + input wire logic cfg_tx_pfc_en = 1'b0, + input wire logic [8*16-1:0] cfg_tx_pfc_quanta = {8{16'hffff}}, + input wire logic [8*16-1:0] cfg_tx_pfc_refresh = {8{16'h7fff}}, + input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001, + input wire logic cfg_rx_lfc_en = 1'b0, + input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101, + input wire logic cfg_rx_pfc_en = 1'b0 +); + +localparam KEEP_W = s_axis_tx.KEEP_W; +localparam TX_USER_W = 1; +localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; +localparam TX_TAG_W = s_axis_tx.ID_W; + +localparam MAC_CTRL_EN = PAUSE_EN || PFC_EN; +localparam TX_USER_W_INT = (MAC_CTRL_EN ? 1 : 0) + TX_USER_W; + +taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W_INT), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int(); +taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int(); + +taxi_eth_mac_phy_10g_rx #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_mac_phy_10g_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_rx_int), + + /* + * SERDES interface + */ + .serdes_rx_data(serdes_rx_data), + .serdes_rx_hdr(serdes_rx_hdr), + .serdes_rx_bitslip(serdes_rx_bitslip), + .serdes_rx_reset_req(serdes_rx_reset_req), + + /* + * PTP + */ + .ptp_ts(rx_ptp_ts), + + /* + * Status + */ + .rx_start_packet(rx_start_packet), + .rx_error_count(rx_error_count), + .rx_error_bad_frame(rx_error_bad_frame), + .rx_error_bad_fcs(rx_error_bad_fcs), + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status), + + /* + * Configuration + */ + .cfg_rx_enable(cfg_rx_enable), + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) +); + +taxi_eth_mac_phy_10g_tx #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .PADDING_EN(PADDING_EN), + .DIC_EN(DIC_EN), + .MIN_FRAME_LEN(MIN_FRAME_LEN), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .TX_CPL_CTRL_IN_TUSER(MAC_CTRL_EN), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(TX_SERDES_PIPELINE) +) +eth_mac_phy_10g_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_tx_int), + .m_axis_tx_cpl(m_axis_tx_cpl), + + /* + * SERDES interface + */ + .serdes_tx_data(serdes_tx_data), + .serdes_tx_hdr(serdes_tx_hdr), + + /* + * PTP + */ + .ptp_ts(tx_ptp_ts), + + /* + * Status + */ + .tx_start_packet(tx_start_packet), + .tx_error_underflow(tx_error_underflow), + + /* + * Configuration + */ + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) +); + +if (MAC_CTRL_EN) begin : mac_ctrl + + localparam MCF_PARAMS_SIZE = PFC_EN ? 18 : 2; + + wire tx_mcf_valid; + wire tx_mcf_ready; + wire [47:0] tx_mcf_eth_dst; + wire [47:0] tx_mcf_eth_src; + wire [15:0] tx_mcf_eth_type; + wire [15:0] tx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params; + + wire rx_mcf_valid; + wire [47:0] rx_mcf_eth_dst; + wire [47:0] rx_mcf_eth_src; + wire [15:0] rx_mcf_eth_type; + wire [15:0] rx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params; + + // terminate LFC pause requests from RX internally on TX side + wire tx_pause_req_int; + wire rx_lfc_ack_int; + + reg tx_lfc_req_sync_reg_1 = 1'b0; + reg tx_lfc_req_sync_reg_2 = 1'b0; + reg tx_lfc_req_sync_reg_3 = 1'b0; + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + tx_lfc_req_sync_reg_1 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_1 <= rx_lfc_req; + end + end + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_lfc_req_sync_reg_2 <= 1'b0; + tx_lfc_req_sync_reg_3 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1; + tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2; + end + end + + reg rx_lfc_ack_sync_reg_1 = 1'b0; + reg rx_lfc_ack_sync_reg_2 = 1'b0; + reg rx_lfc_ack_sync_reg_3 = 1'b0; + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + rx_lfc_ack_sync_reg_1 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0; + end + end + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_lfc_ack_sync_reg_2 <= 1'b0; + rx_lfc_ack_sync_reg_3 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1; + rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2; + end + end + + assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0); + + assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3; + + taxi_mac_ctrl_tx #( + .ID_W(s_axis_tx.ID_W), + .DEST_W(s_axis_tx.DEST_W), + .USER_W(TX_USER_W_INT), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * AXI stream input + */ + .s_axis(s_axis_tx), + + /* + * AXI stream output + */ + .m_axis(axis_tx_int), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + .mcf_id('0), + .mcf_dest('0), + .mcf_user(2'b10), + + /* + * Pause interface + */ + .tx_pause_req(tx_pause_req_int), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .stat_tx_mcf(stat_tx_mcf) + ); + + taxi_mac_ctrl_rx #( + .USER_W(RX_USER_W), + .USE_READY(0), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * AXI stream input + */ + .s_axis(axis_rx_int), + + /* + * AXI stream output + */ + .m_axis(m_axis_rx), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + .mcf_id(), + .mcf_dest(), + .mcf_user(), + + /* + * Configuration + */ + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_EN), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + + /* + * Status + */ + .stat_rx_mcf(stat_rx_mcf) + ); + + taxi_mac_pause_ctrl_tx #( + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE), + .PFC_EN(PFC_EN) + ) + mac_pause_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + + /* + * Configuration + */ + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_quanta_step(10'((DATA_W*256)/512)), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused) + ); + + taxi_mac_pause_ctrl_rx #( + .MCF_PARAMS_SIZE(18), + .PFC_EN(PFC_EN) + ) + mac_pause_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack_int), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Configuration + */ + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en), + .cfg_quanta_step(10'((DATA_W*256)/512)), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused) + ); + +end else begin + + assign axis_tx_int.tdata = s_axis_tx.tdata; + assign axis_tx_int.tkeep = s_axis_tx.tkeep; + assign axis_tx_int.tvalid = s_axis_tx.tvalid; + assign s_axis_tx.tready = axis_tx_int.tready; + assign axis_tx_int.tlast = s_axis_tx.tlast; + assign axis_tx_int.tid = s_axis_tx.tid; + assign axis_tx_int.tdest = s_axis_tx.tdest; + assign axis_tx_int.tuser = s_axis_tx.tuser; + + assign m_axis_rx.tdata = axis_rx_int.tdata; + assign m_axis_rx.tkeep = axis_rx_int.tkeep; + assign m_axis_rx.tvalid = axis_rx_int.tvalid; + assign m_axis_rx.tlast = axis_rx_int.tlast; + assign m_axis_rx.tid = axis_rx_int.tid; + assign m_axis_rx.tdest = axis_rx_int.tdest; + assign m_axis_rx.tuser = axis_rx_int.tuser; + + assign rx_lfc_req = 0; + assign rx_pfc_req = 0; + assign tx_pause_ack = 0; + + assign stat_tx_mcf = 0; + assign stat_rx_mcf = 0; + assign stat_tx_lfc_pkt = 0; + assign stat_tx_lfc_xon = 0; + assign stat_tx_lfc_xoff = 0; + assign stat_tx_lfc_paused = 0; + assign stat_tx_pfc_pkt = 0; + assign stat_tx_pfc_xon = 0; + assign stat_tx_pfc_xoff = 0; + assign stat_tx_pfc_paused = 0; + assign stat_rx_lfc_pkt = 0; + assign stat_rx_lfc_xon = 0; + assign stat_rx_lfc_xoff = 0; + assign stat_rx_lfc_paused = 0; + assign stat_rx_pfc_pkt = 0; + assign stat_rx_pfc_xon = 0; + assign stat_rx_pfc_xoff = 0; + assign stat_rx_pfc_paused = 0; + +end + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_mac_phy_10g_rx.f b/rtl/eth/taxi_eth_mac_phy_10g_rx.f new file mode 100644 index 0000000..4711713 --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g_rx.f @@ -0,0 +1,4 @@ +taxi_eth_mac_phy_10g_rx.sv +taxi_eth_phy_10g_rx_if.f +taxi_axis_baser_rx_64.sv +../lfsr/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g_rx.sv b/rtl/eth/taxi_eth_mac_phy_10g_rx.sv new file mode 100644 index 0000000..2b117bc --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g_rx.sv @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2019-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet MAC/PHY combination + */ +module taxi_eth_mac_phy_10g_rx # +( + parameter DATA_W = 64, + parameter HDR_W = (DATA_W/32), + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 0, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic clk, + input wire logic rst, + + /* + * Receive interface (AXI stream) + */ + taxi_axis_if.src m_axis_rx, + + /* + * SERDES interface + */ + input wire logic [DATA_W-1:0] serdes_rx_data, + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + output wire logic serdes_rx_reset_req, + + /* + * PTP + */ + input wire logic [PTP_TS_W-1:0] ptp_ts, + + /* + * Status + */ + output wire logic [1:0] rx_start_packet, + output wire logic [6:0] rx_error_count, + output wire logic rx_error_bad_frame, + output wire logic rx_error_bad_fcs, + output wire logic rx_bad_block, + output wire logic rx_sequence_error, + output wire logic rx_block_lock, + output wire logic rx_high_ber, + output wire logic rx_status, + + /* + * Configuration + */ + input wire logic cfg_rx_enable, + input wire logic cfg_rx_prbs31_enable +); + +wire [DATA_W-1:0] encoded_rx_data; +wire [HDR_W-1:0] encoded_rx_hdr; + +taxi_eth_phy_10g_rx_if #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_phy_10g_rx_if_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded interface + */ + .encoded_rx_data(encoded_rx_data), + .encoded_rx_hdr(encoded_rx_hdr), + + /* + * SERDES interface + */ + .serdes_rx_data(serdes_rx_data), + .serdes_rx_hdr(serdes_rx_hdr), + .serdes_rx_bitslip(serdes_rx_bitslip), + .serdes_rx_reset_req(serdes_rx_reset_req), + + /* + * Status + */ + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_error_count(rx_error_count), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status), + + /* + * Configuration + */ + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) +); + +taxi_axis_baser_rx_64 #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W) +) +axis_baser_rx_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded input + */ + .encoded_rx_data(encoded_rx_data), + .encoded_rx_hdr(encoded_rx_hdr), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(m_axis_rx), + + /* + * PTP + */ + .ptp_ts(ptp_ts), + + /* + * Configuration + */ + .cfg_rx_enable(cfg_rx_enable), + + /* + * Status + */ + .start_packet(rx_start_packet), + .error_bad_frame(rx_error_bad_frame), + .error_bad_fcs(rx_error_bad_fcs), + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error) +); + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_mac_phy_10g_tx.f b/rtl/eth/taxi_eth_mac_phy_10g_tx.f new file mode 100644 index 0000000..dc86ab5 --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g_tx.f @@ -0,0 +1,4 @@ +taxi_eth_mac_phy_10g_tx.sv +taxi_eth_phy_10g_tx_if.f +taxi_axis_baser_tx_64.sv +../lfsr/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_mac_phy_10g_tx.sv b/rtl/eth/taxi_eth_mac_phy_10g_tx.sv new file mode 100644 index 0000000..f2b15a7 --- /dev/null +++ b/rtl/eth/taxi_eth_mac_phy_10g_tx.sv @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2019-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet MAC/PHY combination + */ +module taxi_eth_mac_phy_10g_tx # +( + parameter DATA_W = 64, + parameter HDR_W = (DATA_W/32), + parameter logic PADDING_EN = 1'b1, + parameter logic DIC_EN = 1'b1, + parameter MIN_FRAME_LEN = 64, + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64, + parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * Transmit interface (AXI stream) + */ + taxi_axis_if.snk s_axis_tx, + taxi_axis_if.src m_axis_tx_cpl, + + /* + * SERDES interface + */ + output wire logic [DATA_W-1:0] serdes_tx_data, + output wire logic [HDR_W-1:0] serdes_tx_hdr, + + /* + * PTP + */ + input wire logic [PTP_TS_W-1:0] ptp_ts, + + /* + * Status + */ + output wire logic [1:0] tx_start_packet, + output wire logic tx_error_underflow, + + /* + * Configuration + */ + input wire logic [7:0] cfg_ifg, + input wire logic cfg_tx_enable, + input wire logic cfg_tx_prbs31_enable +); + +wire [DATA_W-1:0] encoded_tx_data; +wire [HDR_W-1:0] encoded_tx_hdr; + +taxi_axis_baser_tx_64 #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .PADDING_EN(PADDING_EN), + .DIC_EN(DIC_EN), + .MIN_FRAME_LEN(MIN_FRAME_LEN), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER) +) +axis_baser_tx_inst ( + .clk(clk), + .rst(rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(s_axis_tx), + .m_axis_tx_cpl(m_axis_tx_cpl), + + /* + * 10GBASE-R encoded interface + */ + .encoded_tx_data(encoded_tx_data), + .encoded_tx_hdr(encoded_tx_hdr), + + /* + * PTP + */ + .ptp_ts(ptp_ts), + + /* + * Configuration + */ + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + + /* + * Status + */ + .start_packet(tx_start_packet), + .error_underflow(tx_error_underflow) +); + +taxi_eth_phy_10g_tx_if #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(SERDES_PIPELINE) +) +eth_phy_10g_tx_if_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded interface + */ + .encoded_tx_data(encoded_tx_data), + .encoded_tx_hdr(encoded_tx_hdr), + + /* + * SERDES interface + */ + .serdes_tx_data(serdes_tx_data), + .serdes_tx_hdr(serdes_tx_hdr), + + /* + * Configuration + */ + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/tb/eth/taxi_eth_mac_phy_10g/Makefile b/tb/eth/taxi_eth_mac_phy_10g/Makefile new file mode 100644 index 0000000..d76bd07 --- /dev/null +++ b/tb/eth/taxi_eth_mac_phy_10g/Makefile @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_eth_mac_phy_10g +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f +VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 64 +export PARAM_HDR_W := 2 +export PARAM_PADDING_EN := 1 +export PARAM_DIC_EN := 1 +export PARAM_MIN_FRAME_LEN := 64 +export PARAM_PTP_TS_EN := 1 +export PARAM_PTP_TS_FMT_TOD := 1 +export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) +export PARAM_TX_TAG_W := 16 +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_EN := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 0 +export PARAM_BITSLIP_LOW_CYCLES := 7 +export PARAM_COUNT_125US := 195 +export PARAM_PFC_EN := 1 +export PARAM_PAUSE_EN := $(PARAM_PFC_EN) + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_eth_mac_phy_10g/baser.py b/tb/eth/taxi_eth_mac_phy_10g/baser.py new file mode 120000 index 0000000..33a2368 --- /dev/null +++ b/tb/eth/taxi_eth_mac_phy_10g/baser.py @@ -0,0 +1 @@ +../baser.py \ No newline at end of file diff --git a/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py b/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py new file mode 100644 index 0000000..20a0606 --- /dev/null +++ b/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py @@ -0,0 +1,787 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import struct +import sys + +from scapy.layers.l2 import Ether + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps +from cocotb.regression import TestFactory + +from cocotbext.eth import XgmiiFrame, PtpClockSimTime +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + if len(dut.serdes_tx_data) == 64: + self.clk_period = 6.4 + else: + self.clk_period = 3.2 + + cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start()) + cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start()) + + self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip) + self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk) + + self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst) + self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst) + self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst) + + self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk) + self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk) + + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) + + async def reset(self): + self.dut.rx_rst.setimmediatevalue(0) + self.dut.tx_rst.setimmediatevalue(0) + await RisingEdge(self.dut.rx_clk) + await RisingEdge(self.dut.rx_clk) + self.dut.rx_rst.value = 1 + self.dut.tx_rst.value = 1 + await RisingEdge(self.dut.rx_clk) + await RisingEdge(self.dut.rx_clk) + self.dut.rx_rst.value = 0 + self.dut.tx_rst.value = 0 + await RisingEdge(self.dut.rx_clk) + await RisingEdge(self.dut.rx_clk) + + +async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.dut.cfg_rx_enable.value = 0 + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + tb.dut.cfg_rx_enable.value = 1 + + test_frames = [payload_data(x) for x in payload_lengths()] + tx_frames = [] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append) + await tb.serdes_source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.axis_sink.recv() + tx_frame = tx_frames.pop(0) + + frame_error = rx_frame.tuser & 1 + ptp_ts = rx_frame.tuser >> 1 + ptp_ts_ns = ptp_ts / 2**16 + + print(tx_frame) + + tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns") + + if tx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + tx_frame_sfd_ns -= tb.clk_period/2 + + tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) + + assert rx_frame.tdata == test_data + assert frame_error == 0 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*4) < 0.01 + + assert tb.axis_sink.empty() + + await RisingEdge(dut.rx_clk) + await RisingEdge(dut.rx_clk) + + +async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0)) + + for test_data in test_frames: + rx_frame = await tb.serdes_sink.recv() + tx_cpl = await tb.tx_cpl_sink.recv() + + ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= tb.clk_period/2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < 0.01 + + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_tx_alignment(dut, payload_data=None, ifg=12): + + dic_en = int(cocotb.top.DIC_EN.value) + + tb = TB(dut) + + byte_width = tb.axis_source.width // 8 + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.dut.cfg_tx_enable.value = 1 + + for length in range(60, 92): + + for k in range(10): + await RisingEdge(dut.tx_clk) + + test_frames = [payload_data(length) for k in range(10)] + start_lane = [] + + for test_data in test_frames: + await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0)) + + for test_data in test_frames: + rx_frame = await tb.serdes_sink.recv() + tx_cpl = await tb.tx_cpl_sink.recv() + + ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= 3.2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < 0.01 + + start_lane.append(rx_frame.start_lane) + + tb.log.info("length: %d", length) + tb.log.info("start_lane: %s", start_lane) + + start_lane_ref = [] + + # compute expected starting lanes + lane = 0 + deficit_idle_count = 0 + + for test_data in test_frames: + if ifg == 0: + lane = 0 + + start_lane_ref.append(lane) + lane = (lane + len(test_data)+4+ifg) % byte_width + + if dic_en: + offset = lane % 4 + if deficit_idle_count+offset >= 4: + offset += 4 + lane = (lane - offset) % byte_width + deficit_idle_count = (deficit_idle_count + offset) % 4 + else: + offset = lane % 4 + if offset > 0: + offset += 4 + lane = (lane - offset) % byte_width + + tb.log.info("start_lane_ref: %s", start_lane_ref) + + assert start_lane_ref == start_lane + + await RisingEdge(dut.tx_clk) + + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_tx_underrun(dut, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.dut.cfg_tx_enable.value = 1 + + test_data = bytes(x for x in range(60)) + + for k in range(3): + test_frame = AxiStreamFrame(test_data) + await tb.axis_source.send(test_frame) + + for k in range(64*16 // tb.axis_source.width): + await RisingEdge(dut.tx_clk) + + tb.axis_source.pause = True + + for k in range(4): + await RisingEdge(dut.tx_clk) + + tb.axis_source.pause = False + + for k in range(3): + rx_frame = await tb.serdes_sink.recv() + + if k == 1: + assert rx_frame.data[-1] == 0xFE + assert rx_frame.ctrl[-1] == 1 + else: + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_tx_error(dut, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.dut.cfg_tx_enable.value = 1 + + test_data = bytes(x for x in range(60)) + + for k in range(3): + test_frame = AxiStreamFrame(test_data) + if k == 1: + test_frame.tuser = 1 + await tb.axis_source.send(test_frame) + + for k in range(3): + rx_frame = await tb.serdes_sink.recv() + + if k == 1: + assert rx_frame.data[-1] == 0xFE + assert rx_frame.ctrl[-1] == 1 + else: + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_rx_frame_sync(dut): + + tb = TB(dut) + + await tb.reset() + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + assert int(dut.rx_block_lock.value) + + tb.log.info("Change offset") + tb.serdes_source.bit_offset = 33 + + for k in range(100): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for lock lost") + assert not int(dut.rx_block_lock.value) + assert int(dut.rx_high_ber.value) + + for k in range(500): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for block lock") + assert int(dut.rx_block_lock.value) + + for k in range(300): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for high BER deassert") + assert not int(dut.rx_high_ber.value) + + await RisingEdge(dut.rx_clk) + await RisingEdge(dut.rx_clk) + + +async def run_test_lfc(dut, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 1 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.serdes_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.serdes_source.send(test_frame) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while not dut.rx_lfc_req.value.integer: + await RisingEdge(dut.tx_clk) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_lfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.serdes_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_lfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_lfc_cnt == 4 + + assert tb.axis_sink.empty() + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_pfc(dut, ifg=12): + + tb = TB(dut) + + tb.serdes_source.ifg = ifg + tb.dut.cfg_ifg.value = ifg + + await tb.reset() + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + tb.dut.cfg_tx_enable.value = 1 + tb.dut.cfg_rx_enable.value = 1 + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + dut.rx_pfc_en.value = 0xff + dut.rx_pfc_ack.value = 0x00 + + dut.tx_lfc_pause_en.value = 0 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.serdes_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.serdes_source.send(test_frame) + + for i in range(8): + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0xff >> (7-i) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0x00 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_pfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.serdes_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_pfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_pfc_cnt == 9 + + assert tb.axis_sink.empty() + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + for test in [run_test_rx, run_test_tx]: + + factory = TestFactory(test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12, 0]) + factory.generate_tests() + + factory = TestFactory(run_test_tx_alignment) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.generate_tests() + + for test in [run_test_tx_underrun, run_test_tx_error]: + + factory = TestFactory(test) + factory.add_option("ifg", [12]) + factory.generate_tests() + + factory = TestFactory(run_test_rx_frame_sync) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)]) +@pytest.mark.parametrize("data_w", [64]) +def test_taxi_eth_mac_phy_10g(request, data_w, dic_en, pfc_en): + dut = "taxi_eth_mac_phy_10g" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "eth", f"{dut}.f"), + os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = data_w + parameters['HDR_W'] = 2 + parameters['PADDING_EN'] = 1 + parameters['DIC_EN'] = dic_en + parameters['MIN_FRAME_LEN'] = 64 + parameters['PTP_TS_EN'] = 1 + parameters['PTP_TS_FMT_TOD'] = 1 + parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64 + parameters['TX_TAG_W'] = 16 + parameters['BIT_REVERSE'] = 0 + parameters['SCRAMBLER_DISABLE'] = 0 + parameters['PRBS31_EN'] = 1 + parameters['TX_SERDES_PIPELINE'] = 2 + parameters['RX_SERDES_PIPELINE'] = 2 + parameters['BITSLIP_HIGH_CYCLES'] = 0 + parameters['BITSLIP_LOW_CYCLES'] = 7 + parameters['COUNT_125US'] = int(1250/6.4) + parameters['PFC_EN'] = pfc_en + parameters['PAUSE_EN'] = parameters['PFC_EN'] + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv b/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv new file mode 100644 index 0000000..6e0784b --- /dev/null +++ b/tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet MAC/PHY testbench + */ +module test_taxi_eth_mac_phy_10g # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DATA_W = 64, + parameter KEEP_W = (DATA_W/8), + parameter HDR_W = (DATA_W/32), + parameter logic PADDING_EN = 1'b1, + parameter logic DIC_EN = 1'b1, + parameter MIN_FRAME_LEN = 64, + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64, + parameter TX_TAG_W = 16, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 0, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4, + parameter logic PFC_EN = 1'b0, + parameter logic PAUSE_EN = PFC_EN + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam TX_USER_W = 1; +localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; + +logic rx_clk; +logic rx_rst; +logic tx_clk; +logic tx_rst; + +taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx(); +taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl(); +taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx(); + +logic [DATA_W-1:0] serdes_tx_data; +logic [HDR_W-1:0] serdes_tx_hdr; +logic [DATA_W-1:0] serdes_rx_data; +logic [HDR_W-1:0] serdes_rx_hdr; +logic serdes_rx_bitslip; +logic serdes_rx_reset_req; + +logic [PTP_TS_W-1:0] tx_ptp_ts; +logic [PTP_TS_W-1:0] rx_ptp_ts; + +logic tx_lfc_req; +logic tx_lfc_resend; +logic rx_lfc_en; +logic rx_lfc_req; +logic rx_lfc_ack; + +logic [7:0] tx_pfc_req; +logic tx_pfc_resend; +logic [7:0] rx_pfc_en; +logic [7:0] rx_pfc_req; +logic [7:0] rx_pfc_ack; + +logic tx_lfc_pause_en; +logic tx_pause_req; +logic tx_pause_ack; + +logic [1:0] tx_start_packet; +logic tx_error_underflow; +logic [1:0] rx_start_packet; +logic [6:0] rx_error_count; +logic rx_error_bad_frame; +logic rx_error_bad_fcs; +logic rx_bad_block; +logic rx_sequence_error; +logic rx_block_lock; +logic rx_high_ber; +logic rx_status; +logic stat_tx_mcf; +logic stat_rx_mcf; +logic stat_tx_lfc_pkt; +logic stat_tx_lfc_xon; +logic stat_tx_lfc_xoff; +logic stat_tx_lfc_paused; +logic stat_tx_pfc_pkt; +logic [7:0] stat_tx_pfc_xon; +logic [7:0] stat_tx_pfc_xoff; +logic [7:0] stat_tx_pfc_paused; +logic stat_rx_lfc_pkt; +logic stat_rx_lfc_xon; +logic stat_rx_lfc_xoff; +logic stat_rx_lfc_paused; +logic stat_rx_pfc_pkt; +logic [7:0] stat_rx_pfc_xon; +logic [7:0] stat_rx_pfc_xoff; +logic [7:0] stat_rx_pfc_paused; + +logic [7:0] cfg_ifg; +logic cfg_tx_enable; +logic cfg_rx_enable; +logic cfg_tx_prbs31_enable; +logic cfg_rx_prbs31_enable; +logic [47:0] cfg_mcf_rx_eth_dst_mcast; +logic cfg_mcf_rx_check_eth_dst_mcast; +logic [47:0] cfg_mcf_rx_eth_dst_ucast; +logic cfg_mcf_rx_check_eth_dst_ucast; +logic [47:0] cfg_mcf_rx_eth_src; +logic cfg_mcf_rx_check_eth_src; +logic [15:0] cfg_mcf_rx_eth_type; +logic [15:0] cfg_mcf_rx_opcode_lfc; +logic cfg_mcf_rx_check_opcode_lfc; +logic [15:0] cfg_mcf_rx_opcode_pfc; +logic cfg_mcf_rx_check_opcode_pfc; +logic cfg_mcf_rx_forward; +logic cfg_mcf_rx_enable; +logic [47:0] cfg_tx_lfc_eth_dst; +logic [47:0] cfg_tx_lfc_eth_src; +logic [15:0] cfg_tx_lfc_eth_type; +logic [15:0] cfg_tx_lfc_opcode; +logic cfg_tx_lfc_en; +logic [15:0] cfg_tx_lfc_quanta; +logic [15:0] cfg_tx_lfc_refresh; +logic [47:0] cfg_tx_pfc_eth_dst; +logic [47:0] cfg_tx_pfc_eth_src; +logic [15:0] cfg_tx_pfc_eth_type; +logic [15:0] cfg_tx_pfc_opcode; +logic cfg_tx_pfc_en; +logic [8*16-1:0] cfg_tx_pfc_quanta; +logic [8*16-1:0] cfg_tx_pfc_refresh; +logic [15:0] cfg_rx_lfc_opcode; +logic cfg_rx_lfc_en; +logic [15:0] cfg_rx_pfc_opcode; +logic cfg_rx_pfc_en; + +taxi_eth_mac_phy_10g #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .PADDING_EN(PADDING_EN), + .DIC_EN(DIC_EN), + .MIN_FRAME_LEN(MIN_FRAME_LEN), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US), + .PFC_EN(PFC_EN), + .PAUSE_EN(PAUSE_EN) +) +uut ( + .rx_clk(rx_clk), + .rx_rst(rx_rst), + .tx_clk(tx_clk), + .tx_rst(tx_rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(s_axis_tx), + .m_axis_tx_cpl(m_axis_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(m_axis_rx), + + /* + * SERDES interface + */ + .serdes_tx_data(serdes_tx_data), + .serdes_tx_hdr(serdes_tx_hdr), + .serdes_rx_data(serdes_rx_data), + .serdes_rx_hdr(serdes_rx_hdr), + .serdes_rx_bitslip(serdes_rx_bitslip), + .serdes_rx_reset_req(serdes_rx_reset_req), + + /* + * PTP + */ + .tx_ptp_ts(tx_ptp_ts), + .rx_ptp_ts(rx_ptp_ts), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Pause interface + */ + .tx_lfc_pause_en(tx_lfc_pause_en), + .tx_pause_req(tx_pause_req), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .tx_start_packet(tx_start_packet), + .tx_error_underflow(tx_error_underflow), + .rx_start_packet(rx_start_packet), + .rx_error_count(rx_error_count), + .rx_error_bad_frame(rx_error_bad_frame), + .rx_error_bad_fcs(rx_error_bad_fcs), + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status), + .stat_tx_mcf(stat_tx_mcf), + .stat_rx_mcf(stat_rx_mcf), + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused), + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused), + + /* + * Configuration + */ + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable), + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable), + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable), + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en) +); + +endmodule + +`resetall