eth: Add 10G Ethernet combined MAC+PHY module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/eth/taxi_eth_mac_phy_10g_rx.sv

@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2019-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC/PHY combination
+ */
+module taxi_eth_mac_phy_10g_rx #
+(
+    parameter DATA_W = 64,
+    parameter HDR_W = (DATA_W/32),
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter logic BIT_REVERSE = 1'b0,
+    parameter logic SCRAMBLER_DISABLE = 1'b0,
+    parameter logic PRBS31_EN = 1'b0,
+    parameter SERDES_PIPELINE = 0,
+    parameter BITSLIP_HIGH_CYCLES = 0,
+    parameter BITSLIP_LOW_CYCLES = 7,
+    parameter COUNT_125US = 125000/6.4
+)
+(
+    input  wire logic                 clk,
+    input  wire logic                 rst,
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    taxi_axis_if.src                  m_axis_rx,
+
+    /*
+     * SERDES interface
+     */
+    input  wire logic [DATA_W-1:0]    serdes_rx_data,
+    input  wire logic [HDR_W-1:0]     serdes_rx_hdr,
+    output wire logic                 serdes_rx_bitslip,
+    output wire logic                 serdes_rx_reset_req,
+
+    /*
+     * PTP
+     */
+    input  wire logic [PTP_TS_W-1:0]  ptp_ts,
+
+    /*
+     * Status
+     */
+    output wire logic [1:0]           rx_start_packet,
+    output wire logic [6:0]           rx_error_count,
+    output wire logic                 rx_error_bad_frame,
+    output wire logic                 rx_error_bad_fcs,
+    output wire logic                 rx_bad_block,
+    output wire logic                 rx_sequence_error,
+    output wire logic                 rx_block_lock,
+    output wire logic                 rx_high_ber,
+    output wire logic                 rx_status,
+
+    /*
+     * Configuration
+     */
+    input  wire logic                 cfg_rx_enable,
+    input  wire logic                 cfg_rx_prbs31_enable
+);
+
+wire [DATA_W-1:0] encoded_rx_data;
+wire [HDR_W-1:0]  encoded_rx_hdr;
+
+taxi_eth_phy_10g_rx_if #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .BIT_REVERSE(BIT_REVERSE),
+    .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
+    .PRBS31_EN(PRBS31_EN),
+    .SERDES_PIPELINE(SERDES_PIPELINE),
+    .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+    .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+    .COUNT_125US(COUNT_125US)
+)
+eth_phy_10g_rx_if_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded interface
+     */
+    .encoded_rx_data(encoded_rx_data),
+    .encoded_rx_hdr(encoded_rx_hdr),
+
+    /*
+     * SERDES interface
+     */
+    .serdes_rx_data(serdes_rx_data),
+    .serdes_rx_hdr(serdes_rx_hdr),
+    .serdes_rx_bitslip(serdes_rx_bitslip),
+    .serdes_rx_reset_req(serdes_rx_reset_req),
+
+    /*
+     * Status
+     */
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error),
+    .rx_error_count(rx_error_count),
+    .rx_block_lock(rx_block_lock),
+    .rx_high_ber(rx_high_ber),
+    .rx_status(rx_status),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
+);
+
+taxi_axis_baser_rx_64 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W)
+)
+axis_baser_rx_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded input
+     */
+    .encoded_rx_data(encoded_rx_data),
+    .encoded_rx_hdr(encoded_rx_hdr),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_enable(cfg_rx_enable), 
+
+    /*
+     * Status
+     */
+    .start_packet(rx_start_packet),
+    .error_bad_frame(rx_error_bad_frame),
+    .error_bad_fcs(rx_error_bad_fcs),
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error)
+);
+
+endmodule
+
+`resetall