eth: Add 10G Ethernet combined MAC+PHY module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-09 08:58:40 -08:00 · 2025-02-08 21:40:50 -08:00
parent 0ddb89b18f
commit 2616e3f3e3
10 changed files with 2113 additions and 0 deletions
--- a/rtl/eth/taxi_eth_mac_phy_10g_tx.sv
+++ b/rtl/eth/taxi_eth_mac_phy_10g_tx.sv
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2019-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC/PHY combination
+ */
+module taxi_eth_mac_phy_10g_tx #
+(
+    parameter DATA_W = 64,
+    parameter HDR_W = (DATA_W/32),
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0,
+    parameter logic BIT_REVERSE = 1'b0,
+    parameter logic SCRAMBLER_DISABLE = 1'b0,
+    parameter logic PRBS31_EN = 1'b0,
+    parameter SERDES_PIPELINE = 0
+)
+(
+    input  wire logic                 clk,
+    input  wire logic                 rst,
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    taxi_axis_if.snk                  s_axis_tx,
+    taxi_axis_if.src                  m_axis_tx_cpl,
+
+    /*
+     * SERDES interface
+     */
+    output wire logic [DATA_W-1:0]    serdes_tx_data,
+    output wire logic [HDR_W-1:0]     serdes_tx_hdr,
+
+    /*
+     * PTP
+     */
+    input  wire logic [PTP_TS_W-1:0]  ptp_ts,
+
+    /*
+     * Status
+     */
+    output wire logic [1:0]           tx_start_packet,
+    output wire logic                 tx_error_underflow,
+
+    /*
+     * Configuration
+     */
+    input  wire logic [7:0]           cfg_ifg,
+    input  wire logic                 cfg_tx_enable,
+    input  wire logic                 cfg_tx_prbs31_enable
+);
+
+wire [DATA_W-1:0] encoded_tx_data;
+wire [HDR_W-1:0]  encoded_tx_hdr;
+
+taxi_axis_baser_tx_64 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+axis_baser_tx_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * 10GBASE-R encoded interface
+     */
+    .encoded_tx_data(encoded_tx_data),
+    .encoded_tx_hdr(encoded_tx_hdr),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(cfg_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .start_packet(tx_start_packet),
+    .error_underflow(tx_error_underflow)
+);
+
+taxi_eth_phy_10g_tx_if #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .BIT_REVERSE(BIT_REVERSE),
+    .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
+    .PRBS31_EN(PRBS31_EN),
+    .SERDES_PIPELINE(SERDES_PIPELINE)
+)
+eth_phy_10g_tx_if_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded interface
+     */
+    .encoded_tx_data(encoded_tx_data),
+    .encoded_tx_hdr(encoded_tx_hdr),
+
+    /*
+     * SERDES interface
+     */
+    .serdes_tx_data(serdes_tx_data),
+    .serdes_tx_hdr(serdes_tx_hdr),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
+);
+
+endmodule
+
+`resetall