diff --git a/example/KCU105/fpga/fpga.xdc b/example/KCU105/fpga/fpga.xdc index 12b6cdf..9965311 100644 --- a/example/KCU105/fpga/fpga.xdc +++ b/example/KCU105/fpga/fpga.xdc @@ -84,27 +84,27 @@ set_false_path -from [get_ports {sw[*]}] set_input_delay 0 [get_ports {sw[*]}] # PMOD0 -#set_property -dict {LOC AK25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] -#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] -#set_property -dict {LOC AH18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] -#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] -#set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] -#set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] -#set_property -dict {LOC AE21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] -#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] +#set_property -dict {LOC AK25 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J52.1 +#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J52.3 +#set_property -dict {LOC AH18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J52.5 +#set_property -dict {LOC AM19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J52.7 +#set_property -dict {LOC AE26 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J52.2 +#set_property -dict {LOC AF25 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J52.4 +#set_property -dict {LOC AE21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J52.6 +#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J52.8 #set_false_path -to [get_ports {pmod0[*]}] #set_output_delay 0 [get_ports {pmod0[*]}] # PMOD1 -#set_property -dict {LOC AL14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] -#set_property -dict {LOC AM14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] -#set_property -dict {LOC AP16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] -#set_property -dict {LOC AP15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] -#set_property -dict {LOC AM16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] -#set_property -dict {LOC AM15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] -#set_property -dict {LOC AN18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] -#set_property -dict {LOC AN17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] +#set_property -dict {LOC AL14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J53.1 +#set_property -dict {LOC AM14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J53.3 +#set_property -dict {LOC AP16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J53.5 +#set_property -dict {LOC AP15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J53.7 +#set_property -dict {LOC AM16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J53.2 +#set_property -dict {LOC AM15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J53.4 +#set_property -dict {LOC AN18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J53.6 +#set_property -dict {LOC AN17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J53.8 #set_false_path -to [get_ports {pmod1[*]}] #set_output_delay 0 [get_ports {pmod1[*]}] diff --git a/example/KR260/fpga/fpga.xdc b/example/KR260/fpga/fpga.xdc index 2d9cf54..b2f3603 100644 --- a/example/KR260/fpga/fpga.xdc +++ b/example/KR260/fpga/fpga.xdc @@ -32,53 +32,53 @@ set_false_path -to [get_ports {led[*] sfp_led[*]}] set_output_delay 0 [get_ports {led[*] sfp_led[*]}] # PMOD1 -#set_property -dict {LOC H12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J2.1 / HDA11 som240_1_a17 -#set_property -dict {LOC E10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J2.3 / HDA12 som240_1_d20 -#set_property -dict {LOC D10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J2.5 / HDA13 som240_1_d21 -#set_property -dict {LOC C11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J2.7 / HDA14 som240_1_d22 -#set_property -dict {LOC B10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J2.2 / HDA15 som240_1_b20 -#set_property -dict {LOC E12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J2.4 / HDA16_CC som240_1_b21 -#set_property -dict {LOC D11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J2.6 / HDA17 som240_1_b22 -#set_property -dict {LOC B11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J2.8 / HDA18 som240_1_c22 +#set_property -dict {LOC H12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J2.1 / HDA11 som240_1_a17 +#set_property -dict {LOC E10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J2.3 / HDA12 som240_1_d20 +#set_property -dict {LOC D10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J2.5 / HDA13 som240_1_d21 +#set_property -dict {LOC C11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J2.7 / HDA14 som240_1_d22 +#set_property -dict {LOC B10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J2.2 / HDA15 som240_1_b20 +#set_property -dict {LOC E12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J2.4 / HDA16_CC som240_1_b21 +#set_property -dict {LOC D11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J2.6 / HDA17 som240_1_b22 +#set_property -dict {LOC B11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J2.8 / HDA18 som240_1_c22 #set_false_path -to [get_ports {pmod1[*]}] #set_output_delay 0 [get_ports {pmod1[*]}] # PMOD2 -#set_property -dict {LOC J11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[0]}] ;# J18.1 / HDA02 som240_1_d18 -#set_property -dict {LOC J10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[1]}] ;# J18.3 / HDA03 som240_1_b16 -#set_property -dict {LOC K13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[2]}] ;# J18.5 / HDA04 som240_1_b17 -#set_property -dict {LOC K12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[3]}] ;# J18.7 / HDA05 som240_1_b18 -#set_property -dict {LOC H11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[4]}] ;# J18.2 / HDA06 som240_1_c18 -#set_property -dict {LOC G10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[5]}] ;# J18.4 / HDA07 som240_1_c19 -#set_property -dict {LOC F12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[6]}] ;# J18.6 / HDA08_CC som240_1_c20 -#set_property -dict {LOC F11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[7]}] ;# J18.8 / HDA09 som240_1_a15 +#set_property -dict {LOC J11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[0]}] ;# J18.1 / HDA02 som240_1_d18 +#set_property -dict {LOC J10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[1]}] ;# J18.3 / HDA03 som240_1_b16 +#set_property -dict {LOC K13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[2]}] ;# J18.5 / HDA04 som240_1_b17 +#set_property -dict {LOC K12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[3]}] ;# J18.7 / HDA05 som240_1_b18 +#set_property -dict {LOC H11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[4]}] ;# J18.2 / HDA06 som240_1_c18 +#set_property -dict {LOC G10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[5]}] ;# J18.4 / HDA07 som240_1_c19 +#set_property -dict {LOC F12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[6]}] ;# J18.6 / HDA08_CC som240_1_c20 +#set_property -dict {LOC F11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod2[7]}] ;# J18.8 / HDA09 som240_1_a15 #set_false_path -to [get_ports {pmod2[*]}] #set_output_delay 0 [get_ports {pmod2[*]}] # PMOD3 -#set_property -dict {LOC AE12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[0]}] ;# J19.1 / HDB00_CC som240_2_d44 -#set_property -dict {LOC AF12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[1]}] ;# J19.3 / HDB01 som240_2_d45 -#set_property -dict {LOC AG10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[2]}] ;# J19.5 / HDB02 som240_2_d46 -#set_property -dict {LOC AH10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[3]}] ;# J19.7 / HDB03 som240_2_d48 -#set_property -dict {LOC AF11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[4]}] ;# J19.2 / HDB04 som240_2_d49 -#set_property -dict {LOC AG11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[5]}] ;# J19.4 / HDB05 som240_2_d50 -#set_property -dict {LOC AH12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[6]}] ;# J19.6 / HDB06 som240_2_c46 -#set_property -dict {LOC AH11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[7]}] ;# J19.8 / HDB07 som240_2_c47 +#set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[0]}] ;# J19.1 / HDB00_CC som240_2_d44 +#set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[1]}] ;# J19.3 / HDB01 som240_2_d45 +#set_property -dict {LOC AG10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[2]}] ;# J19.5 / HDB02 som240_2_d46 +#set_property -dict {LOC AH10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[3]}] ;# J19.7 / HDB03 som240_2_d48 +#set_property -dict {LOC AF11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[4]}] ;# J19.2 / HDB04 som240_2_d49 +#set_property -dict {LOC AG11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[5]}] ;# J19.4 / HDB05 som240_2_d50 +#set_property -dict {LOC AH12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[6]}] ;# J19.6 / HDB06 som240_2_c46 +#set_property -dict {LOC AH11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod3[7]}] ;# J19.8 / HDB07 som240_2_c47 #set_false_path -to [get_ports {pmod3[*]}] #set_output_delay 0 [get_ports {pmod3[*]}] # PMOD4 -#set_property -dict {LOC AC12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[0]}] ;# J20.1 / HDB08_CC som240_2_c48 -#set_property -dict {LOC AD12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[1]}] ;# J20.3 / HDB09 som240_2_c50 -#set_property -dict {LOC AE10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[2]}] ;# J20.5 / HDB10 som240_2_c51 -#set_property -dict {LOC AF10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[3]}] ;# J20.7 / HDB11 som240_2_c52 -#set_property -dict {LOC AD11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[4]}] ;# J20.2 / HDB12 som240_2_b44 -#set_property -dict {LOC AD10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[5]}] ;# J20.4 / HDB13 som240_2_b45 -#set_property -dict {LOC AA11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[6]}] ;# J20.6 / HDB14 som240_2_b46 -#set_property -dict {LOC AA10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[7]}] ;# J20.8 / HDB15 som240_2_b48 +#set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[0]}] ;# J20.1 / HDB08_CC som240_2_c48 +#set_property -dict {LOC AD12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[1]}] ;# J20.3 / HDB09 som240_2_c50 +#set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[2]}] ;# J20.5 / HDB10 som240_2_c51 +#set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[3]}] ;# J20.7 / HDB11 som240_2_c52 +#set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[4]}] ;# J20.2 / HDB12 som240_2_b44 +#set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[5]}] ;# J20.4 / HDB13 som240_2_b45 +#set_property -dict {LOC AA11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[6]}] ;# J20.6 / HDB14 som240_2_b46 +#set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod4[7]}] ;# J20.8 / HDB15 som240_2_b48 #set_false_path -to [get_ports {pmod4[*]}] #set_output_delay 0 [get_ports {pmod4[*]}] diff --git a/example/VCU108/fpga/fpga.xdc b/example/VCU108/fpga/fpga.xdc index fa13b6d..40c31bb 100644 --- a/example/VCU108/fpga/fpga.xdc +++ b/example/VCU108/fpga/fpga.xdc @@ -81,27 +81,27 @@ set_false_path -from [get_ports {sw[*]}] set_input_delay 0 [get_ports {sw[*]}] # PMOD0 -#set_property -dict {LOC BC14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] -#set_property -dict {LOC BA10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] -#set_property -dict {LOC AW16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] -#set_property -dict {LOC BB16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] -#set_property -dict {LOC BC13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] -#set_property -dict {LOC BF7 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] -#set_property -dict {LOC AW12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] -#set_property -dict {LOC BC16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] +#set_property -dict {LOC BC14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J52.1 +#set_property -dict {LOC BA10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J52.3 +#set_property -dict {LOC AW16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J52.5 +#set_property -dict {LOC BB16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J52.7 +#set_property -dict {LOC BC13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J52.2 +#set_property -dict {LOC BF7 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J52.4 +#set_property -dict {LOC AW12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J52.6 +#set_property -dict {LOC BC16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J52.8 #set_false_path -to [get_ports {pmod0[*]}] #set_output_delay 0 [get_ports {pmod0[*]}] # PMOD1 -#set_property -dict {LOC P22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] -#set_property -dict {LOC N22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] -#set_property -dict {LOC J20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] -#set_property -dict {LOC K24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] -#set_property -dict {LOC J24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] -#set_property -dict {LOC T23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] -#set_property -dict {LOC R23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] -#set_property -dict {LOC R22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] +#set_property -dict {LOC P22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J53.1 +#set_property -dict {LOC N22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J53.3 +#set_property -dict {LOC J20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J53.5 +#set_property -dict {LOC K24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J53.7 +#set_property -dict {LOC J24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J53.2 +#set_property -dict {LOC T23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J53.4 +#set_property -dict {LOC R23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J53.6 +#set_property -dict {LOC R22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J53.8 #set_false_path -to [get_ports {pmod1[*]}] #set_output_delay 0 [get_ports {pmod1[*]}] diff --git a/example/ZCU102/fpga/fpga.xdc b/example/ZCU102/fpga/fpga.xdc index bde4985..dba7c72 100644 --- a/example/ZCU102/fpga/fpga.xdc +++ b/example/ZCU102/fpga/fpga.xdc @@ -60,6 +60,47 @@ set_property -dict {LOC AK13 IOSTANDARD LVCMOS33} [get_ports {sw[7]}] set_false_path -from [get_ports {sw[*]}] set_input_delay 0 [get_ports {sw[*]}] +# PMOD0 +#set_property -dict {LOC A20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J55.1 +#set_property -dict {LOC B20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J55.3 +#set_property -dict {LOC A22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J55.5 +#set_property -dict {LOC A21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J55.7 +#set_property -dict {LOC B21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J55.2 +#set_property -dict {LOC C21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J55.4 +#set_property -dict {LOC C22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J55.6 +#set_property -dict {LOC D21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J55.8 + +#set_false_path -to [get_ports {pmod0[*]}] +#set_output_delay 0 [get_ports {pmod0[*]}] + +# PMOD1 +#set_property -dict {LOC D20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J87.1 +#set_property -dict {LOC E20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J87.3 +#set_property -dict {LOC D22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J87.5 +#set_property -dict {LOC E22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J87.7 +#set_property -dict {LOC F20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J87.2 +#set_property -dict {LOC G20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J87.4 +#set_property -dict {LOC J20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J87.6 +#set_property -dict {LOC J19 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J87.8 + +#set_false_path -to [get_ports {pmod1[*]}] +#set_output_delay 0 [get_ports {pmod1[*]}] + +# "Prototype header" GPIO +#set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[0]}] ;# J3.6 +#set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[1]}] ;# J3.8 +#set_property -dict {LOC G14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[2]}] ;# J3.10 +#set_property -dict {LOC G15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[3]}] ;# J3.12 +#set_property -dict {LOC J15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[4]}] ;# J3.14 +#set_property -dict {LOC J16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[5]}] ;# J3.16 +#set_property -dict {LOC G16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[6]}] ;# J3.18 +#set_property -dict {LOC H16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[7]}] ;# J3.20 +#set_property -dict {LOC G13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[8]}] ;# J3.22 +#set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[9]}] ;# J3.24 + +#set_false_path -to [get_ports {proto_gpio[*]}] +#set_output_delay 0 [get_ports {proto_gpio[*]}] + # UART set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd] set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd] diff --git a/example/ZCU106/fpga/fpga.xdc b/example/ZCU106/fpga/fpga.xdc index b117f03..2adfb35 100644 --- a/example/ZCU106/fpga/fpga.xdc +++ b/example/ZCU106/fpga/fpga.xdc @@ -60,6 +60,47 @@ set_property -dict {LOC B13 IOSTANDARD LVCMOS18} [get_ports {sw[7]}] set_false_path -from [get_ports {sw[*]}] set_input_delay 0 [get_ports {sw[*]}] +# PMOD0 +#set_property -dict {LOC B23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J55.1 +#set_property -dict {LOC A23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J55.3 +#set_property -dict {LOC F25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J55.5 +#set_property -dict {LOC E20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J55.7 +#set_property -dict {LOC K24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J55.2 +#set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J55.4 +#set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J55.6 +#set_property -dict {LOC D7 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J55.8 + +#set_false_path -to [get_ports {pmod0[*]}] +#set_output_delay 0 [get_ports {pmod0[*]}] + +# PMOD1 +#set_property -dict {LOC AN8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J87.1 +#set_property -dict {LOC AN9 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J87.3 +#set_property -dict {LOC AP11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J87.5 +#set_property -dict {LOC AN11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J87.7 +#set_property -dict {LOC AP9 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J87.2 +#set_property -dict {LOC AP10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J87.4 +#set_property -dict {LOC AP12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J87.6 +#set_property -dict {LOC AN12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J87.8 + +#set_false_path -to [get_ports {pmod1[*]}] +#set_output_delay 0 [get_ports {pmod1[*]}] + +# "Prototype header" GPIO +#set_property -dict {LOC K13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[0]}] ;# J3.6 +#set_property -dict {LOC L14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[1]}] ;# J3.8 +#set_property -dict {LOC J14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[2]}] ;# J3.10 +#set_property -dict {LOC K14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[3]}] ;# J3.12 +#set_property -dict {LOC J11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[4]}] ;# J3.14 +#set_property -dict {LOC K12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[5]}] ;# J3.16 +#set_property -dict {LOC L11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[6]}] ;# J3.18 +#set_property -dict {LOC L12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[7]}] ;# J3.20 +#set_property -dict {LOC G24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[8]}] ;# J3.22 +#set_property -dict {LOC G23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {proto_gpio[9]}] ;# J3.24 + +#set_false_path -to [get_ports {proto_gpio[*]}] +#set_output_delay 0 [get_ports {proto_gpio[*]}] + # UART set_property -dict {LOC AL17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] set_property -dict {LOC AH17 IOSTANDARD LVCMOS12} [get_ports uart_rxd]