diff --git a/example/Arty/fpga/README.md b/example/Arty/fpga/README.md
index b05e68c..160547b 100644
--- a/example/Arty/fpga/README.md
+++ b/example/Arty/fpga/README.md
@@ -7,7 +7,7 @@ This example design targets the Digilent Arty A7 FPGA board.
 The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
 
 *  USB UART
-    *  XFCP
+    *  XFCP (3 Mbaud)
 *  RJ-45 Ethernet port with TI DP83848J PHY
     *  Looped-back MAC via MII
 
@@ -32,6 +32,4 @@ Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensu
 
 Run `make program` to program the board with Vivado.
 
-To test the looped-back UART, use any serial terminal software like minicom, screen, etc.  The looped-back UART will echo typed text back without modification.
-
 To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
diff --git a/example/Arty/fpga/rtl/fpga_core.sv b/example/Arty/fpga/rtl/fpga_core.sv
index 229570e..81d07b4 100644
--- a/example/Arty/fpga/rtl/fpga_core.sv
+++ b/example/Arty/fpga/rtl/fpga_core.sv
@@ -78,6 +78,7 @@ module fpga_core #
 assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = {sw, btn};
 assign phy_reset_n = !rst;
 
+// XFCP
 taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
 
 taxi_xfcp_if_uart #(
diff --git a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
index 9777723..34a456d 100644
--- a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
@@ -35,8 +35,8 @@ class TB:
         self.mii_phy = MiiPhy(dut.phy_txd, None, dut.phy_tx_en, dut.phy_tx_clk,
             dut.phy_rxd, dut.phy_rx_er, dut.phy_rx_dv, dut.phy_rx_clk, speed=speed)
 
-        self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1)
-        self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1)
+        self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
+        self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
 
         dut.phy_crs.setimmediatevalue(0)
         dut.phy_col.setimmediatevalue(0)