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example/Arty: Arty example design clean-up

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-04-09 19:12:57 -07:00
parent d355956b68
commit 28fd0f8cba
3 changed files with 4 additions and 5 deletions
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example/Arty/fpga/rtl/fpga_core.sv
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@@ -78,6 +78,7 @@ module fpga_core #
assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = {sw, btn};
assign phy_reset_n = !rst;
// XFCP
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
taxi_xfcp_if_uart #(