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eth: Add Ethernet example design for Napatech NT200A01/NT200A02
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
52
src/eth/example/NT200A02/fpga/README.md
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52
src/eth/example/NT200A02/fpga/README.md
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# Taxi Example Design for NT200A01/NT200A02
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## Introduction
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This example design targets the Napatech NT200A01/NT200A02 FPGA board.
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The design places looped-back MACs on the QSFP28 ports.
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* QSFP28
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* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA
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* NT200A01: xcvu095-ffva2104-2-e
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* NT200A02: xcvu5p-flva2104-2-e
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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## JTAG pinout
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Napatech boards use a non-standard connector for JTAG. There are three debug connectors, and one of them carries the JTAG signals for the FPGA.
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J16 J22
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FPGA AVR
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TDI 7 8 GND TDI 7 8 GND
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TMS 5 6 HALT TMS 5 6
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TDO 3 4 Vref TDO 3 4 Vref
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TCK 1 2 GND TCK 1 2 GND
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J17
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GND 2 1
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4 3
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6 5
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Note: J18.6 HALT must be driven low to access the JTAG chain. So, either tie to to ground, or connect it to the HALT signal on DLC9/DLC10 cables.
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153
src/eth/example/NT200A02/fpga/common/vivado.mk
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153
src/eth/example/NT200A02/fpga/common/vivado.mk
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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157
src/eth/example/NT200A02/fpga/fpga_NT200A01/Makefile
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157
src/eth/example/NT200A02/fpga/fpga_NT200A01/Makefile
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xcvu095-ffva2104-2-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexu
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RTL_DIR = ../rtl
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LIB_DIR = ../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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# Files for synthesis
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SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
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SYN_FILES += $(RTL_DIR)/fpga_core.sv
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SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
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SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
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SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
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SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
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SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
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# XDC files
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XDC_FILES = ../fpga_nt200a01.xdc
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XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
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# IP
|
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IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
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# Configuration
|
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CONFIG_TCL_FILES = config.tcl
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|
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|
include ../common/vivado.mk
|
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|
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%_fallback.bit: %.bit
|
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echo "open_project $*.xpr" > generate_fallback_bit.tcl
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echo "open_run impl_1" >> generate_fallback_bit.tcl
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echo "startgroup" >> generate_fallback_bit.tcl
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echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
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echo "endgroup" >> generate_fallback_bit.tcl
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echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
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echo "undo" >> generate_fallback_bit.tcl
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echo "exit" >> generate_fallback_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
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|
do COUNT=$$((COUNT+1)); done; \
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|
COUNT=$$((COUNT-1)); \
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cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
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||||||
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|
||||||
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program: $(FPGA_TOP).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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||||||
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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||||||
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||||||
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%.mcs %.prm: %.bit
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||||||
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echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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||||||
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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||||||
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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||||||
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COUNT=$$((COUNT-1)); \
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||||||
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for x in .mcs .prm; \
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||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
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||||||
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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||||||
|
|
||||||
|
%_fallback.mcs %_fallback.prm: %_fallback.bit
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||||||
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echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
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||||||
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echo "exit" >> generate_fallback_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
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||||||
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mkdir -p rev
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||||||
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COUNT=100; \
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||||||
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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||||||
|
do COUNT=$$((COUNT+1)); done; \
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||||||
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COUNT=$$((COUNT-1)); \
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||||||
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for x in .mcs .prm; \
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||||||
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do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
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||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
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%_full.mcs %_full.prm: %_fallback.bit %.bit
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||||||
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echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||||
|
echo "exit" >> generate_full_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
|
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||||
|
echo "open_hw_manager" > flash$*.tcl
|
||||||
|
echo "connect_hw_server" >> flash$*.tcl
|
||||||
|
echo "open_hw_target" >> flash$*.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "exit" >> flash$*.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||||
22
src/eth/example/NT200A02/fpga/fpga_NT200A01/config.tcl
Normal file
22
src/eth/example/NT200A02/fpga/fpga_NT200A01/config.tcl
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# 10G MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "64"
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
157
src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/Makefile
Normal file
157
src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/Makefile
Normal file
@@ -0,0 +1,157 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu095-ffva2104-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexu
|
||||||
|
|
||||||
|
RTL_DIR = ../rtl
|
||||||
|
LIB_DIR = ../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga_nt200a01.xdc
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
|
||||||
|
|
||||||
|
# Configuration
|
||||||
|
CONFIG_TCL_FILES = config.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
%_fallback.bit: %.bit
|
||||||
|
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||||
|
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||||
|
echo "startgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||||
|
echo "endgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||||
|
echo "undo" >> generate_fallback_bit.tcl
|
||||||
|
echo "exit" >> generate_fallback_bit.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
EXT=bit; COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||||
|
|
||||||
|
program: $(FPGA_TOP).bit
|
||||||
|
echo "open_hw_manager" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
%.mcs %.prm: %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||||
|
echo "exit" >> generate_fallback_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||||
|
echo "exit" >> generate_full_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
|
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||||
|
echo "open_hw_manager" > flash$*.tcl
|
||||||
|
echo "connect_hw_server" >> flash$*.tcl
|
||||||
|
echo "open_hw_target" >> flash$*.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "exit" >> flash$*.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||||
22
src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/config.tcl
Normal file
22
src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/config.tcl
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# 10G MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "32"
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
157
src/eth/example/NT200A02/fpga/fpga_NT200A02/Makefile
Normal file
157
src/eth/example/NT200A02/fpga/fpga_NT200A02/Makefile
Normal file
@@ -0,0 +1,157 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu5p-flva2104-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexuplus
|
||||||
|
|
||||||
|
RTL_DIR = ../rtl
|
||||||
|
LIB_DIR = ../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga_nt200a02.xdc
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
|
||||||
|
|
||||||
|
# Configuration
|
||||||
|
CONFIG_TCL_FILES = config.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
%_fallback.bit: %.bit
|
||||||
|
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||||
|
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||||
|
echo "startgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||||
|
echo "endgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||||
|
echo "undo" >> generate_fallback_bit.tcl
|
||||||
|
echo "exit" >> generate_fallback_bit.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
EXT=bit; COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||||
|
|
||||||
|
program: $(FPGA_TOP).bit
|
||||||
|
echo "open_hw_manager" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
%.mcs %.prm: %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||||
|
echo "exit" >> generate_fallback_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||||
|
echo "exit" >> generate_full_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
|
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||||
|
echo "open_hw_manager" > flash$*.tcl
|
||||||
|
echo "connect_hw_server" >> flash$*.tcl
|
||||||
|
echo "open_hw_target" >> flash$*.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "exit" >> flash$*.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||||
22
src/eth/example/NT200A02/fpga/fpga_NT200A02/config.tcl
Normal file
22
src/eth/example/NT200A02/fpga/fpga_NT200A02/config.tcl
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# 10G MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "64"
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
157
src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/Makefile
Normal file
157
src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/Makefile
Normal file
@@ -0,0 +1,157 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu5p-flva2104-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexuplus
|
||||||
|
|
||||||
|
RTL_DIR = ../rtl
|
||||||
|
LIB_DIR = ../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga_nt200a02.xdc
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
|
||||||
|
|
||||||
|
# Configuration
|
||||||
|
CONFIG_TCL_FILES = config.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
%_fallback.bit: %.bit
|
||||||
|
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||||
|
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||||
|
echo "startgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||||
|
echo "endgroup" >> generate_fallback_bit.tcl
|
||||||
|
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||||
|
echo "undo" >> generate_fallback_bit.tcl
|
||||||
|
echo "exit" >> generate_fallback_bit.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
EXT=bit; COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||||
|
|
||||||
|
program: $(FPGA_TOP).bit
|
||||||
|
echo "open_hw_manager" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
%.mcs %.prm: %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||||
|
echo "exit" >> generate_fallback_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||||
|
echo "exit" >> generate_full_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
|
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||||
|
echo "open_hw_manager" > flash$*.tcl
|
||||||
|
echo "connect_hw_server" >> flash$*.tcl
|
||||||
|
echo "open_hw_target" >> flash$*.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||||
|
echo "exit" >> flash$*.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||||
22
src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/config.tcl
Normal file
22
src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/config.tcl
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# 10G MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "32"
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
262
src/eth/example/NT200A02/fpga/fpga_nt200a01.xdc
Normal file
262
src/eth/example/NT200A02/fpga/fpga_nt200a01.xdc
Normal file
@@ -0,0 +1,262 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# XDC constraints for the Napatech NT200A01 board
|
||||||
|
# part: xcvu095-ffva2104-2-e
|
||||||
|
|
||||||
|
# General configuration
|
||||||
|
set_property CFGBVS GND [current_design]
|
||||||
|
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||||
|
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||||
|
|
||||||
|
# System clocks
|
||||||
|
# 50 MHz system clock
|
||||||
|
set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
|
||||||
|
create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
|
||||||
|
|
||||||
|
# 80 MHz EMCCLK
|
||||||
|
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
|
||||||
|
#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
|
||||||
|
|
||||||
|
# 20 MHz reference clock
|
||||||
|
#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
|
||||||
|
#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
|
||||||
|
#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
|
||||||
|
#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC B10 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
|
||||||
|
#set_property -dict {LOC C10 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
|
||||||
|
|
||||||
|
# LEDs
|
||||||
|
set_property -dict {LOC R26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
|
||||||
|
set_property -dict {LOC M28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
|
||||||
|
set_property -dict {LOC R27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
|
||||||
|
set_property -dict {LOC T24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
|
||||||
|
set_property -dict {LOC J27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
|
||||||
|
set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
|
||||||
|
set_property -dict {LOC L25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
|
||||||
|
set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
|
||||||
|
set_property -dict {LOC B28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
|
||||||
|
set_property -dict {LOC C27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
|
||||||
|
set_property -dict {LOC J25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
|
||||||
|
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
|
||||||
|
set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
|
||||||
|
set_property -dict {LOC D27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
|
||||||
|
set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
|
||||||
|
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
|
||||||
|
set_property -dict {LOC M15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
|
||||||
|
set_property -dict {LOC M13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
|
||||||
|
set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
|
||||||
|
|
||||||
|
# Si5340 U18
|
||||||
|
set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
|
||||||
|
set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
|
||||||
|
set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
|
||||||
|
set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
|
||||||
|
|
||||||
|
# Gigabit PHY (DP83867)
|
||||||
|
#set_property -dict {LOC P12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
|
||||||
|
#set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
|
||||||
|
#set_property -dict {LOC R11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
|
||||||
|
#set_property -dict {LOC R12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
|
||||||
|
#set_property -dict {LOC P11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
|
||||||
|
#set_property -dict {LOC N12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
|
||||||
|
#set_property -dict {LOC U13 IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
|
||||||
|
#set_property -dict {LOC U16 IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
|
||||||
|
#set_property -dict {LOC T11 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
|
||||||
|
#set_property -dict {LOC U11 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
|
||||||
|
#set_property -dict {LOC R13 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
|
||||||
|
#set_property -dict {LOC V15 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
|
||||||
|
#set_property -dict {LOC J11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
|
||||||
|
#set_property -dict {LOC T14 IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
|
||||||
|
#set_property -dict {LOC M11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
|
||||||
|
#set_property -dict {LOC V16 IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
|
||||||
|
#set_property -dict {LOC U12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
|
||||||
|
#set_property -dict {LOC J12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
|
||||||
|
#set_property -dict {LOC L14 IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
|
||||||
|
#set_property -dict {LOC M12 IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
|
||||||
|
#set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
|
||||||
|
#set_property -dict {LOC W14 IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
|
||||||
|
#set_property -dict {LOC K14 IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
|
||||||
|
|
||||||
|
# QSFP28 Interfaces
|
||||||
|
set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_129 from Si5340 U23 OUT1
|
||||||
|
set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_129 from Si5340 U23 OUT1
|
||||||
|
set_property -dict {LOC A26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
|
||||||
|
set_property -dict {LOC C25 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
|
||||||
|
set_property -dict {LOC B26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
|
||||||
|
set_property -dict {LOC G25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
|
||||||
|
set_property -dict {LOC B25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
|
||||||
|
set_property -dict {LOC F25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
|
||||||
|
|
||||||
|
# 322.265625 MHz MGT reference clock
|
||||||
|
create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
|
||||||
|
set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_130 from Si5340 U23 OUT2
|
||||||
|
set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_130 from Si5340 U23 OUT2
|
||||||
|
set_property -dict {LOC B27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||||
|
set_property -dict {LOC H28 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
|
||||||
|
set_property -dict {LOC N24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
|
||||||
|
set_property -dict {LOC H25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
|
||||||
|
set_property -dict {LOC P27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
|
||||||
|
set_property -dict {LOC R24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
|
||||||
|
|
||||||
|
# 322.265625 MHz MGT reference clock
|
||||||
|
create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
|
||||||
|
# PCIe Interface
|
||||||
|
#set_property -dict {LOC U4 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC U3 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC M7 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC M6 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC V2 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC P7 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC P6 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC W4 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC W3 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC T7 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC T6 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC V7 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC V6 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
|
||||||
|
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
#set_property -dict {LOC AR9 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_224
|
||||||
|
#set_property -dict {LOC AR8 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_224
|
||||||
|
#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
|
||||||
|
#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
|
||||||
|
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||||
|
|
||||||
|
# 100 MHz MGT reference clock
|
||||||
|
#create_clock -period 10.000 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||||
|
#create_clock -period 10.000 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||||
|
|
||||||
|
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||||
|
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||||
259
src/eth/example/NT200A02/fpga/fpga_nt200a02.xdc
Normal file
259
src/eth/example/NT200A02/fpga/fpga_nt200a02.xdc
Normal file
@@ -0,0 +1,259 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# XDC constraints for the Napatech NT200A02 board
|
||||||
|
# part: xcvu5p-flva2104-2-e
|
||||||
|
|
||||||
|
# General configuration
|
||||||
|
set_property CFGBVS GND [current_design]
|
||||||
|
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||||
|
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||||
|
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||||
|
|
||||||
|
# System clocks
|
||||||
|
# 50 MHz system clock
|
||||||
|
set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
|
||||||
|
create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
|
||||||
|
|
||||||
|
# 80 MHz EMCCLK
|
||||||
|
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
|
||||||
|
#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
|
||||||
|
|
||||||
|
# 20 MHz reference clock
|
||||||
|
#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
|
||||||
|
#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
|
||||||
|
#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
|
||||||
|
#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
|
||||||
|
|
||||||
|
# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
|
||||||
|
#set_property -dict {LOC B10 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
|
||||||
|
#set_property -dict {LOC C10 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
|
||||||
|
#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
|
||||||
|
|
||||||
|
# LEDs
|
||||||
|
set_property -dict {LOC R26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
|
||||||
|
set_property -dict {LOC M28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
|
||||||
|
set_property -dict {LOC R27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
|
||||||
|
set_property -dict {LOC T24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
|
||||||
|
set_property -dict {LOC J27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
|
||||||
|
set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
|
||||||
|
set_property -dict {LOC L25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
|
||||||
|
set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
|
||||||
|
set_property -dict {LOC B28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
|
||||||
|
set_property -dict {LOC C27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
|
||||||
|
set_property -dict {LOC J25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
|
||||||
|
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
|
||||||
|
set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
|
||||||
|
set_property -dict {LOC D27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
|
||||||
|
set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
|
||||||
|
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
|
||||||
|
set_property -dict {LOC M15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
|
||||||
|
set_property -dict {LOC M13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
|
||||||
|
set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
|
||||||
|
|
||||||
|
# Si5340 U18
|
||||||
|
set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
|
||||||
|
set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
|
||||||
|
set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
|
||||||
|
set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
|
||||||
|
|
||||||
|
# Gigabit PHY (DP83867)
|
||||||
|
#set_property -dict {LOC P12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
|
||||||
|
#set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
|
||||||
|
#set_property -dict {LOC R11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
|
||||||
|
#set_property -dict {LOC R12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
|
||||||
|
#set_property -dict {LOC P11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
|
||||||
|
#set_property -dict {LOC N12 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
|
||||||
|
#set_property -dict {LOC U13 IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
|
||||||
|
#set_property -dict {LOC U16 IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
|
||||||
|
#set_property -dict {LOC T11 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
|
||||||
|
#set_property -dict {LOC U11 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
|
||||||
|
#set_property -dict {LOC R13 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
|
||||||
|
#set_property -dict {LOC V15 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
|
||||||
|
#set_property -dict {LOC J11 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
|
||||||
|
#set_property -dict {LOC T14 IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
|
||||||
|
#set_property -dict {LOC M11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
|
||||||
|
#set_property -dict {LOC V16 IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
|
||||||
|
#set_property -dict {LOC U12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
|
||||||
|
#set_property -dict {LOC J12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
|
||||||
|
#set_property -dict {LOC L14 IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
|
||||||
|
#set_property -dict {LOC M12 IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
|
||||||
|
#set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
|
||||||
|
#set_property -dict {LOC W14 IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
|
||||||
|
#set_property -dict {LOC K14 IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
|
||||||
|
|
||||||
|
# QSFP28 Interfaces
|
||||||
|
set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||||
|
set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_131 from Si5340 U23 OUT1
|
||||||
|
set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_131 from Si5340 U23 OUT1
|
||||||
|
set_property -dict {LOC A26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
|
||||||
|
set_property -dict {LOC C25 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
|
||||||
|
set_property -dict {LOC B26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
|
||||||
|
set_property -dict {LOC G25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
|
||||||
|
set_property -dict {LOC B25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
|
||||||
|
set_property -dict {LOC F25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
|
||||||
|
|
||||||
|
# 322.265625 MHz MGT reference clock
|
||||||
|
create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||||
|
|
||||||
|
set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||||
|
set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_132 from Si5340 U23 OUT2
|
||||||
|
set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_132 from Si5340 U23 OUT2
|
||||||
|
set_property -dict {LOC B27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||||
|
set_property -dict {LOC H28 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
|
||||||
|
set_property -dict {LOC N24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
|
||||||
|
set_property -dict {LOC H25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
|
||||||
|
set_property -dict {LOC P27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
|
||||||
|
set_property -dict {LOC R24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
|
||||||
|
|
||||||
|
# 322.265625 MHz MGT reference clock
|
||||||
|
create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||||
|
|
||||||
|
# PCIe Interface
|
||||||
|
#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||||
|
#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||||
|
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||||
|
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||||
|
#set_property -dict {LOC AA9 } [get_ports pcie_refclk_p] ;# MGTREFCLK1P_227
|
||||||
|
#set_property -dict {LOC AA8 } [get_ports pcie_refclk_n] ;# MGTREFCLK1N_227
|
||||||
|
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||||
|
|
||||||
|
# 100 MHz MGT reference clock
|
||||||
|
#create_clock -period 10.000 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||||
|
|
||||||
|
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||||
|
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||||
1
src/eth/example/NT200A02/fpga/lib/taxi
Symbolic link
1
src/eth/example/NT200A02/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../../../../../
|
||||||
BIN
src/eth/example/NT200A02/fpga/pll/Si5340-RevD-NT200-Project.slabtimeproj
Executable file
BIN
src/eth/example/NT200A02/fpga/pll/Si5340-RevD-NT200-Project.slabtimeproj
Executable file
Binary file not shown.
351
src/eth/example/NT200A02/fpga/pll/Si5340-RevD-NT200-Registers.txt
Executable file
351
src/eth/example/NT200A02/fpga/pll/Si5340-RevD-NT200-Registers.txt
Executable file
@@ -0,0 +1,351 @@
|
|||||||
|
# Si534x/7x/8x/9x Registers Script
|
||||||
|
#
|
||||||
|
# Part: Si5340
|
||||||
|
# Project File: X:\Projects\taxi-corundum\src\eth\example\NT200A02\fpga\pll\Si5340-RevD-NT200-Project.slabtimeproj
|
||||||
|
# Design ID: NT200
|
||||||
|
# Includes Pre/Post Download Control Register Writes: Yes
|
||||||
|
# Die Revision: B1
|
||||||
|
# Creator: ClockBuilder Pro v4.1 [2021-09-22]
|
||||||
|
# Created On: 2026-04-04 21:47:23 GMT-07:00
|
||||||
|
Address,Data
|
||||||
|
#
|
||||||
|
# Start configuration preamble
|
||||||
|
0x0B24,0xC0
|
||||||
|
0x0B25,0x00
|
||||||
|
# Rev D stuck divider fix
|
||||||
|
0x0502,0x01
|
||||||
|
0x0505,0x03
|
||||||
|
0x0957,0x17
|
||||||
|
0x0B4E,0x1A
|
||||||
|
# End configuration preamble
|
||||||
|
#
|
||||||
|
# Delay 300 msec
|
||||||
|
# Delay is worst case time for device to complete any calibration
|
||||||
|
# that is running due to device state change previous to this script
|
||||||
|
# being processed.
|
||||||
|
#
|
||||||
|
# Start configuration registers
|
||||||
|
0x0006,0x00
|
||||||
|
0x0007,0x00
|
||||||
|
0x0008,0x00
|
||||||
|
0x000B,0x74
|
||||||
|
0x0017,0xD0
|
||||||
|
0x0018,0xFF
|
||||||
|
0x0021,0x0F
|
||||||
|
0x0022,0x00
|
||||||
|
0x002B,0x02
|
||||||
|
0x002C,0x20
|
||||||
|
0x002D,0x00
|
||||||
|
0x002E,0x00
|
||||||
|
0x002F,0x00
|
||||||
|
0x0030,0x00
|
||||||
|
0x0031,0x00
|
||||||
|
0x0032,0x00
|
||||||
|
0x0033,0x00
|
||||||
|
0x0034,0x00
|
||||||
|
0x0035,0x00
|
||||||
|
0x0036,0x00
|
||||||
|
0x0037,0x00
|
||||||
|
0x0038,0x00
|
||||||
|
0x0039,0x00
|
||||||
|
0x003A,0x00
|
||||||
|
0x003B,0x00
|
||||||
|
0x003C,0x00
|
||||||
|
0x003D,0x00
|
||||||
|
0x0041,0x00
|
||||||
|
0x0042,0x00
|
||||||
|
0x0043,0x00
|
||||||
|
0x0044,0x00
|
||||||
|
0x009E,0x00
|
||||||
|
0x0102,0x01
|
||||||
|
0x0112,0x06
|
||||||
|
0x0113,0x09
|
||||||
|
0x0114,0x3B
|
||||||
|
0x0115,0x28
|
||||||
|
0x0117,0x06
|
||||||
|
0x0118,0x09
|
||||||
|
0x0119,0x3B
|
||||||
|
0x011A,0x29
|
||||||
|
0x0126,0x06
|
||||||
|
0x0127,0x09
|
||||||
|
0x0128,0x3B
|
||||||
|
0x0129,0x29
|
||||||
|
0x012B,0x06
|
||||||
|
0x012C,0x09
|
||||||
|
0x012D,0x3B
|
||||||
|
0x012E,0x29
|
||||||
|
0x013F,0x00
|
||||||
|
0x0140,0x00
|
||||||
|
0x0141,0x40
|
||||||
|
0x0206,0x00
|
||||||
|
0x0208,0x00
|
||||||
|
0x0209,0x00
|
||||||
|
0x020A,0x00
|
||||||
|
0x020B,0x00
|
||||||
|
0x020C,0x00
|
||||||
|
0x020D,0x00
|
||||||
|
0x020E,0x00
|
||||||
|
0x020F,0x00
|
||||||
|
0x0210,0x00
|
||||||
|
0x0211,0x00
|
||||||
|
0x0212,0x00
|
||||||
|
0x0213,0x00
|
||||||
|
0x0214,0x00
|
||||||
|
0x0215,0x00
|
||||||
|
0x0216,0x00
|
||||||
|
0x0217,0x00
|
||||||
|
0x0218,0x00
|
||||||
|
0x0219,0x00
|
||||||
|
0x021A,0x00
|
||||||
|
0x021B,0x00
|
||||||
|
0x021C,0x00
|
||||||
|
0x021D,0x00
|
||||||
|
0x021E,0x00
|
||||||
|
0x021F,0x00
|
||||||
|
0x0220,0x00
|
||||||
|
0x0221,0x00
|
||||||
|
0x0222,0x00
|
||||||
|
0x0223,0x00
|
||||||
|
0x0224,0x00
|
||||||
|
0x0225,0x00
|
||||||
|
0x0226,0x00
|
||||||
|
0x0227,0x00
|
||||||
|
0x0228,0x00
|
||||||
|
0x0229,0x00
|
||||||
|
0x022A,0x00
|
||||||
|
0x022B,0x00
|
||||||
|
0x022C,0x00
|
||||||
|
0x022D,0x00
|
||||||
|
0x022E,0x00
|
||||||
|
0x022F,0x00
|
||||||
|
0x0235,0xA0
|
||||||
|
0x0236,0x2A
|
||||||
|
0x0237,0xCD
|
||||||
|
0x0238,0xD8
|
||||||
|
0x0239,0xAD
|
||||||
|
0x023A,0x00
|
||||||
|
0x023B,0x00
|
||||||
|
0x023C,0x80
|
||||||
|
0x023D,0x96
|
||||||
|
0x023E,0x98
|
||||||
|
0x0250,0x00
|
||||||
|
0x0251,0x00
|
||||||
|
0x0252,0x00
|
||||||
|
0x0253,0x00
|
||||||
|
0x0254,0x00
|
||||||
|
0x0255,0x00
|
||||||
|
0x025C,0x00
|
||||||
|
0x025D,0x00
|
||||||
|
0x025E,0x00
|
||||||
|
0x025F,0x00
|
||||||
|
0x0260,0x00
|
||||||
|
0x0261,0x00
|
||||||
|
0x026B,0x4E
|
||||||
|
0x026C,0x54
|
||||||
|
0x026D,0x32
|
||||||
|
0x026E,0x30
|
||||||
|
0x026F,0x30
|
||||||
|
0x0270,0x00
|
||||||
|
0x0271,0x00
|
||||||
|
0x0272,0x00
|
||||||
|
0x0302,0x00
|
||||||
|
0x0303,0x00
|
||||||
|
0x0304,0x00
|
||||||
|
0x0305,0x00
|
||||||
|
0x0306,0x0F
|
||||||
|
0x0307,0x00
|
||||||
|
0x0308,0x00
|
||||||
|
0x0309,0x00
|
||||||
|
0x030A,0x00
|
||||||
|
0x030B,0x80
|
||||||
|
0x030C,0x00
|
||||||
|
0x030D,0xAA
|
||||||
|
0x030E,0xD2
|
||||||
|
0x030F,0x8C
|
||||||
|
0x0310,0xDD
|
||||||
|
0x0311,0x0A
|
||||||
|
0x0312,0x00
|
||||||
|
0x0313,0xFC
|
||||||
|
0x0314,0x8D
|
||||||
|
0x0315,0x0E
|
||||||
|
0x0316,0x80
|
||||||
|
0x0317,0x00
|
||||||
|
0x0318,0x00
|
||||||
|
0x0319,0x00
|
||||||
|
0x031A,0x00
|
||||||
|
0x031B,0x00
|
||||||
|
0x031C,0x00
|
||||||
|
0x031D,0x00
|
||||||
|
0x031E,0x00
|
||||||
|
0x031F,0x00
|
||||||
|
0x0320,0x00
|
||||||
|
0x0321,0x00
|
||||||
|
0x0322,0x00
|
||||||
|
0x0323,0x00
|
||||||
|
0x0324,0x00
|
||||||
|
0x0325,0x00
|
||||||
|
0x0326,0x00
|
||||||
|
0x0327,0x00
|
||||||
|
0x0328,0x00
|
||||||
|
0x0329,0x00
|
||||||
|
0x032A,0x00
|
||||||
|
0x032B,0x00
|
||||||
|
0x032C,0x00
|
||||||
|
0x032D,0x00
|
||||||
|
0x0338,0x00
|
||||||
|
0x0339,0x1F
|
||||||
|
0x033B,0x00
|
||||||
|
0x033C,0x00
|
||||||
|
0x033D,0x00
|
||||||
|
0x033E,0x00
|
||||||
|
0x033F,0x00
|
||||||
|
0x0340,0x00
|
||||||
|
0x0341,0x00
|
||||||
|
0x0342,0x00
|
||||||
|
0x0343,0x00
|
||||||
|
0x0344,0x00
|
||||||
|
0x0345,0x00
|
||||||
|
0x0346,0x00
|
||||||
|
0x0347,0x00
|
||||||
|
0x0348,0x00
|
||||||
|
0x0349,0x00
|
||||||
|
0x034A,0x00
|
||||||
|
0x034B,0x00
|
||||||
|
0x034C,0x00
|
||||||
|
0x034D,0x00
|
||||||
|
0x034E,0x00
|
||||||
|
0x034F,0x00
|
||||||
|
0x0350,0x00
|
||||||
|
0x0351,0x00
|
||||||
|
0x0352,0x00
|
||||||
|
0x0359,0x00
|
||||||
|
0x035A,0x00
|
||||||
|
0x035B,0x00
|
||||||
|
0x035C,0x00
|
||||||
|
0x035D,0x00
|
||||||
|
0x035E,0x00
|
||||||
|
0x035F,0x00
|
||||||
|
0x0360,0x00
|
||||||
|
0x0802,0x00
|
||||||
|
0x0803,0x00
|
||||||
|
0x0804,0x00
|
||||||
|
0x0805,0x00
|
||||||
|
0x0806,0x00
|
||||||
|
0x0807,0x00
|
||||||
|
0x0808,0x00
|
||||||
|
0x0809,0x00
|
||||||
|
0x080A,0x00
|
||||||
|
0x080B,0x00
|
||||||
|
0x080C,0x00
|
||||||
|
0x080D,0x00
|
||||||
|
0x080E,0x00
|
||||||
|
0x080F,0x00
|
||||||
|
0x0810,0x00
|
||||||
|
0x0811,0x00
|
||||||
|
0x0812,0x00
|
||||||
|
0x0813,0x00
|
||||||
|
0x0814,0x00
|
||||||
|
0x0815,0x00
|
||||||
|
0x0816,0x00
|
||||||
|
0x0817,0x00
|
||||||
|
0x0818,0x00
|
||||||
|
0x0819,0x00
|
||||||
|
0x081A,0x00
|
||||||
|
0x081B,0x00
|
||||||
|
0x081C,0x00
|
||||||
|
0x081D,0x00
|
||||||
|
0x081E,0x00
|
||||||
|
0x081F,0x00
|
||||||
|
0x0820,0x00
|
||||||
|
0x0821,0x00
|
||||||
|
0x0822,0x00
|
||||||
|
0x0823,0x00
|
||||||
|
0x0824,0x00
|
||||||
|
0x0825,0x00
|
||||||
|
0x0826,0x00
|
||||||
|
0x0827,0x00
|
||||||
|
0x0828,0x00
|
||||||
|
0x0829,0x00
|
||||||
|
0x082A,0x00
|
||||||
|
0x082B,0x00
|
||||||
|
0x082C,0x00
|
||||||
|
0x082D,0x00
|
||||||
|
0x082E,0x00
|
||||||
|
0x082F,0x00
|
||||||
|
0x0830,0x00
|
||||||
|
0x0831,0x00
|
||||||
|
0x0832,0x00
|
||||||
|
0x0833,0x00
|
||||||
|
0x0834,0x00
|
||||||
|
0x0835,0x00
|
||||||
|
0x0836,0x00
|
||||||
|
0x0837,0x00
|
||||||
|
0x0838,0x00
|
||||||
|
0x0839,0x00
|
||||||
|
0x083A,0x00
|
||||||
|
0x083B,0x00
|
||||||
|
0x083C,0x00
|
||||||
|
0x083D,0x00
|
||||||
|
0x083E,0x00
|
||||||
|
0x083F,0x00
|
||||||
|
0x0840,0x00
|
||||||
|
0x0841,0x00
|
||||||
|
0x0842,0x00
|
||||||
|
0x0843,0x00
|
||||||
|
0x0844,0x00
|
||||||
|
0x0845,0x00
|
||||||
|
0x0846,0x00
|
||||||
|
0x0847,0x00
|
||||||
|
0x0848,0x00
|
||||||
|
0x0849,0x00
|
||||||
|
0x084A,0x00
|
||||||
|
0x084B,0x00
|
||||||
|
0x084C,0x00
|
||||||
|
0x084D,0x00
|
||||||
|
0x084E,0x00
|
||||||
|
0x084F,0x00
|
||||||
|
0x0850,0x00
|
||||||
|
0x0851,0x00
|
||||||
|
0x0852,0x00
|
||||||
|
0x0853,0x00
|
||||||
|
0x0854,0x00
|
||||||
|
0x0855,0x00
|
||||||
|
0x0856,0x00
|
||||||
|
0x0857,0x00
|
||||||
|
0x0858,0x00
|
||||||
|
0x0859,0x00
|
||||||
|
0x085A,0x00
|
||||||
|
0x085B,0x00
|
||||||
|
0x085C,0x00
|
||||||
|
0x085D,0x00
|
||||||
|
0x085E,0x00
|
||||||
|
0x085F,0x00
|
||||||
|
0x0860,0x00
|
||||||
|
0x0861,0x00
|
||||||
|
0x090E,0x02
|
||||||
|
0x091C,0x04
|
||||||
|
0x0943,0x00
|
||||||
|
0x0949,0x00
|
||||||
|
0x094A,0x00
|
||||||
|
0x094E,0x49
|
||||||
|
0x094F,0x02
|
||||||
|
0x095E,0x00
|
||||||
|
0x0A02,0x00
|
||||||
|
0x0A03,0x03
|
||||||
|
0x0A04,0x01
|
||||||
|
0x0A05,0x03
|
||||||
|
0x0A14,0x00
|
||||||
|
0x0A1A,0x00
|
||||||
|
0x0A20,0x00
|
||||||
|
0x0A26,0x00
|
||||||
|
0x0B44,0x0F
|
||||||
|
0x0B4A,0x0C
|
||||||
|
0x0B57,0x0E
|
||||||
|
0x0B58,0x01
|
||||||
|
# End configuration registers
|
||||||
|
#
|
||||||
|
# Start configuration postamble
|
||||||
|
0x001C,0x01
|
||||||
|
0x0B24,0xC3
|
||||||
|
0x0B25,0x02
|
||||||
|
# End configuration postamble
|
||||||
642
src/eth/example/NT200A02/fpga/pll/si5340_i2c_init.py
Executable file
642
src/eth/example/NT200A02/fpga/pll/si5340_i2c_init.py
Executable file
@@ -0,0 +1,642 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
"""
|
||||||
|
Generates an I2C init module for multiple chips
|
||||||
|
"""
|
||||||
|
|
||||||
|
from jinja2 import Template
|
||||||
|
|
||||||
|
|
||||||
|
def si5340_cmds(regs, dev_addr=0x77):
|
||||||
|
cur_page = None
|
||||||
|
cur_addr = None
|
||||||
|
|
||||||
|
cmds = []
|
||||||
|
|
||||||
|
print(f"Reading register list file '{regs}'...")
|
||||||
|
|
||||||
|
with open(regs, "r") as f:
|
||||||
|
for line in f:
|
||||||
|
line = line.strip()
|
||||||
|
if not line or line == "Address,Data":
|
||||||
|
continue
|
||||||
|
if line[0] == '#':
|
||||||
|
cmds.append(f"// {line[1:].strip()}")
|
||||||
|
|
||||||
|
if line.startswith("# Delay"):
|
||||||
|
cmds.append("cmd_delay(10); // delay 300 ms")
|
||||||
|
cur_addr = None
|
||||||
|
|
||||||
|
continue
|
||||||
|
|
||||||
|
d = line.split(",")
|
||||||
|
addr = int(d[0], 0)
|
||||||
|
page = (addr >> 8) & 0xff
|
||||||
|
data = int(d[1], 0)
|
||||||
|
|
||||||
|
if page != cur_page:
|
||||||
|
cmds.append(f"cmd_start(7'h{dev_addr:02x});")
|
||||||
|
cmds.append("cmd_wr(8'h01);")
|
||||||
|
cmds.append(f"cmd_wr(8'h{page:02x}); // set page {page:#04x}")
|
||||||
|
cur_page = page
|
||||||
|
cur_addr = None
|
||||||
|
|
||||||
|
if addr != cur_addr:
|
||||||
|
cmds.append(f"cmd_start(7'h{dev_addr:02x});")
|
||||||
|
cmds.append(f"cmd_wr(8'h{addr & 0xff:02x});")
|
||||||
|
cur_addr = addr
|
||||||
|
|
||||||
|
cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x} to {addr:#06x}")
|
||||||
|
cur_addr += 1
|
||||||
|
|
||||||
|
return cmds
|
||||||
|
|
||||||
|
|
||||||
|
def mux_cmds(val, dev_addr):
|
||||||
|
cmds = []
|
||||||
|
cmds.append(f"cmd_start(7'h{dev_addr:02x});")
|
||||||
|
cmds.append(f"cmd_wr(8'h{val:02x});")
|
||||||
|
cmds.append("cmd_stop(); // I2C stop")
|
||||||
|
return cmds
|
||||||
|
|
||||||
|
|
||||||
|
def main():
|
||||||
|
cmds = []
|
||||||
|
|
||||||
|
cmds.append("// Initial delay")
|
||||||
|
cmds.append("cmd_delay(6); // delay 30 ms")
|
||||||
|
|
||||||
|
cmds.extend(si5340_cmds("Si5340-RevD-NT200-Registers.txt", 0x74))
|
||||||
|
|
||||||
|
generate(cmds, output="si5340_i2c_init.sv")
|
||||||
|
|
||||||
|
|
||||||
|
def generate(cmds=None, name=None, output=None):
|
||||||
|
if cmds is None:
|
||||||
|
raise Exception("Command list is required")
|
||||||
|
|
||||||
|
if name is None:
|
||||||
|
name = "si5340_i2c_init"
|
||||||
|
|
||||||
|
if output is None:
|
||||||
|
output = name + ".sv"
|
||||||
|
|
||||||
|
print(f"Generating Si5340 I2C init module {name}...")
|
||||||
|
|
||||||
|
cmds = cmds.copy()
|
||||||
|
cmds.append("cmd_halt(); // end")
|
||||||
|
|
||||||
|
cmd_str = ""
|
||||||
|
cmd_count = 0
|
||||||
|
|
||||||
|
for cmd in cmds:
|
||||||
|
if cmd.startswith('//'):
|
||||||
|
cmd_str += f" {cmd}\n"
|
||||||
|
else:
|
||||||
|
cmd_str += f" init_data[{cmd_count}] = {cmd}\n"
|
||||||
|
cmd_count += 1
|
||||||
|
|
||||||
|
t = Template(u"""// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2015-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* {{name}}
|
||||||
|
*/
|
||||||
|
module {{name}} #
|
||||||
|
(
|
||||||
|
parameter logic SIM_SPEEDUP = 1'b0
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire logic clk,
|
||||||
|
input wire logic rst,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C master interface
|
||||||
|
*/
|
||||||
|
taxi_axis_if.src m_axis_cmd,
|
||||||
|
taxi_axis_if.src m_axis_tx,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
output wire logic busy,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
input wire logic start
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
|
||||||
|
Generic module for I2C bus initialization. Good for use when multiple devices
|
||||||
|
on an I2C bus must be initialized on system start without intervention of a
|
||||||
|
general-purpose processor.
|
||||||
|
|
||||||
|
Copy this file and change init_data and INIT_DATA_LEN as needed.
|
||||||
|
|
||||||
|
This module can be used in two modes: simple device initialization, or multiple
|
||||||
|
device initialization. In multiple device mode, the same initialization sequence
|
||||||
|
can be performed on multiple different device addresses.
|
||||||
|
|
||||||
|
To use single device mode, only use the start write to address and write data commands.
|
||||||
|
The module will generate the I2C commands in sequential order. Terminate the list
|
||||||
|
with a 0 entry.
|
||||||
|
|
||||||
|
To use the multiple device mode, use the start data and start address block commands
|
||||||
|
to set up lists of initialization data and device addresses. The module enters
|
||||||
|
multiple device mode upon seeing a start data block command. The module stores the
|
||||||
|
offset of the start of the data block and then skips ahead until it reaches a start
|
||||||
|
address block command. The module will store the offset to the address block and
|
||||||
|
read the first address in the block. Then it will jump back to the data block
|
||||||
|
and execute it, substituting the stored address for each current address write
|
||||||
|
command. Upon reaching the start address block command, the module will read out the
|
||||||
|
next address and start again at the top of the data block. If the module encounters
|
||||||
|
a start data block command while looking for an address, then it will store a new data
|
||||||
|
offset and then look for a start address block command. Terminate the list with a 0
|
||||||
|
entry. Normal address commands will operate normally inside a data block.
|
||||||
|
|
||||||
|
Commands:
|
||||||
|
|
||||||
|
00 0000000 : stop
|
||||||
|
00 0000001 : exit multiple device mode
|
||||||
|
00 0000011 : start write to current address
|
||||||
|
00 0001000 : start address block
|
||||||
|
00 0001001 : start data block
|
||||||
|
00 001dddd : delay 2**(16+d) cycles
|
||||||
|
00 1000001 : send I2C stop
|
||||||
|
01 aaaaaaa : start write to address
|
||||||
|
1 dddddddd : write 8-bit data
|
||||||
|
|
||||||
|
Examples
|
||||||
|
|
||||||
|
write 0x11223344 to register 0x0004 on device at 0x50
|
||||||
|
|
||||||
|
01 1010000 start write to 0x50
|
||||||
|
1 00000000 write address 0x0004
|
||||||
|
1 00000100
|
||||||
|
1 00010001 write data 0x11223344
|
||||||
|
1 00100010
|
||||||
|
1 00110011
|
||||||
|
1 01000100
|
||||||
|
0 00000000 stop
|
||||||
|
|
||||||
|
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
|
||||||
|
|
||||||
|
00 0001001 start data block
|
||||||
|
00 0000011 start write to current address
|
||||||
|
1 00000000 write address 0x0004
|
||||||
|
1 00000100
|
||||||
|
1 00010001 write data 0x11223344
|
||||||
|
1 00100010
|
||||||
|
1 00110011
|
||||||
|
1 01000100
|
||||||
|
00 0001000 start address block
|
||||||
|
01 1010000 address 0x50
|
||||||
|
01 1010001 address 0x51
|
||||||
|
01 1010010 address 0x52
|
||||||
|
01 1010011 address 0x53
|
||||||
|
00 0000001 exit multi-dev mode
|
||||||
|
00 0000000 stop
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// check configuration
|
||||||
|
if (m_axis_cmd.DATA_W < 12)
|
||||||
|
$fatal(0, "Command interface width must be at least 12 bits (instance %m)");
|
||||||
|
|
||||||
|
if (m_axis_tx.DATA_W != 8)
|
||||||
|
$fatal(0, "Data interface width must be 8 bits (instance %m)");
|
||||||
|
|
||||||
|
function [8:0] cmd_start(input [6:0] addr);
|
||||||
|
cmd_start = {2'b01, addr};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_wr(input [7:0] data);
|
||||||
|
cmd_wr = {1'b1, data};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_stop();
|
||||||
|
cmd_stop = {2'b00, 7'b1000001};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_delay(input [3:0] d);
|
||||||
|
cmd_delay = {2'b00, 3'b001, d};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_halt();
|
||||||
|
cmd_halt = 9'd0;
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] blk_start_data();
|
||||||
|
blk_start_data = {2'b00, 7'b0001001};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] blk_start_addr();
|
||||||
|
blk_start_addr = {2'b00, 7'b0001000};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_start_cur();
|
||||||
|
cmd_start_cur = {2'b00, 7'b0000011};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function [8:0] cmd_exit();
|
||||||
|
cmd_exit = {2'b00, 7'b0000001};
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
// init_data ROM
|
||||||
|
localparam INIT_DATA_LEN = {{cmd_count}};
|
||||||
|
|
||||||
|
reg [8:0] init_data [INIT_DATA_LEN-1:0];
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
{{cmd_str-}}
|
||||||
|
end
|
||||||
|
|
||||||
|
typedef enum logic [2:0] {
|
||||||
|
STATE_IDLE,
|
||||||
|
STATE_RUN,
|
||||||
|
STATE_TABLE_1,
|
||||||
|
STATE_TABLE_2,
|
||||||
|
STATE_TABLE_3
|
||||||
|
} state_t;
|
||||||
|
|
||||||
|
state_t state_reg = STATE_IDLE, state_next;
|
||||||
|
|
||||||
|
localparam AW = $clog2(INIT_DATA_LEN);
|
||||||
|
|
||||||
|
logic [8:0] init_data_reg = '0;
|
||||||
|
|
||||||
|
logic [AW-1:0] address_reg = '0, address_next;
|
||||||
|
logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
|
||||||
|
logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
|
||||||
|
|
||||||
|
logic [6:0] cur_address_reg = '0, cur_address_next;
|
||||||
|
|
||||||
|
logic [31:0] delay_counter_reg = '0, delay_counter_next;
|
||||||
|
|
||||||
|
logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
|
||||||
|
logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
|
||||||
|
logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
|
||||||
|
logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
|
||||||
|
logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
|
||||||
|
|
||||||
|
logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
|
||||||
|
logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
|
||||||
|
|
||||||
|
logic start_flag_reg = 1'b0, start_flag_next;
|
||||||
|
|
||||||
|
logic busy_reg = 1'b0;
|
||||||
|
|
||||||
|
assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
|
||||||
|
assign m_axis_cmd.tdata[7] = m_axis_cmd_start_reg;
|
||||||
|
assign m_axis_cmd.tdata[8] = 1'b0; // read
|
||||||
|
assign m_axis_cmd.tdata[9] = m_axis_cmd_write_reg;
|
||||||
|
assign m_axis_cmd.tdata[10] = 1'b0; // write multi
|
||||||
|
assign m_axis_cmd.tdata[11] = m_axis_cmd_stop_reg;
|
||||||
|
assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
|
||||||
|
assign m_axis_cmd.tlast = 1'b1;
|
||||||
|
assign m_axis_cmd.tid = '0;
|
||||||
|
assign m_axis_cmd.tdest = '0;
|
||||||
|
assign m_axis_cmd.tuser = '0;
|
||||||
|
|
||||||
|
assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
|
||||||
|
assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
|
||||||
|
assign m_axis_tx.tlast = 1'b1;
|
||||||
|
assign m_axis_tx.tid = '0;
|
||||||
|
assign m_axis_tx.tdest = '0;
|
||||||
|
assign m_axis_tx.tuser = '0;
|
||||||
|
|
||||||
|
assign busy = busy_reg;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
|
||||||
|
address_next = address_reg;
|
||||||
|
address_ptr_next = address_ptr_reg;
|
||||||
|
data_ptr_next = data_ptr_reg;
|
||||||
|
|
||||||
|
cur_address_next = cur_address_reg;
|
||||||
|
|
||||||
|
delay_counter_next = delay_counter_reg;
|
||||||
|
|
||||||
|
m_axis_cmd_address_next = m_axis_cmd_address_reg;
|
||||||
|
m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
|
||||||
|
m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
|
||||||
|
m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
|
||||||
|
m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
|
||||||
|
|
||||||
|
m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
|
||||||
|
m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
|
||||||
|
|
||||||
|
start_flag_next = start_flag_reg;
|
||||||
|
|
||||||
|
if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
|
||||||
|
// wait for output registers to clear
|
||||||
|
state_next = state_reg;
|
||||||
|
end else if (delay_counter_reg != 0) begin
|
||||||
|
// delay
|
||||||
|
delay_counter_next = delay_counter_reg - 1;
|
||||||
|
state_next = state_reg;
|
||||||
|
end else begin
|
||||||
|
case (state_reg)
|
||||||
|
STATE_IDLE: begin
|
||||||
|
// wait for start signal
|
||||||
|
if (!start_flag_reg && start) begin
|
||||||
|
address_next = '0;
|
||||||
|
start_flag_next = 1'b1;
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else begin
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_RUN: begin
|
||||||
|
// process commands
|
||||||
|
if (init_data_reg[8] == 1'b1) begin
|
||||||
|
// write data
|
||||||
|
m_axis_cmd_write_next = 1'b1;
|
||||||
|
m_axis_cmd_stop_next = 1'b0;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
m_axis_tx_tdata_next = init_data_reg[7:0];
|
||||||
|
m_axis_tx_tvalid_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg[8:7] == 2'b01) begin
|
||||||
|
// write address
|
||||||
|
m_axis_cmd_address_next = init_data_reg[6:0];
|
||||||
|
m_axis_cmd_start_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg[8:4] == 5'b00001) begin
|
||||||
|
// delay
|
||||||
|
if (SIM_SPEEDUP) begin
|
||||||
|
delay_counter_next = 32'd1 << (init_data_reg[3:0]);
|
||||||
|
end else begin
|
||||||
|
delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
|
||||||
|
end
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg == 9'b001000001) begin
|
||||||
|
// send stop
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg == 9'b000001001) begin
|
||||||
|
// data table start
|
||||||
|
data_ptr_next = address_reg + 1;
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_1;
|
||||||
|
end else if (init_data_reg == 9'd0) begin
|
||||||
|
// stop
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
// invalid command, skip
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_TABLE_1: begin
|
||||||
|
// find address table start
|
||||||
|
if (init_data_reg == 9'b000001000) begin
|
||||||
|
// address table start
|
||||||
|
address_ptr_next = address_reg + 1;
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_2;
|
||||||
|
end else if (init_data_reg == 9'b000001001) begin
|
||||||
|
// data table start
|
||||||
|
data_ptr_next = address_reg + 1;
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_1;
|
||||||
|
end else if (init_data_reg == 1) begin
|
||||||
|
// exit mode
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg == 9'd0) begin
|
||||||
|
// stop
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
// invalid command, skip
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_TABLE_2: begin
|
||||||
|
// find next address
|
||||||
|
if (init_data_reg[8:7] == 2'b01) begin
|
||||||
|
// write address command
|
||||||
|
// store address and move to data table
|
||||||
|
cur_address_next = init_data_reg[6:0];
|
||||||
|
address_ptr_next = address_reg + 1;
|
||||||
|
address_next = data_ptr_reg;
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg == 9'b000001001) begin
|
||||||
|
// data table start
|
||||||
|
data_ptr_next = address_reg + 1;
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_1;
|
||||||
|
end else if (init_data_reg == 9'd1) begin
|
||||||
|
// exit mode
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg == 9'd0) begin
|
||||||
|
// stop
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
// invalid command, skip
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_2;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_TABLE_3: begin
|
||||||
|
// process data table with selected address
|
||||||
|
if (init_data_reg[8] == 1'b1) begin
|
||||||
|
// write data
|
||||||
|
m_axis_cmd_write_next = 1'b1;
|
||||||
|
m_axis_cmd_stop_next = 1'b0;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
m_axis_tx_tdata_next = init_data_reg[7:0];
|
||||||
|
m_axis_tx_tvalid_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg[8:7] == 2'b01) begin
|
||||||
|
// write address
|
||||||
|
m_axis_cmd_address_next = init_data_reg[6:0];
|
||||||
|
m_axis_cmd_start_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg == 9'b000000011) begin
|
||||||
|
// write current address
|
||||||
|
m_axis_cmd_address_next = cur_address_reg;
|
||||||
|
m_axis_cmd_start_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg[8:4] == 5'b00001) begin
|
||||||
|
// delay
|
||||||
|
if (SIM_SPEEDUP) begin
|
||||||
|
delay_counter_next = 32'd1 << (init_data_reg[3:0]);
|
||||||
|
end else begin
|
||||||
|
delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
|
||||||
|
end
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg == 9'b001000001) begin
|
||||||
|
// send stop
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end else if (init_data_reg == 9'b000001001) begin
|
||||||
|
// data table start
|
||||||
|
data_ptr_next = address_reg + 1;
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_1;
|
||||||
|
end else if (init_data_reg == 9'b000001000) begin
|
||||||
|
// address table start
|
||||||
|
address_next = address_ptr_reg;
|
||||||
|
state_next = STATE_TABLE_2;
|
||||||
|
end else if (init_data_reg == 9'd1) begin
|
||||||
|
// exit mode
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_RUN;
|
||||||
|
end else if (init_data_reg == 9'd0) begin
|
||||||
|
// stop
|
||||||
|
m_axis_cmd_start_next = 1'b0;
|
||||||
|
m_axis_cmd_write_next = 1'b0;
|
||||||
|
m_axis_cmd_stop_next = 1'b1;
|
||||||
|
m_axis_cmd_valid_next = 1'b1;
|
||||||
|
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end else begin
|
||||||
|
// invalid command, skip
|
||||||
|
address_next = address_reg + 1;
|
||||||
|
state_next = STATE_TABLE_3;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
// invalid state
|
||||||
|
state_next = STATE_IDLE;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always_ff @(posedge clk) begin
|
||||||
|
state_reg <= state_next;
|
||||||
|
|
||||||
|
// read init_data ROM
|
||||||
|
init_data_reg <= init_data[address_next];
|
||||||
|
|
||||||
|
address_reg <= address_next;
|
||||||
|
address_ptr_reg <= address_ptr_next;
|
||||||
|
data_ptr_reg <= data_ptr_next;
|
||||||
|
|
||||||
|
cur_address_reg <= cur_address_next;
|
||||||
|
|
||||||
|
delay_counter_reg <= delay_counter_next;
|
||||||
|
|
||||||
|
m_axis_cmd_address_reg <= m_axis_cmd_address_next;
|
||||||
|
m_axis_cmd_start_reg <= m_axis_cmd_start_next;
|
||||||
|
m_axis_cmd_write_reg <= m_axis_cmd_write_next;
|
||||||
|
m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
|
||||||
|
m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
|
||||||
|
|
||||||
|
m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
|
||||||
|
m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
|
||||||
|
|
||||||
|
start_flag_reg <= start && start_flag_next;
|
||||||
|
|
||||||
|
busy_reg <= (state_reg != STATE_IDLE);
|
||||||
|
|
||||||
|
if (rst) begin
|
||||||
|
state_reg <= STATE_IDLE;
|
||||||
|
|
||||||
|
init_data_reg <= '0;
|
||||||
|
|
||||||
|
address_reg <= '0;
|
||||||
|
address_ptr_reg <= '0;
|
||||||
|
data_ptr_reg <= '0;
|
||||||
|
|
||||||
|
cur_address_reg <= '0;
|
||||||
|
|
||||||
|
delay_counter_reg <= '0;
|
||||||
|
|
||||||
|
m_axis_cmd_valid_reg <= 1'b0;
|
||||||
|
|
||||||
|
m_axis_tx_tvalid_reg <= 1'b0;
|
||||||
|
|
||||||
|
start_flag_reg <= 1'b0;
|
||||||
|
|
||||||
|
busy_reg <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
""")
|
||||||
|
|
||||||
|
print(f"Writing file '{output}'...")
|
||||||
|
|
||||||
|
with open(output, 'w') as f:
|
||||||
|
f.write(t.render(
|
||||||
|
cmd_str=cmd_str,
|
||||||
|
cmd_count=cmd_count,
|
||||||
|
name=name
|
||||||
|
))
|
||||||
|
f.flush()
|
||||||
|
|
||||||
|
print("Done")
|
||||||
|
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
1013
src/eth/example/NT200A02/fpga/pll/si5340_i2c_init.sv
Normal file
1013
src/eth/example/NT200A02/fpga/pll/si5340_i2c_init.sv
Normal file
File diff suppressed because it is too large
Load Diff
483
src/eth/example/NT200A02/fpga/rtl/fpga_core.sv
Normal file
483
src/eth/example/NT200A02/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,483 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA core logic
|
||||||
|
*/
|
||||||
|
module fpga_core #
|
||||||
|
(
|
||||||
|
// simulation (set to avoid vendor primitives)
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
// device family
|
||||||
|
parameter string FAMILY = "virtexuplus",
|
||||||
|
// Board configuration
|
||||||
|
parameter PORT_CNT = 2,
|
||||||
|
parameter GTY_QUAD_CNT = PORT_CNT,
|
||||||
|
parameter GTY_CNT = GTY_QUAD_CNT*4,
|
||||||
|
parameter GTY_CLK_CNT = GTY_QUAD_CNT,
|
||||||
|
// 10G/25G MAC configuration
|
||||||
|
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||||
|
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||||
|
parameter MAC_DATA_W = 64
|
||||||
|
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 125 MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
input wire logic clk_125mhz,
|
||||||
|
input wire logic rst_125mhz,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
output wire logic [3:0] led,
|
||||||
|
output wire logic [3:0] qsfp_led[PORT_CNT],
|
||||||
|
output wire logic led_red,
|
||||||
|
output wire logic led_green,
|
||||||
|
output wire logic [1:0] led_sync,
|
||||||
|
output wire logic eth_led_yellow,
|
||||||
|
output wire logic eth_led_green,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
output wire logic eth_gty_tx_p[GTY_CNT],
|
||||||
|
output wire logic eth_gty_tx_n[GTY_CNT],
|
||||||
|
input wire logic eth_gty_rx_p[GTY_CNT],
|
||||||
|
input wire logic eth_gty_rx_n[GTY_CNT],
|
||||||
|
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
|
||||||
|
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
|
||||||
|
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
|
||||||
|
|
||||||
|
output wire logic [PORT_CNT-1:0] eth_port_resetl,
|
||||||
|
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
|
||||||
|
input wire logic [PORT_CNT-1:0] eth_port_intl,
|
||||||
|
output wire logic [PORT_CNT-1:0] eth_port_lpmode,
|
||||||
|
|
||||||
|
input wire logic [PORT_CNT-1:0] eth_port_i2c_scl_i,
|
||||||
|
output wire logic [PORT_CNT-1:0] eth_port_i2c_scl_o,
|
||||||
|
input wire logic [PORT_CNT-1:0] eth_port_i2c_sda_i,
|
||||||
|
output wire logic [PORT_CNT-1:0] eth_port_i2c_sda_o
|
||||||
|
);
|
||||||
|
|
||||||
|
assign eth_port_i2c_scl_o = '1;
|
||||||
|
assign eth_port_i2c_sda_o = '1;
|
||||||
|
|
||||||
|
// QSFP28
|
||||||
|
assign eth_port_resetl = '1;
|
||||||
|
assign eth_port_lpmode = '0;
|
||||||
|
|
||||||
|
wire eth_gty_tx_clk[GTY_CNT];
|
||||||
|
wire eth_gty_tx_rst[GTY_CNT];
|
||||||
|
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
|
||||||
|
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
|
||||||
|
|
||||||
|
wire eth_gty_rx_clk[GTY_CNT];
|
||||||
|
wire eth_gty_rx_rst[GTY_CNT];
|
||||||
|
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
|
||||||
|
|
||||||
|
wire eth_gty_rx_status[GTY_CNT];
|
||||||
|
|
||||||
|
assign qsfp_led[0][0] = eth_gty_rx_status[0];
|
||||||
|
assign qsfp_led[0][1] = eth_gty_rx_status[1];
|
||||||
|
assign qsfp_led[0][2] = eth_gty_rx_status[2];
|
||||||
|
assign qsfp_led[0][3] = eth_gty_rx_status[3];
|
||||||
|
assign qsfp_led[1][0] = eth_gty_rx_status[4];
|
||||||
|
assign qsfp_led[1][1] = eth_gty_rx_status[5];
|
||||||
|
assign qsfp_led[1][2] = eth_gty_rx_status[6];
|
||||||
|
assign qsfp_led[1][3] = eth_gty_rx_status[7];
|
||||||
|
|
||||||
|
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
|
||||||
|
|
||||||
|
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
|
||||||
|
|
||||||
|
wire eth_gty_rst[GTY_CLK_CNT];
|
||||||
|
|
||||||
|
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
|
||||||
|
|
||||||
|
wire eth_gty_mgt_refclk_int;
|
||||||
|
|
||||||
|
if (SIM) begin
|
||||||
|
|
||||||
|
assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
|
||||||
|
assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
|
||||||
|
assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
if (FAMILY == "virtexuplus") begin
|
||||||
|
|
||||||
|
IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||||
|
.I (eth_gty_mgt_refclk_p[n]),
|
||||||
|
.IB (eth_gty_mgt_refclk_n[n]),
|
||||||
|
.CEB (1'b0),
|
||||||
|
.O (eth_gty_mgt_refclk[n]),
|
||||||
|
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||||
|
.I (eth_gty_mgt_refclk_p[n]),
|
||||||
|
.IB (eth_gty_mgt_refclk_n[n]),
|
||||||
|
.CEB (1'b0),
|
||||||
|
.O (eth_gty_mgt_refclk[n]),
|
||||||
|
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
|
||||||
|
.CE (ð_gty_gtpowergood),
|
||||||
|
.CEMASK (1'b1),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b1),
|
||||||
|
.DIV (3'd0),
|
||||||
|
.I (eth_gty_mgt_refclk_int),
|
||||||
|
.O (eth_gty_mgt_refclk_bufg[n])
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
qsfp_sync_reset_inst (
|
||||||
|
.clk(eth_gty_mgt_refclk_bufg[n]),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
.out(eth_gty_rst[n])
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP0[4] = '{"QSFP0.1", "QSFP0.2", "QSFP0.3", "QSFP0.4"};
|
||||||
|
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
|
||||||
|
|
||||||
|
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
|
||||||
|
|
||||||
|
localparam CNT = 4;
|
||||||
|
|
||||||
|
taxi_apb_if #(
|
||||||
|
.ADDR_W(18),
|
||||||
|
.DATA_W(16)
|
||||||
|
)
|
||||||
|
gt_apb_ctrl();
|
||||||
|
|
||||||
|
taxi_eth_mac_25g_us #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
|
||||||
|
.CNT(4),
|
||||||
|
|
||||||
|
// GT config
|
||||||
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||||
|
|
||||||
|
// GT type
|
||||||
|
.GT_TYPE("GTY"),
|
||||||
|
|
||||||
|
// GT parameters
|
||||||
|
.GT_TX_POLARITY(n == 0 ? 4'b0101 : 4'b0001),
|
||||||
|
.GT_RX_POLARITY(n == 0 ? 4'b1011 : 4'b0011),
|
||||||
|
|
||||||
|
// MAC/PHY config
|
||||||
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||||
|
.DATA_W(MAC_DATA_W),
|
||||||
|
.PADDING_EN(1'b1),
|
||||||
|
.DIC_EN(1'b1),
|
||||||
|
.MIN_FRAME_LEN(64),
|
||||||
|
.PTP_TS_EN(1'b0),
|
||||||
|
.PTP_TD_EN(1'b0),
|
||||||
|
.PTP_TS_FMT_TOD(1'b1),
|
||||||
|
.PTP_TS_W(96),
|
||||||
|
.PTP_TD_SDI_PIPELINE(2),
|
||||||
|
.PRBS31_EN(1'b0),
|
||||||
|
.TX_SERDES_PIPELINE(1),
|
||||||
|
.RX_SERDES_PIPELINE(1),
|
||||||
|
.COUNT_125US(125000/6.4),
|
||||||
|
.STAT_EN(0),
|
||||||
|
.STAT_TX_LEVEL(1),
|
||||||
|
.STAT_RX_LEVEL(1),
|
||||||
|
.STAT_ID_BASE(n*CNT*(16+16)),
|
||||||
|
.STAT_UPDATE_PERIOD(1024),
|
||||||
|
.STAT_STR_EN(0),
|
||||||
|
.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP0 : STAT_PREFIX_STR_QSFP1)
|
||||||
|
)
|
||||||
|
mac_inst (
|
||||||
|
.xcvr_ctrl_clk(clk_125mhz),
|
||||||
|
.xcvr_ctrl_rst(eth_gty_rst[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transceiver control
|
||||||
|
*/
|
||||||
|
.s_apb_ctrl(gt_apb_ctrl),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Common
|
||||||
|
*/
|
||||||
|
.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
|
||||||
|
.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]),
|
||||||
|
.xcvr_qpll0pd_in(1'b0),
|
||||||
|
.xcvr_qpll0reset_in(1'b0),
|
||||||
|
.xcvr_qpll0pcierate_in(3'd0),
|
||||||
|
.xcvr_qpll0lock_out(),
|
||||||
|
.xcvr_qpll0clk_out(),
|
||||||
|
.xcvr_qpll0refclk_out(),
|
||||||
|
.xcvr_gtrefclk01_in(eth_gty_mgt_refclk[n]),
|
||||||
|
.xcvr_qpll1pd_in(1'b0),
|
||||||
|
.xcvr_qpll1reset_in(1'b0),
|
||||||
|
.xcvr_qpll1pcierate_in(3'd0),
|
||||||
|
.xcvr_qpll1lock_out(),
|
||||||
|
.xcvr_qpll1clk_out(),
|
||||||
|
.xcvr_qpll1refclk_out(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial data
|
||||||
|
*/
|
||||||
|
.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
|
||||||
|
.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
|
||||||
|
.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
|
||||||
|
.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAC clocks
|
||||||
|
*/
|
||||||
|
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
|
||||||
|
.rx_rst_in('{CNT{1'b0}}),
|
||||||
|
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
|
||||||
|
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
|
||||||
|
.tx_rst_in('{CNT{1'b0}}),
|
||||||
|
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
|
||||||
|
.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PTP clock
|
||||||
|
*/
|
||||||
|
.ptp_clk(1'b0),
|
||||||
|
.ptp_rst(1'b0),
|
||||||
|
.ptp_sample_clk(1'b0),
|
||||||
|
.ptp_td_sdi(1'b0),
|
||||||
|
.tx_ptp_ts_in('{CNT{'0}}),
|
||||||
|
.tx_ptp_ts_out(),
|
||||||
|
.tx_ptp_ts_step_out(),
|
||||||
|
.tx_ptp_locked(),
|
||||||
|
.rx_ptp_ts_in('{CNT{'0}}),
|
||||||
|
.rx_ptp_ts_out(),
|
||||||
|
.rx_ptp_ts_step_out(),
|
||||||
|
.rx_ptp_locked(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||||
|
*/
|
||||||
|
.tx_lfc_req('{CNT{1'b0}}),
|
||||||
|
.tx_lfc_resend('{CNT{1'b0}}),
|
||||||
|
.rx_lfc_en('{CNT{1'b0}}),
|
||||||
|
.rx_lfc_req(),
|
||||||
|
.rx_lfc_ack('{CNT{1'b0}}),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||||
|
*/
|
||||||
|
.tx_pfc_req('{CNT{'0}}),
|
||||||
|
.tx_pfc_resend('{CNT{1'b0}}),
|
||||||
|
.rx_pfc_en('{CNT{'0}}),
|
||||||
|
.rx_pfc_req(),
|
||||||
|
.rx_pfc_ack('{CNT{'0}}),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pause interface
|
||||||
|
*/
|
||||||
|
.tx_lfc_pause_en('{CNT{1'b0}}),
|
||||||
|
.tx_pause_req('{CNT{1'b0}}),
|
||||||
|
.tx_pause_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Statistics
|
||||||
|
*/
|
||||||
|
.stat_clk(clk_125mhz),
|
||||||
|
.stat_rst(rst_125mhz),
|
||||||
|
.m_axis_stat(axis_eth_stat[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_start_packet(),
|
||||||
|
.stat_tx_byte(),
|
||||||
|
.stat_tx_pkt_len(),
|
||||||
|
.stat_tx_pkt_ucast(),
|
||||||
|
.stat_tx_pkt_mcast(),
|
||||||
|
.stat_tx_pkt_bcast(),
|
||||||
|
.stat_tx_pkt_vlan(),
|
||||||
|
.stat_tx_pkt_good(),
|
||||||
|
.stat_tx_pkt_bad(),
|
||||||
|
.stat_tx_err_oversize(),
|
||||||
|
.stat_tx_err_user(),
|
||||||
|
.stat_tx_err_underflow(),
|
||||||
|
.rx_start_packet(),
|
||||||
|
.rx_error_count(),
|
||||||
|
.rx_block_lock(),
|
||||||
|
.rx_high_ber(),
|
||||||
|
.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
|
||||||
|
.stat_rx_byte(),
|
||||||
|
.stat_rx_pkt_len(),
|
||||||
|
.stat_rx_pkt_fragment(),
|
||||||
|
.stat_rx_pkt_jabber(),
|
||||||
|
.stat_rx_pkt_ucast(),
|
||||||
|
.stat_rx_pkt_mcast(),
|
||||||
|
.stat_rx_pkt_bcast(),
|
||||||
|
.stat_rx_pkt_vlan(),
|
||||||
|
.stat_rx_pkt_good(),
|
||||||
|
.stat_rx_pkt_bad(),
|
||||||
|
.stat_rx_err_oversize(),
|
||||||
|
.stat_rx_err_bad_fcs(),
|
||||||
|
.stat_rx_err_bad_block(),
|
||||||
|
.stat_rx_err_framing(),
|
||||||
|
.stat_rx_err_preamble(),
|
||||||
|
.stat_rx_fifo_drop('{CNT{1'b0}}),
|
||||||
|
.stat_tx_mcf(),
|
||||||
|
.stat_rx_mcf(),
|
||||||
|
.stat_tx_lfc_pkt(),
|
||||||
|
.stat_tx_lfc_xon(),
|
||||||
|
.stat_tx_lfc_xoff(),
|
||||||
|
.stat_tx_lfc_paused(),
|
||||||
|
.stat_tx_pfc_pkt(),
|
||||||
|
.stat_tx_pfc_xon(),
|
||||||
|
.stat_tx_pfc_xoff(),
|
||||||
|
.stat_tx_pfc_paused(),
|
||||||
|
.stat_rx_lfc_pkt(),
|
||||||
|
.stat_rx_lfc_xon(),
|
||||||
|
.stat_rx_lfc_xoff(),
|
||||||
|
.stat_rx_lfc_paused(),
|
||||||
|
.stat_rx_pfc_pkt(),
|
||||||
|
.stat_rx_pfc_xon(),
|
||||||
|
.stat_rx_pfc_xoff(),
|
||||||
|
.stat_rx_pfc_paused(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
||||||
|
.cfg_tx_ifg('{CNT{8'd12}}),
|
||||||
|
.cfg_tx_enable('{CNT{1'b1}}),
|
||||||
|
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
||||||
|
.cfg_rx_enable('{CNT{1'b1}}),
|
||||||
|
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
|
||||||
|
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
|
||||||
|
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
|
||||||
|
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
|
||||||
|
.cfg_mcf_rx_forward('{CNT{1'b0}}),
|
||||||
|
.cfg_mcf_rx_enable('{CNT{1'b0}}),
|
||||||
|
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||||
|
.cfg_tx_lfc_en('{CNT{1'b0}}),
|
||||||
|
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||||
|
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||||
|
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||||
|
.cfg_tx_pfc_en('{CNT{1'b0}}),
|
||||||
|
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||||
|
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||||
|
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||||
|
.cfg_rx_lfc_en('{CNT{1'b0}}),
|
||||||
|
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||||
|
.cfg_rx_pfc_en('{CNT{1'b0}})
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : qsfp_ch
|
||||||
|
|
||||||
|
taxi_axis_async_fifo #(
|
||||||
|
.DEPTH(16384),
|
||||||
|
.RAM_PIPELINE(2),
|
||||||
|
.FRAME_FIFO(1),
|
||||||
|
.USER_BAD_FRAME_VALUE(1'b1),
|
||||||
|
.USER_BAD_FRAME_MASK(1'b1),
|
||||||
|
.DROP_OVERSIZE_FRAME(1),
|
||||||
|
.DROP_BAD_FRAME(1),
|
||||||
|
.DROP_WHEN_FULL(1)
|
||||||
|
)
|
||||||
|
ch_fifo (
|
||||||
|
/*
|
||||||
|
* AXI4-Stream input (sink)
|
||||||
|
*/
|
||||||
|
.s_clk(eth_gty_rx_clk[n]),
|
||||||
|
.s_rst(eth_gty_rx_rst[n]),
|
||||||
|
.s_axis(eth_gty_axis_rx[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream output (source)
|
||||||
|
*/
|
||||||
|
.m_clk(eth_gty_tx_clk[n]),
|
||||||
|
.m_rst(eth_gty_tx_rst[n]),
|
||||||
|
.m_axis(eth_gty_axis_tx[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pause
|
||||||
|
*/
|
||||||
|
.s_pause_req(1'b0),
|
||||||
|
.s_pause_ack(),
|
||||||
|
.m_pause_req(1'b0),
|
||||||
|
.m_pause_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.s_status_depth(),
|
||||||
|
.s_status_depth_commit(),
|
||||||
|
.s_status_overflow(),
|
||||||
|
.s_status_bad_frame(),
|
||||||
|
.s_status_good_frame(),
|
||||||
|
.m_status_depth(),
|
||||||
|
.m_status_depth_commit(),
|
||||||
|
.m_status_overflow(),
|
||||||
|
.m_status_bad_frame(),
|
||||||
|
.m_status_good_frame()
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
412
src/eth/example/NT200A02/fpga/rtl/fpga_nt200a01.sv
Normal file
412
src/eth/example/NT200A02/fpga/rtl/fpga_nt200a01.sv
Normal file
@@ -0,0 +1,412 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA top-level module
|
||||||
|
*/
|
||||||
|
module fpga #
|
||||||
|
(
|
||||||
|
// simulation (set to avoid vendor primitives)
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
// device family
|
||||||
|
parameter string FAMILY = "virtexu",
|
||||||
|
// 10G/25G MAC configuration
|
||||||
|
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||||
|
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||||
|
parameter MAC_DATA_W = 64
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 50MHz
|
||||||
|
*/
|
||||||
|
input wire logic clk_50mhz,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
output wire logic [3:0] led,
|
||||||
|
output wire logic [3:0] qsfp_led[2],
|
||||||
|
output wire logic led_red,
|
||||||
|
output wire logic led_green,
|
||||||
|
output wire logic [1:0] led_sync,
|
||||||
|
output wire logic eth_led_yellow,
|
||||||
|
output wire logic eth_led_green,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C
|
||||||
|
*/
|
||||||
|
inout wire logic si5340_i2c_scl,
|
||||||
|
inout wire logic si5340_i2c_sda,
|
||||||
|
input wire logic si5340_intr,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
output wire logic qsfp0_tx_p[4],
|
||||||
|
output wire logic qsfp0_tx_n[4],
|
||||||
|
input wire logic qsfp0_rx_p[4],
|
||||||
|
input wire logic qsfp0_rx_n[4],
|
||||||
|
input wire logic qsfp0_mgt_refclk_p,
|
||||||
|
input wire logic qsfp0_mgt_refclk_n,
|
||||||
|
output wire logic qsfp0_resetl,
|
||||||
|
input wire logic qsfp0_modprsl,
|
||||||
|
input wire logic qsfp0_intl,
|
||||||
|
output wire logic qsfp0_lpmode,
|
||||||
|
inout wire logic qsfp0_i2c_scl,
|
||||||
|
inout wire logic qsfp0_i2c_sda,
|
||||||
|
|
||||||
|
output wire logic qsfp1_tx_p[4],
|
||||||
|
output wire logic qsfp1_tx_n[4],
|
||||||
|
input wire logic qsfp1_rx_p[4],
|
||||||
|
input wire logic qsfp1_rx_n[4],
|
||||||
|
input wire logic qsfp1_mgt_refclk_p,
|
||||||
|
input wire logic qsfp1_mgt_refclk_n,
|
||||||
|
output wire logic qsfp1_resetl,
|
||||||
|
input wire logic qsfp1_modprsl,
|
||||||
|
input wire logic qsfp1_intl,
|
||||||
|
output wire logic qsfp1_lpmode,
|
||||||
|
inout wire logic qsfp1_i2c_scl,
|
||||||
|
inout wire logic qsfp1_i2c_sda
|
||||||
|
);
|
||||||
|
|
||||||
|
// Clock and reset
|
||||||
|
|
||||||
|
wire clk_125mhz_mmcm_out;
|
||||||
|
|
||||||
|
// Internal 125 MHz clock
|
||||||
|
wire clk_125mhz_int;
|
||||||
|
wire rst_125mhz_int;
|
||||||
|
|
||||||
|
wire mmcm_rst = 1'b0;
|
||||||
|
wire mmcm_locked;
|
||||||
|
wire mmcm_clkfb;
|
||||||
|
|
||||||
|
// MMCM instance
|
||||||
|
MMCME3_BASE #(
|
||||||
|
// 50 MHz input
|
||||||
|
.CLKIN1_PERIOD(20.000),
|
||||||
|
.REF_JITTER1(0.010),
|
||||||
|
// 50 MHz input / 1 = 50 MHz PFD (range 10 MHz to 500 MHz)
|
||||||
|
.DIVCLK_DIVIDE(1),
|
||||||
|
// 50 MHz PFD * 20 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
|
||||||
|
.CLKFBOUT_MULT_F(20),
|
||||||
|
.CLKFBOUT_PHASE(0),
|
||||||
|
// 1000 MHz / 8 = 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0_DIVIDE_F(8),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT0_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT1_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT2_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT3_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT4_PHASE(0),
|
||||||
|
.CLKOUT4_CASCADE("FALSE"),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT5_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6_DIVIDE(1),
|
||||||
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT6_PHASE(0),
|
||||||
|
|
||||||
|
// optimized bandwidth
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
// don't wait for lock during startup
|
||||||
|
.STARTUP_WAIT("FALSE")
|
||||||
|
)
|
||||||
|
clk_mmcm_inst (
|
||||||
|
// 50 MHz input
|
||||||
|
.CLKIN1(clk_50mhz),
|
||||||
|
// direct clkfb feeback
|
||||||
|
.CLKFBIN(mmcm_clkfb),
|
||||||
|
.CLKFBOUT(mmcm_clkfb),
|
||||||
|
.CLKFBOUTB(),
|
||||||
|
// 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||||
|
.CLKOUT0B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1(),
|
||||||
|
.CLKOUT1B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2(),
|
||||||
|
.CLKOUT2B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3(),
|
||||||
|
.CLKOUT3B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6(),
|
||||||
|
// reset input
|
||||||
|
.RST(mmcm_rst),
|
||||||
|
// don't power down
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
// locked output
|
||||||
|
.LOCKED(mmcm_locked)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG
|
||||||
|
clk_125mhz_bufg_inst (
|
||||||
|
.I(clk_125mhz_mmcm_out),
|
||||||
|
.O(clk_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
sync_reset_125mhz_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(~mmcm_locked),
|
||||||
|
.out(rst_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
// GPIO
|
||||||
|
wire qsfp0_modprsl_int;
|
||||||
|
wire qsfp0_intl_int;
|
||||||
|
wire qsfp0_i2c_scl_i;
|
||||||
|
wire qsfp0_i2c_scl_o;
|
||||||
|
wire qsfp0_i2c_sda_i;
|
||||||
|
wire qsfp0_i2c_sda_o;
|
||||||
|
|
||||||
|
wire qsfp1_modprsl_int;
|
||||||
|
wire qsfp1_intl_int;
|
||||||
|
wire qsfp1_i2c_scl_i;
|
||||||
|
wire qsfp1_i2c_scl_o;
|
||||||
|
wire qsfp1_i2c_sda_i;
|
||||||
|
wire qsfp1_i2c_sda_o;
|
||||||
|
|
||||||
|
logic qsfp0_i2c_scl_o_reg;
|
||||||
|
logic qsfp0_i2c_sda_o_reg;
|
||||||
|
|
||||||
|
logic qsfp1_i2c_scl_o_reg;
|
||||||
|
logic qsfp1_i2c_sda_o_reg;
|
||||||
|
|
||||||
|
always_ff @(posedge clk_125mhz_int) begin
|
||||||
|
qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
|
||||||
|
qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
|
||||||
|
|
||||||
|
qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
|
||||||
|
qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_sync_signal #(
|
||||||
|
.WIDTH(8),
|
||||||
|
.N(2)
|
||||||
|
)
|
||||||
|
sync_signal_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.in({qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
|
||||||
|
qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda}),
|
||||||
|
.out({qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
|
||||||
|
qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i})
|
||||||
|
);
|
||||||
|
|
||||||
|
assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||||
|
assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||||
|
assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
// I2C
|
||||||
|
wire si5340_i2c_scl_i;
|
||||||
|
wire si5340_i2c_scl_o;
|
||||||
|
wire si5340_i2c_sda_i;
|
||||||
|
wire si5340_i2c_sda_o;
|
||||||
|
|
||||||
|
assign si5340_i2c_scl_i = si5340_i2c_scl;
|
||||||
|
assign si5340_i2c_scl = si5340_i2c_scl_o ? 1'bz : 1'b0;
|
||||||
|
assign si5340_i2c_sda_i = si5340_i2c_sda;
|
||||||
|
assign si5340_i2c_sda = si5340_i2c_sda_o ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
// wire i2c_init_scl_i = i2c_scl_i;
|
||||||
|
// wire i2c_init_scl_o;
|
||||||
|
// wire i2c_init_sda_i = i2c_sda_i;
|
||||||
|
// wire i2c_init_sda_o;
|
||||||
|
|
||||||
|
// wire i2c_int_scl_i = i2c_scl_i;
|
||||||
|
// wire i2c_int_scl_o;
|
||||||
|
// wire i2c_int_sda_i = i2c_sda_i;
|
||||||
|
// wire i2c_int_sda_o;
|
||||||
|
|
||||||
|
// assign si5340_i2c_scl_o = si5340_i2c_init_scl_o & si5340_i2c_int_scl_o;
|
||||||
|
// assign si5340_i2c_sda_o = si5340_i2c_init_sda_o & si5340_i2c_int_sda_o;
|
||||||
|
|
||||||
|
// Si5340 init
|
||||||
|
taxi_axis_if #(.DATA_W(12)) si5340_i2c_cmd();
|
||||||
|
taxi_axis_if #(.DATA_W(8)) si5340_i2c_tx();
|
||||||
|
taxi_axis_if #(.DATA_W(8)) si5340_i2c_rx();
|
||||||
|
|
||||||
|
assign si5340_i2c_rx.tready = 1'b1;
|
||||||
|
|
||||||
|
wire si5340_i2c_busy;
|
||||||
|
|
||||||
|
taxi_i2c_master
|
||||||
|
si5340_i2c_master_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Host interface
|
||||||
|
*/
|
||||||
|
.s_axis_cmd(si5340_i2c_cmd),
|
||||||
|
.s_axis_tx(si5340_i2c_tx),
|
||||||
|
.m_axis_rx(si5340_i2c_rx),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C interface
|
||||||
|
*/
|
||||||
|
.scl_i(si5340_i2c_scl_i),
|
||||||
|
.scl_o(si5340_i2c_scl_o),
|
||||||
|
.sda_i(si5340_i2c_sda_i),
|
||||||
|
.sda_o(si5340_i2c_sda_o),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.busy(),
|
||||||
|
.bus_control(),
|
||||||
|
.bus_active(),
|
||||||
|
.missed_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.prescale(SIM ? 32 : 312),
|
||||||
|
.stop_on_idle(1)
|
||||||
|
);
|
||||||
|
|
||||||
|
si5340_i2c_init #(
|
||||||
|
.SIM_SPEEDUP(SIM)
|
||||||
|
)
|
||||||
|
si5340_i2c_init_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C master interface
|
||||||
|
*/
|
||||||
|
.m_axis_cmd(si5340_i2c_cmd),
|
||||||
|
.m_axis_tx(si5340_i2c_tx),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.busy(si5340_i2c_busy),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.start(1'b1)
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam PORT_CNT = 2;
|
||||||
|
localparam GTY_QUAD_CNT = PORT_CNT;
|
||||||
|
localparam GTY_CNT = GTY_QUAD_CNT*4;
|
||||||
|
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
|
||||||
|
|
||||||
|
wire eth_gty_tx_p[GTY_CNT];
|
||||||
|
wire eth_gty_tx_n[GTY_CNT];
|
||||||
|
wire eth_gty_rx_p[GTY_CNT];
|
||||||
|
wire eth_gty_rx_n[GTY_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
|
||||||
|
|
||||||
|
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
|
||||||
|
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
|
||||||
|
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
|
||||||
|
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
|
||||||
|
|
||||||
|
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
|
||||||
|
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
|
||||||
|
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
|
||||||
|
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
|
||||||
|
|
||||||
|
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
|
||||||
|
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
|
||||||
|
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
|
||||||
|
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
|
||||||
|
|
||||||
|
fpga_core #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
.PORT_CNT(PORT_CNT),
|
||||||
|
.GTY_QUAD_CNT(GTY_QUAD_CNT),
|
||||||
|
.GTY_CNT(GTY_CNT),
|
||||||
|
.GTY_CLK_CNT(GTY_CLK_CNT),
|
||||||
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||||
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||||
|
.MAC_DATA_W(MAC_DATA_W)
|
||||||
|
)
|
||||||
|
core_inst (
|
||||||
|
/*
|
||||||
|
* Clock: 125 MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
.clk_125mhz(clk_125mhz_int),
|
||||||
|
.rst_125mhz(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
.led(led),
|
||||||
|
.qsfp_led(qsfp_led),
|
||||||
|
.led_red(led_red),
|
||||||
|
.led_green(led_green),
|
||||||
|
.led_sync(led_sync),
|
||||||
|
.eth_led_yellow(eth_led_yellow),
|
||||||
|
.eth_led_green(eth_led_green),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
.eth_gty_tx_p(eth_gty_tx_p),
|
||||||
|
.eth_gty_tx_n(eth_gty_tx_n),
|
||||||
|
.eth_gty_rx_p(eth_gty_rx_p),
|
||||||
|
.eth_gty_rx_n(eth_gty_rx_n),
|
||||||
|
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
|
||||||
|
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
|
||||||
|
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
|
||||||
|
|
||||||
|
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
|
||||||
|
.eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
|
||||||
|
.eth_port_intl({qsfp1_intl, qsfp0_intl}),
|
||||||
|
.eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode}),
|
||||||
|
|
||||||
|
.eth_port_i2c_scl_i({qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
|
||||||
|
.eth_port_i2c_scl_o({qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
|
||||||
|
.eth_port_i2c_sda_i({qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
|
||||||
|
.eth_port_i2c_sda_o({qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
412
src/eth/example/NT200A02/fpga/rtl/fpga_nt200a02.sv
Normal file
412
src/eth/example/NT200A02/fpga/rtl/fpga_nt200a02.sv
Normal file
@@ -0,0 +1,412 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA top-level module
|
||||||
|
*/
|
||||||
|
module fpga #
|
||||||
|
(
|
||||||
|
// simulation (set to avoid vendor primitives)
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
// device family
|
||||||
|
parameter string FAMILY = "virtexuplus",
|
||||||
|
// 10G/25G MAC configuration
|
||||||
|
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||||
|
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||||
|
parameter MAC_DATA_W = 64
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 50MHz
|
||||||
|
*/
|
||||||
|
input wire logic clk_50mhz,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
output wire logic [3:0] led,
|
||||||
|
output wire logic [3:0] qsfp_led[2],
|
||||||
|
output wire logic led_red,
|
||||||
|
output wire logic led_green,
|
||||||
|
output wire logic [1:0] led_sync,
|
||||||
|
output wire logic eth_led_yellow,
|
||||||
|
output wire logic eth_led_green,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C
|
||||||
|
*/
|
||||||
|
inout wire logic si5340_i2c_scl,
|
||||||
|
inout wire logic si5340_i2c_sda,
|
||||||
|
input wire logic si5340_intr,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
output wire logic qsfp0_tx_p[4],
|
||||||
|
output wire logic qsfp0_tx_n[4],
|
||||||
|
input wire logic qsfp0_rx_p[4],
|
||||||
|
input wire logic qsfp0_rx_n[4],
|
||||||
|
input wire logic qsfp0_mgt_refclk_p,
|
||||||
|
input wire logic qsfp0_mgt_refclk_n,
|
||||||
|
output wire logic qsfp0_resetl,
|
||||||
|
input wire logic qsfp0_modprsl,
|
||||||
|
input wire logic qsfp0_intl,
|
||||||
|
output wire logic qsfp0_lpmode,
|
||||||
|
inout wire logic qsfp0_i2c_scl,
|
||||||
|
inout wire logic qsfp0_i2c_sda,
|
||||||
|
|
||||||
|
output wire logic qsfp1_tx_p[4],
|
||||||
|
output wire logic qsfp1_tx_n[4],
|
||||||
|
input wire logic qsfp1_rx_p[4],
|
||||||
|
input wire logic qsfp1_rx_n[4],
|
||||||
|
input wire logic qsfp1_mgt_refclk_p,
|
||||||
|
input wire logic qsfp1_mgt_refclk_n,
|
||||||
|
output wire logic qsfp1_resetl,
|
||||||
|
input wire logic qsfp1_modprsl,
|
||||||
|
input wire logic qsfp1_intl,
|
||||||
|
output wire logic qsfp1_lpmode,
|
||||||
|
inout wire logic qsfp1_i2c_scl,
|
||||||
|
inout wire logic qsfp1_i2c_sda
|
||||||
|
);
|
||||||
|
|
||||||
|
// Clock and reset
|
||||||
|
|
||||||
|
wire clk_125mhz_mmcm_out;
|
||||||
|
|
||||||
|
// Internal 125 MHz clock
|
||||||
|
wire clk_125mhz_int;
|
||||||
|
wire rst_125mhz_int;
|
||||||
|
|
||||||
|
wire mmcm_rst = 1'b0;
|
||||||
|
wire mmcm_locked;
|
||||||
|
wire mmcm_clkfb;
|
||||||
|
|
||||||
|
// MMCM instance
|
||||||
|
MMCME4_BASE #(
|
||||||
|
// 50 MHz input
|
||||||
|
.CLKIN1_PERIOD(20.000),
|
||||||
|
.REF_JITTER1(0.010),
|
||||||
|
// 50 MHz input / 1 = 50 MHz PFD (range 10 MHz to 500 MHz)
|
||||||
|
.DIVCLK_DIVIDE(1),
|
||||||
|
// 50 MHz PFD * 20 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
|
||||||
|
.CLKFBOUT_MULT_F(20),
|
||||||
|
.CLKFBOUT_PHASE(0),
|
||||||
|
// 1000 MHz / 8 = 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0_DIVIDE_F(8),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT0_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT1_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT2_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT3_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT4_PHASE(0),
|
||||||
|
.CLKOUT4_CASCADE("FALSE"),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT5_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6_DIVIDE(1),
|
||||||
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT6_PHASE(0),
|
||||||
|
|
||||||
|
// optimized bandwidth
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
// don't wait for lock during startup
|
||||||
|
.STARTUP_WAIT("FALSE")
|
||||||
|
)
|
||||||
|
clk_mmcm_inst (
|
||||||
|
// 50 MHz input
|
||||||
|
.CLKIN1(clk_50mhz),
|
||||||
|
// direct clkfb feeback
|
||||||
|
.CLKFBIN(mmcm_clkfb),
|
||||||
|
.CLKFBOUT(mmcm_clkfb),
|
||||||
|
.CLKFBOUTB(),
|
||||||
|
// 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||||
|
.CLKOUT0B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1(),
|
||||||
|
.CLKOUT1B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2(),
|
||||||
|
.CLKOUT2B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3(),
|
||||||
|
.CLKOUT3B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6(),
|
||||||
|
// reset input
|
||||||
|
.RST(mmcm_rst),
|
||||||
|
// don't power down
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
// locked output
|
||||||
|
.LOCKED(mmcm_locked)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG
|
||||||
|
clk_125mhz_bufg_inst (
|
||||||
|
.I(clk_125mhz_mmcm_out),
|
||||||
|
.O(clk_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
sync_reset_125mhz_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(~mmcm_locked),
|
||||||
|
.out(rst_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
// GPIO
|
||||||
|
wire qsfp0_modprsl_int;
|
||||||
|
wire qsfp0_intl_int;
|
||||||
|
wire qsfp0_i2c_scl_i;
|
||||||
|
wire qsfp0_i2c_scl_o;
|
||||||
|
wire qsfp0_i2c_sda_i;
|
||||||
|
wire qsfp0_i2c_sda_o;
|
||||||
|
|
||||||
|
wire qsfp1_modprsl_int;
|
||||||
|
wire qsfp1_intl_int;
|
||||||
|
wire qsfp1_i2c_scl_i;
|
||||||
|
wire qsfp1_i2c_scl_o;
|
||||||
|
wire qsfp1_i2c_sda_i;
|
||||||
|
wire qsfp1_i2c_sda_o;
|
||||||
|
|
||||||
|
logic qsfp0_i2c_scl_o_reg;
|
||||||
|
logic qsfp0_i2c_sda_o_reg;
|
||||||
|
|
||||||
|
logic qsfp1_i2c_scl_o_reg;
|
||||||
|
logic qsfp1_i2c_sda_o_reg;
|
||||||
|
|
||||||
|
always_ff @(posedge clk_125mhz_int) begin
|
||||||
|
qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
|
||||||
|
qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
|
||||||
|
|
||||||
|
qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
|
||||||
|
qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_sync_signal #(
|
||||||
|
.WIDTH(8),
|
||||||
|
.N(2)
|
||||||
|
)
|
||||||
|
sync_signal_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.in({qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
|
||||||
|
qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda}),
|
||||||
|
.out({qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
|
||||||
|
qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i})
|
||||||
|
);
|
||||||
|
|
||||||
|
assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||||
|
assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||||
|
assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
// I2C
|
||||||
|
wire si5340_i2c_scl_i;
|
||||||
|
wire si5340_i2c_scl_o;
|
||||||
|
wire si5340_i2c_sda_i;
|
||||||
|
wire si5340_i2c_sda_o;
|
||||||
|
|
||||||
|
assign si5340_i2c_scl_i = si5340_i2c_scl;
|
||||||
|
assign si5340_i2c_scl = si5340_i2c_scl_o ? 1'bz : 1'b0;
|
||||||
|
assign si5340_i2c_sda_i = si5340_i2c_sda;
|
||||||
|
assign si5340_i2c_sda = si5340_i2c_sda_o ? 1'bz : 1'b0;
|
||||||
|
|
||||||
|
// wire i2c_init_scl_i = i2c_scl_i;
|
||||||
|
// wire i2c_init_scl_o;
|
||||||
|
// wire i2c_init_sda_i = i2c_sda_i;
|
||||||
|
// wire i2c_init_sda_o;
|
||||||
|
|
||||||
|
// wire i2c_int_scl_i = i2c_scl_i;
|
||||||
|
// wire i2c_int_scl_o;
|
||||||
|
// wire i2c_int_sda_i = i2c_sda_i;
|
||||||
|
// wire i2c_int_sda_o;
|
||||||
|
|
||||||
|
// assign si5340_i2c_scl_o = si5340_i2c_init_scl_o & si5340_i2c_int_scl_o;
|
||||||
|
// assign si5340_i2c_sda_o = si5340_i2c_init_sda_o & si5340_i2c_int_sda_o;
|
||||||
|
|
||||||
|
// Si5340 init
|
||||||
|
taxi_axis_if #(.DATA_W(12)) si5340_i2c_cmd();
|
||||||
|
taxi_axis_if #(.DATA_W(8)) si5340_i2c_tx();
|
||||||
|
taxi_axis_if #(.DATA_W(8)) si5340_i2c_rx();
|
||||||
|
|
||||||
|
assign si5340_i2c_rx.tready = 1'b1;
|
||||||
|
|
||||||
|
wire si5340_i2c_busy;
|
||||||
|
|
||||||
|
taxi_i2c_master
|
||||||
|
si5340_i2c_master_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Host interface
|
||||||
|
*/
|
||||||
|
.s_axis_cmd(si5340_i2c_cmd),
|
||||||
|
.s_axis_tx(si5340_i2c_tx),
|
||||||
|
.m_axis_rx(si5340_i2c_rx),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C interface
|
||||||
|
*/
|
||||||
|
.scl_i(si5340_i2c_scl_i),
|
||||||
|
.scl_o(si5340_i2c_scl_o),
|
||||||
|
.sda_i(si5340_i2c_sda_i),
|
||||||
|
.sda_o(si5340_i2c_sda_o),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.busy(),
|
||||||
|
.bus_control(),
|
||||||
|
.bus_active(),
|
||||||
|
.missed_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.prescale(SIM ? 32 : 312),
|
||||||
|
.stop_on_idle(1)
|
||||||
|
);
|
||||||
|
|
||||||
|
si5340_i2c_init #(
|
||||||
|
.SIM_SPEEDUP(SIM)
|
||||||
|
)
|
||||||
|
si5340_i2c_init_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C master interface
|
||||||
|
*/
|
||||||
|
.m_axis_cmd(si5340_i2c_cmd),
|
||||||
|
.m_axis_tx(si5340_i2c_tx),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.busy(si5340_i2c_busy),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.start(1'b1)
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam PORT_CNT = 2;
|
||||||
|
localparam GTY_QUAD_CNT = PORT_CNT;
|
||||||
|
localparam GTY_CNT = GTY_QUAD_CNT*4;
|
||||||
|
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
|
||||||
|
|
||||||
|
wire eth_gty_tx_p[GTY_CNT];
|
||||||
|
wire eth_gty_tx_n[GTY_CNT];
|
||||||
|
wire eth_gty_rx_p[GTY_CNT];
|
||||||
|
wire eth_gty_rx_n[GTY_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
|
||||||
|
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
|
||||||
|
|
||||||
|
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
|
||||||
|
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
|
||||||
|
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
|
||||||
|
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
|
||||||
|
|
||||||
|
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
|
||||||
|
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
|
||||||
|
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
|
||||||
|
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
|
||||||
|
|
||||||
|
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
|
||||||
|
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
|
||||||
|
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
|
||||||
|
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
|
||||||
|
|
||||||
|
fpga_core #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
.PORT_CNT(PORT_CNT),
|
||||||
|
.GTY_QUAD_CNT(GTY_QUAD_CNT),
|
||||||
|
.GTY_CNT(GTY_CNT),
|
||||||
|
.GTY_CLK_CNT(GTY_CLK_CNT),
|
||||||
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||||
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||||
|
.MAC_DATA_W(MAC_DATA_W)
|
||||||
|
)
|
||||||
|
core_inst (
|
||||||
|
/*
|
||||||
|
* Clock: 125 MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
.clk_125mhz(clk_125mhz_int),
|
||||||
|
.rst_125mhz(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
.led(led),
|
||||||
|
.qsfp_led(qsfp_led),
|
||||||
|
.led_red(led_red),
|
||||||
|
.led_green(led_green),
|
||||||
|
.led_sync(led_sync),
|
||||||
|
.eth_led_yellow(eth_led_yellow),
|
||||||
|
.eth_led_green(eth_led_green),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
.eth_gty_tx_p(eth_gty_tx_p),
|
||||||
|
.eth_gty_tx_n(eth_gty_tx_n),
|
||||||
|
.eth_gty_rx_p(eth_gty_rx_p),
|
||||||
|
.eth_gty_rx_n(eth_gty_rx_n),
|
||||||
|
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
|
||||||
|
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
|
||||||
|
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
|
||||||
|
|
||||||
|
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
|
||||||
|
.eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
|
||||||
|
.eth_port_intl({qsfp1_intl, qsfp0_intl}),
|
||||||
|
.eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode}),
|
||||||
|
|
||||||
|
.eth_port_i2c_scl_i({qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
|
||||||
|
.eth_port_i2c_scl_o({qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
|
||||||
|
.eth_port_i2c_sda_i({qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
|
||||||
|
.eth_port_i2c_sda_o({qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
62
src/eth/example/NT200A02/fpga/tb/fpga_core/Makefile
Normal file
62
src/eth/example/NT200A02/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,62 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
|
||||||
|
TOPLEVEL_LANG = verilog
|
||||||
|
|
||||||
|
SIM ?= verilator
|
||||||
|
WAVES ?= 0
|
||||||
|
|
||||||
|
COCOTB_HDL_TIMEUNIT = 1ns
|
||||||
|
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||||
|
|
||||||
|
RTL_DIR = ../../rtl
|
||||||
|
LIB_DIR = ../../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
DUT = fpga_core
|
||||||
|
COCOTB_TEST_MODULES = test_$(DUT)
|
||||||
|
COCOTB_TOPLEVEL = $(DUT)
|
||||||
|
MODULE = $(COCOTB_TEST_MODULES)
|
||||||
|
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||||
|
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
|
||||||
|
# handle file list files
|
||||||
|
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||||
|
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||||
|
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||||
|
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||||
|
|
||||||
|
# module parameters
|
||||||
|
export PARAM_SIM := "1'b1"
|
||||||
|
export PARAM_VENDOR := "\"XILINX\""
|
||||||
|
export PARAM_FAMILY := "\"virtexuplus\""
|
||||||
|
export PARAM_PORT_CNT := 2
|
||||||
|
export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
|
||||||
|
export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
|
||||||
|
export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
|
||||||
|
export PARAM_CFG_LOW_LATENCY := "1'b1"
|
||||||
|
export PARAM_COMBINED_MAC_PCS := "1'b1"
|
||||||
|
export PARAM_MAC_DATA_W := "64"
|
||||||
|
|
||||||
|
ifeq ($(SIM), icarus)
|
||||||
|
PLUSARGS += -fst
|
||||||
|
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
else ifeq ($(SIM), verilator)
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
|
||||||
|
ifeq ($(WAVES), 1)
|
||||||
|
COMPILE_ARGS += --trace-fst
|
||||||
|
VERILATOR_TRACE = 1
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||||
1
src/eth/example/NT200A02/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/eth/example/NT200A02/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../lib/taxi/src/eth/tb/baser.py
|
||||||
244
src/eth/example/NT200A02/fpga/tb/fpga_core/test_fpga_core.py
Normal file
244
src/eth/example/NT200A02/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,244 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
"""
|
||||||
|
|
||||||
|
Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
"""
|
||||||
|
|
||||||
|
import itertools
|
||||||
|
import logging
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
|
||||||
|
import pytest
|
||||||
|
import cocotb_test.simulator
|
||||||
|
|
||||||
|
import cocotb
|
||||||
|
from cocotb.clock import Clock
|
||||||
|
from cocotb.triggers import RisingEdge, Combine
|
||||||
|
|
||||||
|
from cocotbext.eth import XgmiiFrame
|
||||||
|
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
except ImportError:
|
||||||
|
# attempt import from current directory
|
||||||
|
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
finally:
|
||||||
|
del sys.path[0]
|
||||||
|
|
||||||
|
|
||||||
|
class TB:
|
||||||
|
def __init__(self, dut, speed=1000e6):
|
||||||
|
self.dut = dut
|
||||||
|
|
||||||
|
self.log = logging.getLogger("cocotb.tb")
|
||||||
|
self.log.setLevel(logging.DEBUG)
|
||||||
|
|
||||||
|
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||||
|
|
||||||
|
self.qsfp_sources = []
|
||||||
|
self.qsfp_sinks = []
|
||||||
|
|
||||||
|
for clk in dut.eth_gty_mgt_refclk_p:
|
||||||
|
cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
|
||||||
|
|
||||||
|
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
|
||||||
|
gt_inst = ch.ch_inst.gt.gt_inst
|
||||||
|
|
||||||
|
if ch.ch_inst.DATA_W.value == 64:
|
||||||
|
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||||
|
clk = 2.482
|
||||||
|
gbx_cfg = (66, [64, 65])
|
||||||
|
else:
|
||||||
|
clk = 2.56
|
||||||
|
gbx_cfg = None
|
||||||
|
else:
|
||||||
|
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||||
|
clk = 3.102
|
||||||
|
gbx_cfg = (66, [64, 65])
|
||||||
|
else:
|
||||||
|
clk = 3.2
|
||||||
|
gbx_cfg = None
|
||||||
|
|
||||||
|
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
|
||||||
|
|
||||||
|
self.qsfp_sources.append(BaseRSerdesSource(
|
||||||
|
data=gt_inst.serdes_rx_data,
|
||||||
|
data_valid=gt_inst.serdes_rx_data_valid,
|
||||||
|
hdr=gt_inst.serdes_rx_hdr,
|
||||||
|
hdr_valid=gt_inst.serdes_rx_hdr_valid,
|
||||||
|
clock=gt_inst.rx_clk,
|
||||||
|
slip=gt_inst.serdes_rx_bitslip,
|
||||||
|
reverse=True,
|
||||||
|
gbx_cfg=gbx_cfg
|
||||||
|
))
|
||||||
|
self.qsfp_sinks.append(BaseRSerdesSink(
|
||||||
|
data=gt_inst.serdes_tx_data,
|
||||||
|
data_valid=gt_inst.serdes_tx_data_valid,
|
||||||
|
hdr=gt_inst.serdes_tx_hdr,
|
||||||
|
hdr_valid=gt_inst.serdes_tx_hdr_valid,
|
||||||
|
gbx_sync=gt_inst.serdes_tx_gbx_sync,
|
||||||
|
clock=gt_inst.tx_clk,
|
||||||
|
reverse=True,
|
||||||
|
gbx_cfg=gbx_cfg
|
||||||
|
))
|
||||||
|
|
||||||
|
async def init(self):
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 1
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 0
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
|
||||||
|
async def mac_test(tb, source, sink):
|
||||||
|
tb.log.info("Test MAC")
|
||||||
|
|
||||||
|
tb.log.info("Wait for block lock")
|
||||||
|
for k in range(1200):
|
||||||
|
await RisingEdge(tb.dut.clk_125mhz)
|
||||||
|
|
||||||
|
sink.clear()
|
||||||
|
|
||||||
|
tb.log.info("Multiple small packets")
|
||||||
|
|
||||||
|
count = 64
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(XgmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
|
||||||
|
tb.log.info("Multiple large packets")
|
||||||
|
|
||||||
|
count = 32
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(XgmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
|
||||||
|
tb.log.info("MAC test done")
|
||||||
|
|
||||||
|
|
||||||
|
@cocotb.test()
|
||||||
|
async def run_test(dut):
|
||||||
|
|
||||||
|
tb = TB(dut)
|
||||||
|
|
||||||
|
await tb.init()
|
||||||
|
|
||||||
|
tests = []
|
||||||
|
|
||||||
|
tb.log.info("Start BASE-T MAC loopback test")
|
||||||
|
|
||||||
|
for k in range(len(tb.qsfp_sources)):
|
||||||
|
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||||
|
|
||||||
|
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||||
|
|
||||||
|
await Combine(*tests)
|
||||||
|
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
|
||||||
|
|
||||||
|
# cocotb-test
|
||||||
|
|
||||||
|
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||||
|
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||||
|
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||||
|
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||||
|
|
||||||
|
|
||||||
|
def process_f_files(files):
|
||||||
|
lst = {}
|
||||||
|
for f in files:
|
||||||
|
if f[-2:].lower() == '.f':
|
||||||
|
with open(f, 'r') as fp:
|
||||||
|
l = fp.read().split()
|
||||||
|
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
else:
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
return list(lst.values())
|
||||||
|
|
||||||
|
|
||||||
|
@pytest.mark.parametrize("mac_data_w", [32, 64])
|
||||||
|
def test_fpga_core(request, mac_data_w):
|
||||||
|
dut = "fpga_core"
|
||||||
|
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||||
|
toplevel = dut
|
||||||
|
|
||||||
|
verilog_sources = [
|
||||||
|
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
|
||||||
|
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
|
||||||
|
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||||
|
]
|
||||||
|
|
||||||
|
verilog_sources = process_f_files(verilog_sources)
|
||||||
|
|
||||||
|
parameters = {}
|
||||||
|
|
||||||
|
parameters['SIM'] = "1'b1"
|
||||||
|
parameters['VENDOR'] = "\"XILINX\""
|
||||||
|
parameters['FAMILY'] = "\"virtexuplus\""
|
||||||
|
parameters['PORT_CNT'] = 2
|
||||||
|
parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
|
||||||
|
parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
|
||||||
|
parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
|
||||||
|
parameters['CFG_LOW_LATENCY'] = "1'b1"
|
||||||
|
parameters['COMBINED_MAC_PCS'] = "1'b1"
|
||||||
|
parameters['MAC_DATA_W'] = mac_data_w
|
||||||
|
|
||||||
|
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||||
|
|
||||||
|
sim_build = os.path.join(tests_dir, "sim_build",
|
||||||
|
request.node.name.replace('[', '-').replace(']', ''))
|
||||||
|
|
||||||
|
cocotb_test.simulator.run(
|
||||||
|
simulator="verilator",
|
||||||
|
python_search=[tests_dir],
|
||||||
|
verilog_sources=verilog_sources,
|
||||||
|
toplevel=toplevel,
|
||||||
|
module=module,
|
||||||
|
parameters=parameters,
|
||||||
|
sim_build=sim_build,
|
||||||
|
extra_env=extra_env,
|
||||||
|
)
|
||||||
Reference in New Issue
Block a user