diff --git a/src/eth/rtl/taxi_axis_baser_rx_32.sv b/src/eth/rtl/taxi_axis_baser_rx_32.sv
new file mode 100644
index 0000000..8c7b408
--- /dev/null
+++ b/src/eth/rtl/taxi_axis_baser_rx_32.sv
@@ -0,0 +1,737 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame receiver (10GBASE-R in, AXI out)
+ */
+module taxi_axis_baser_rx_32 #
+(
+    parameter DATA_W = 32,
+    parameter HDR_W = 2,
+    parameter logic GBX_IF_EN = 1'b0,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96
+)
+(
+    input  wire logic                 clk,
+    input  wire logic                 rst,
+
+    /*
+     * 10GBASE-R encoded input
+     */
+    input  wire logic [DATA_W-1:0]    encoded_rx_data,
+    input  wire logic                 encoded_rx_data_valid,
+    input  wire logic [HDR_W-1:0]     encoded_rx_hdr,
+    input  wire logic                 encoded_rx_hdr_valid,
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    taxi_axis_if.src                  m_axis_rx,
+
+    /*
+     * PTP
+     */
+    input  wire logic [PTP_TS_W-1:0]  ptp_ts,
+
+    /*
+     * Configuration
+     */
+    input  wire logic [15:0]          cfg_rx_max_pkt_len = 16'd1518,
+    input  wire logic                 cfg_rx_enable,
+
+    /*
+     * Status
+     */
+    output wire logic                 rx_start_packet,
+    output wire logic [2:0]           stat_rx_byte,
+    output wire logic [15:0]          stat_rx_pkt_len,
+    output wire logic                 stat_rx_pkt_fragment,
+    output wire logic                 stat_rx_pkt_jabber,
+    output wire logic                 stat_rx_pkt_ucast,
+    output wire logic                 stat_rx_pkt_mcast,
+    output wire logic                 stat_rx_pkt_bcast,
+    output wire logic                 stat_rx_pkt_vlan,
+    output wire logic                 stat_rx_pkt_good,
+    output wire logic                 stat_rx_pkt_bad,
+    output wire logic                 stat_rx_err_oversize,
+    output wire logic                 stat_rx_err_bad_fcs,
+    output wire logic                 stat_rx_err_bad_block,
+    output wire logic                 stat_rx_err_framing,
+    output wire logic                 stat_rx_err_preamble
+);
+
+// extract parameters
+localparam KEEP_W = DATA_W/8;
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+// check configuration
+if (DATA_W != 32)
+    $fatal(0, "Error: Interface width must be 32 (instance %m)");
+
+if (KEEP_W*8 != DATA_W)
+    $fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
+
+if (HDR_W != 2)
+    $fatal(0, "Error: HDR_W must be 2 (instance %m)");
+
+if (m_axis_rx.DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axis_rx.USER_W != USER_W)
+    $fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
+
+localparam [7:0]
+    ETH_PRE = 8'h55,
+    ETH_SFD = 8'hD5;
+
+localparam [6:0]
+    CTRL_IDLE  = 7'h00,
+    CTRL_LPI   = 7'h06,
+    CTRL_ERROR = 7'h1e,
+    CTRL_RES_0 = 7'h2d,
+    CTRL_RES_1 = 7'h33,
+    CTRL_RES_2 = 7'h4b,
+    CTRL_RES_3 = 7'h55,
+    CTRL_RES_4 = 7'h66,
+    CTRL_RES_5 = 7'h78;
+
+localparam [3:0]
+    O_SEQ_OS = 4'h0,
+    O_SIG_OS = 4'hf;
+
+localparam [1:0]
+    SYNC_DATA = 2'b10,
+    SYNC_CTRL = 2'b01;
+
+localparam [7:0]
+    BLOCK_TYPE_CTRL     = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
+    BLOCK_TYPE_OS_4     = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
+    BLOCK_TYPE_START_4  = 8'h33, // D7 D6 D5    C3 C2 C1 C0 BT
+    BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5    O0 D3 D2 D1 BT
+    BLOCK_TYPE_OS_04    = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
+    BLOCK_TYPE_START_0  = 8'h78, // D7 D6 D5 D4 D3 D2 D1    BT
+    BLOCK_TYPE_OS_0     = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
+    BLOCK_TYPE_TERM_0   = 8'h87, // C7 C6 C5 C4 C3 C2 C1    BT
+    BLOCK_TYPE_TERM_1   = 8'h99, // C7 C6 C5 C4 C3 C2    D0 BT
+    BLOCK_TYPE_TERM_2   = 8'haa, // C7 C6 C5 C4 C3    D1 D0 BT
+    BLOCK_TYPE_TERM_3   = 8'hb4, // C7 C6 C5 C4    D2 D1 D0 BT
+    BLOCK_TYPE_TERM_4   = 8'hcc, // C7 C6 C5    D3 D2 D1 D0 BT
+    BLOCK_TYPE_TERM_5   = 8'hd2, // C7 C6    D4 D3 D2 D1 D0 BT
+    BLOCK_TYPE_TERM_6   = 8'he1, // C7    D5 D4 D3 D2 D1 D0 BT
+    BLOCK_TYPE_TERM_7   = 8'hff; //    D6 D5 D4 D3 D2 D1 D0 BT
+
+localparam [2:0]
+    INPUT_TYPE_IDLE = 3'd0,
+    INPUT_TYPE_ERROR = 3'd1,
+    INPUT_TYPE_START = 3'd2,
+    INPUT_TYPE_DATA = 3'd3,
+    INPUT_TYPE_TERM_0 = 3'd4,
+    INPUT_TYPE_TERM_1 = 3'd5,
+    INPUT_TYPE_TERM_2 = 3'd6,
+    INPUT_TYPE_TERM_3 = 3'd7;
+
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_PREAMBLE = 2'd1,
+    STATE_PAYLOAD = 2'd2,
+    STATE_LAST = 2'd3;
+
+logic [1:0] state_reg = STATE_IDLE, state_next;
+
+// datapath control signals
+logic reset_crc;
+
+logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
+logic term_present_reg = 1'b0;
+logic framing_error_reg = 1'b0;
+
+logic [DATA_W-1:0] input_data_d0 = '0;
+logic [DATA_W-1:0] input_data_d1 = '0;
+logic [DATA_W-1:0] input_data_d2 = '0;
+
+logic [2:0] input_type_alt = INPUT_TYPE_IDLE;
+logic [2:0] input_type_d0 = INPUT_TYPE_IDLE;
+logic [2:0] input_type_d1 = INPUT_TYPE_IDLE;
+logic [2:0] input_type_d2 = INPUT_TYPE_IDLE;
+
+logic [DATA_W-1:0] encoded_rx_data_reg = '0;
+logic encoded_rx_data_valid_reg = 1'b0;
+logic [HDR_W-1:0] encoded_rx_hdr_reg = '0;
+logic encoded_rx_hdr_valid_reg = 1'b0;
+
+logic frame_oversize_reg = 1'b0, frame_oversize_next;
+logic pre_ok_reg = 1'b0, pre_ok_next;
+logic [2:0] hdr_ptr_reg = '0, hdr_ptr_next;
+logic is_mcast_reg = 1'b0, is_mcast_next;
+logic is_bcast_reg = 1'b0, is_bcast_next;
+logic is_8021q_reg = 1'b0, is_8021q_next;
+logic [15:0] frame_len_reg = '0, frame_len_next;
+logic [15:0] frame_len_lim_reg = '0, frame_len_lim_next;
+
+logic [DATA_W-1:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next;
+logic [KEEP_W-1:0] m_axis_rx_tkeep_reg = '0, m_axis_rx_tkeep_next;
+logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
+logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
+logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
+
+logic start_packet_reg = 1'b0, start_packet_next;
+
+logic [2:0] stat_rx_byte_reg = '0, stat_rx_byte_next;
+logic [15:0] stat_rx_pkt_len_reg = '0, stat_rx_pkt_len_next;
+logic stat_rx_pkt_fragment_reg = 1'b0, stat_rx_pkt_fragment_next;
+logic stat_rx_pkt_jabber_reg = 1'b0, stat_rx_pkt_jabber_next;
+logic stat_rx_pkt_ucast_reg = 1'b0, stat_rx_pkt_ucast_next;
+logic stat_rx_pkt_mcast_reg = 1'b0, stat_rx_pkt_mcast_next;
+logic stat_rx_pkt_bcast_reg = 1'b0, stat_rx_pkt_bcast_next;
+logic stat_rx_pkt_vlan_reg = 1'b0, stat_rx_pkt_vlan_next;
+logic stat_rx_pkt_good_reg = 1'b0, stat_rx_pkt_good_next;
+logic stat_rx_pkt_bad_reg = 1'b0, stat_rx_pkt_bad_next;
+logic stat_rx_err_oversize_reg = 1'b0, stat_rx_err_oversize_next;
+logic stat_rx_err_bad_fcs_reg = 1'b0, stat_rx_err_bad_fcs_next;
+logic stat_rx_err_bad_block_reg = 1'b0, stat_rx_err_bad_block_next;
+logic stat_rx_err_framing_reg = 1'b0, stat_rx_err_framing_next;
+logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next;
+
+logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
+
+logic [31:0] crc_state = '1;
+
+wire [31:0] crc_next;
+
+wire [3:0] crc_valid;
+logic [3:0] crc_valid_save;
+
+assign crc_valid[3] = crc_next == ~32'h2144df1c;
+assign crc_valid[2] = crc_next == ~32'hc622f71d;
+assign crc_valid[1] = crc_next == ~32'hb1c2a1a3;
+assign crc_valid[0] = crc_next == ~32'h9d6cdf7e;
+
+assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
+assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg;
+assign m_axis_rx.tstrb = m_axis_rx.tkeep;
+assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg;
+assign m_axis_rx.tlast = m_axis_rx_tlast_reg;
+assign m_axis_rx.tid = '0;
+assign m_axis_rx.tdest = '0;
+assign m_axis_rx.tuser[0] = m_axis_rx_tuser_reg;
+if (PTP_TS_EN) begin
+    assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg;
+end
+
+assign rx_start_packet = start_packet_reg;
+
+assign stat_rx_byte = stat_rx_byte_reg;
+assign stat_rx_pkt_len = stat_rx_pkt_len_reg;
+assign stat_rx_pkt_fragment = stat_rx_pkt_fragment_reg;
+assign stat_rx_pkt_jabber = stat_rx_pkt_jabber_reg;
+assign stat_rx_pkt_ucast = stat_rx_pkt_ucast_reg;
+assign stat_rx_pkt_mcast = stat_rx_pkt_mcast_reg;
+assign stat_rx_pkt_bcast = stat_rx_pkt_bcast_reg;
+assign stat_rx_pkt_vlan = stat_rx_pkt_vlan_reg;
+assign stat_rx_pkt_good = stat_rx_pkt_good_reg;
+assign stat_rx_pkt_bad = stat_rx_pkt_bad_reg;
+assign stat_rx_err_oversize = stat_rx_err_oversize_reg;
+assign stat_rx_err_bad_fcs = stat_rx_err_bad_fcs_reg;
+assign stat_rx_err_bad_block = stat_rx_err_bad_block_reg;
+assign stat_rx_err_framing = stat_rx_err_framing_reg;
+assign stat_rx_err_preamble = stat_rx_err_preamble_reg;
+
+wire last_cycle = state_reg == STATE_LAST;
+
+taxi_lfsr #(
+    .LFSR_W(32),
+    .LFSR_POLY(32'h4c11db7),
+    .LFSR_GALOIS(1),
+    .LFSR_FEED_FORWARD(0),
+    .REVERSE(1),
+    .DATA_W(DATA_W),
+    .DATA_IN_EN(1'b1),
+    .DATA_OUT_EN(1'b0)
+)
+eth_crc (
+    .data_in(input_data_d0),
+    .state_in(crc_state),
+    .data_out(),
+    .state_out(crc_next)
+);
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    reset_crc = 1'b0;
+
+    frame_oversize_next = frame_oversize_reg;
+    pre_ok_next = pre_ok_reg;
+    hdr_ptr_next = hdr_ptr_reg;
+    is_mcast_next = is_mcast_reg;
+    is_bcast_next = is_bcast_reg;
+    is_8021q_next = is_8021q_reg;
+    frame_len_next = frame_len_reg;
+    frame_len_lim_next = frame_len_lim_reg;
+
+    m_axis_rx_tdata_next = input_data_d2;
+    m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
+    m_axis_rx_tvalid_next = 1'b0;
+    m_axis_rx_tlast_next = 1'b0;
+    m_axis_rx_tuser_next = 1'b0;
+
+    ptp_ts_out_next = ptp_ts_out_reg;
+
+    start_packet_next = 1'b0;
+
+    stat_rx_byte_next = '0;
+    stat_rx_pkt_len_next = '0;
+    stat_rx_pkt_fragment_next = 1'b0;
+    stat_rx_pkt_jabber_next = 1'b0;
+    stat_rx_pkt_ucast_next = 1'b0;
+    stat_rx_pkt_mcast_next = 1'b0;
+    stat_rx_pkt_bcast_next = 1'b0;
+    stat_rx_pkt_vlan_next = 1'b0;
+    stat_rx_pkt_good_next = 1'b0;
+    stat_rx_pkt_bad_next = 1'b0;
+    stat_rx_err_oversize_next = 1'b0;
+    stat_rx_err_bad_fcs_next = 1'b0;
+    stat_rx_err_bad_block_next = 1'b0;
+    stat_rx_err_framing_next = 1'b0;
+    stat_rx_err_preamble_next = 1'b0;
+
+    if (GBX_IF_EN && !encoded_rx_data_valid) begin
+        // data from gearbox not valid - hold state
+        state_next = state_reg;
+    end else begin
+        // counter to measure frame length
+        if (&frame_len_reg[15:2] == 0) begin
+            if (input_type_d0[2]) begin
+                frame_len_next = frame_len_reg + 16'(input_type_d0[1:0]);
+            end else begin
+                frame_len_next = frame_len_reg + 16'(KEEP_W);
+            end
+        end else begin
+            frame_len_next = '1;
+        end
+
+        // counter for max frame length enforcement
+        if (frame_len_lim_reg[15:2] != 0) begin
+            frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
+        end else begin
+            frame_len_lim_next = '0;
+        end
+
+        // address and ethertype checks
+        if (&hdr_ptr_reg == 0) begin
+            hdr_ptr_next = hdr_ptr_reg + 1;
+        end
+
+        case (hdr_ptr_reg)
+            3'd0: begin
+                is_mcast_next = input_data_d2[0];
+                is_bcast_next = &input_data_d2;
+            end
+            3'd1: is_bcast_next = is_bcast_reg && &input_data_d2[15:0];
+            3'd3: is_8021q_next = {input_data_d2[7:0], input_data_d2[15:8]} == 16'h8100;
+            default: begin
+                // do nothing
+            end
+        endcase
+
+        case (state_reg)
+            STATE_IDLE: begin
+                // idle state - wait for packet
+                reset_crc = 1'b1;
+
+                frame_len_next = 16'(KEEP_W);
+                frame_len_lim_next = cfg_rx_max_pkt_len;
+                hdr_ptr_next = 0;
+
+                pre_ok_next = input_data_d2[31:8] == 24'h555555;
+
+                if (input_type_d2 == INPUT_TYPE_START && cfg_rx_enable) begin
+                    // start condition
+                    if (framing_error_reg) begin
+                        // control or error characters in first data word
+                        stat_rx_err_framing_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        reset_crc = 1'b0;
+                        stat_rx_byte_next = 3'(KEEP_W);
+                        state_next = STATE_PREAMBLE;
+                    end
+                end else begin
+                    if (PTP_TS_EN) begin
+                        ptp_ts_out_next = ptp_ts;
+                    end
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_PREAMBLE: begin
+                // drop preamble
+
+                frame_len_lim_next = cfg_rx_max_pkt_len;
+                hdr_ptr_next = 0;
+
+                pre_ok_next = pre_ok_reg && input_data_d2 == 32'hD5555555;
+
+                if (framing_error_reg) begin
+                    // control or error characters in packet
+                    stat_rx_err_framing_next = 1'b1;
+                    state_next = STATE_IDLE;
+                end else begin
+                    start_packet_next = 1'b1;
+                    stat_rx_byte_next = 3'(KEEP_W);
+                    state_next = STATE_PAYLOAD;
+                end
+            end
+            STATE_PAYLOAD: begin
+                // read payload
+                m_axis_rx_tdata_next = input_data_d2;
+                m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
+                m_axis_rx_tvalid_next = 1'b1;
+                m_axis_rx_tlast_next = 1'b0;
+                m_axis_rx_tuser_next = 1'b0;
+
+                if (input_type_d0[2]) begin
+                    stat_rx_byte_next = 3'(input_type_d0[1:0]);
+                    frame_oversize_next = frame_len_lim_reg < 16'(4+4+input_type_d0[1:0]);
+                end else begin
+                    stat_rx_byte_next = 3'(KEEP_W);
+                    frame_oversize_next = frame_len_lim_reg < 4+4;
+                end
+
+                if (framing_error_reg) begin
+                    // control or error characters in packet
+                    m_axis_rx_tlast_next = 1'b1;
+                    m_axis_rx_tuser_next = 1'b1;
+                    stat_rx_pkt_bad_next = 1'b1;
+                    stat_rx_pkt_len_next = frame_len_next;
+                    stat_rx_pkt_ucast_next = !is_mcast_reg;
+                    stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
+                    stat_rx_pkt_bcast_next = is_bcast_reg;
+                    stat_rx_pkt_vlan_next = is_8021q_reg;
+                    stat_rx_err_oversize_next = frame_oversize_next;
+                    stat_rx_err_framing_next = 1'b1;
+                    stat_rx_err_preamble_next = !pre_ok_reg;
+                    stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
+                    stat_rx_pkt_jabber_next = frame_oversize_next;
+                    reset_crc = 1'b1;
+                    state_next = STATE_IDLE;
+                end else if (input_type_d0[2]) begin
+                    reset_crc = 1'b1;
+                    if (input_type_d0[1:0] == 0) begin
+                        // end this cycle
+                        m_axis_rx_tkeep_next = 4'b1111;
+                        m_axis_rx_tlast_next = 1'b1;
+                        if (input_type_d0[1:0] == 0 && crc_valid_save[3]) begin
+                            // CRC valid
+                            if (frame_oversize_next) begin
+                                // too long
+                                m_axis_rx_tuser_next = 1'b1;
+                                stat_rx_pkt_bad_next = 1'b1;
+                            end else begin
+                                // length OK
+                                m_axis_rx_tuser_next = 1'b0;
+                                stat_rx_pkt_good_next = 1'b1;
+                            end
+                        end else begin
+                            m_axis_rx_tuser_next = 1'b1;
+                            stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
+                            stat_rx_pkt_jabber_next = frame_oversize_next;
+                            stat_rx_pkt_bad_next = 1'b1;
+                            stat_rx_err_bad_fcs_next = 1'b1;
+                        end
+                        stat_rx_pkt_len_next = frame_len_next;
+                        stat_rx_pkt_ucast_next = !is_mcast_reg;
+                        stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
+                        stat_rx_pkt_bcast_next = is_bcast_reg;
+                        stat_rx_pkt_vlan_next = is_8021q_reg;
+                        stat_rx_err_oversize_next = frame_oversize_next;
+                        stat_rx_err_preamble_next = !pre_ok_reg;
+                        state_next = STATE_IDLE;
+                    end else begin
+                        // need extra cycle
+                        state_next = STATE_LAST;
+                    end
+                end else begin
+                    state_next = STATE_PAYLOAD;
+                end
+            end
+            STATE_LAST: begin
+                // last cycle of packet
+                m_axis_rx_tdata_next = input_data_d2;
+                m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 2'(KEEP_W-input_type_d1[1:0]);
+                m_axis_rx_tvalid_next = 1'b1;
+                m_axis_rx_tlast_next = 1'b1;
+                m_axis_rx_tuser_next = 1'b0;
+
+                reset_crc = 1'b1;
+
+                if ((input_type_d1[1:0] == 1 && crc_valid_save[0]) ||
+                    (input_type_d1[1:0] == 2 && crc_valid_save[1]) ||
+                    (input_type_d1[1:0] == 3 && crc_valid_save[2])) begin
+                    // CRC valid
+                    if (frame_oversize_reg) begin
+                        // too long
+                        m_axis_rx_tuser_next = 1'b1;
+                        stat_rx_pkt_bad_next = 1'b1;
+                    end else begin
+                        // length OK
+                        m_axis_rx_tuser_next = 1'b0;
+                        stat_rx_pkt_good_next = 1'b1;
+                    end
+                end else begin
+                    m_axis_rx_tuser_next = 1'b1;
+                    stat_rx_pkt_fragment_next = frame_len_reg[15:6] == 0;
+                    stat_rx_pkt_jabber_next = frame_oversize_reg;
+                    stat_rx_pkt_bad_next = 1'b1;
+                    stat_rx_err_bad_fcs_next = 1'b1;
+                end
+
+                stat_rx_pkt_len_next = frame_len_reg;
+                stat_rx_pkt_ucast_next = !is_mcast_reg;
+                stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
+                stat_rx_pkt_bcast_next = is_bcast_reg;
+                stat_rx_pkt_vlan_next = is_8021q_reg;
+                stat_rx_err_oversize_next = frame_oversize_reg;
+                stat_rx_err_preamble_next = !pre_ok_reg;
+
+                state_next = STATE_IDLE;
+            end
+            default: begin
+                // invalid state, return to idle
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    frame_oversize_reg <= frame_oversize_next;
+    pre_ok_reg <= pre_ok_next;
+    hdr_ptr_reg <= hdr_ptr_next;
+    is_mcast_reg <= is_mcast_next;
+    is_bcast_reg <= is_bcast_next;
+    is_8021q_reg <= is_8021q_next;
+    frame_len_reg <= frame_len_next;
+    frame_len_lim_reg <= frame_len_lim_next;
+
+    m_axis_rx_tdata_reg <= m_axis_rx_tdata_next;
+    m_axis_rx_tkeep_reg <= m_axis_rx_tkeep_next;
+    m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next;
+    m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
+    m_axis_rx_tuser_reg <= m_axis_rx_tuser_next;
+
+    ptp_ts_out_reg <= ptp_ts_out_next;
+
+    start_packet_reg <= start_packet_next;
+
+    stat_rx_byte_reg <= stat_rx_byte_next;
+    stat_rx_pkt_len_reg <= stat_rx_pkt_len_next;
+    stat_rx_pkt_fragment_reg <= stat_rx_pkt_fragment_next;
+    stat_rx_pkt_jabber_reg <= stat_rx_pkt_jabber_next;
+    stat_rx_pkt_ucast_reg <= stat_rx_pkt_ucast_next;
+    stat_rx_pkt_mcast_reg <= stat_rx_pkt_mcast_next;
+    stat_rx_pkt_bcast_reg <= stat_rx_pkt_bcast_next;
+    stat_rx_pkt_vlan_reg <= stat_rx_pkt_vlan_next;
+    stat_rx_pkt_good_reg <= stat_rx_pkt_good_next;
+    stat_rx_pkt_bad_reg <= stat_rx_pkt_bad_next;
+    stat_rx_err_oversize_reg <= stat_rx_err_oversize_next;
+    stat_rx_err_bad_fcs_reg <= stat_rx_err_bad_fcs_next;
+    stat_rx_err_bad_block_reg <= stat_rx_err_bad_block_next;
+    stat_rx_err_framing_reg <= stat_rx_err_framing_next;
+    stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
+
+    if (!GBX_IF_EN || encoded_rx_data_valid) begin
+        encoded_rx_data_reg <= encoded_rx_data;
+        encoded_rx_data_valid_reg <= encoded_rx_data_valid;
+        encoded_rx_hdr_reg <= encoded_rx_hdr;
+        encoded_rx_hdr_valid_reg <= encoded_rx_hdr_valid;
+
+        input_data_d0 <= encoded_rx_data_reg;
+        input_data_d1 <= input_data_d0;
+        input_data_d2 <= input_data_d1;
+
+        input_type_alt <= INPUT_TYPE_IDLE;
+        input_type_d0 <= input_type_alt;
+        input_type_d1 <= input_type_d0;
+        input_type_d2 <= input_type_d1;
+
+        if (encoded_rx_hdr_valid_reg) begin
+            // portion with header
+            if (encoded_rx_hdr_reg[0] == 0) begin
+                // data
+                input_data_d0 <= encoded_rx_data_reg;
+                input_type_d0 <= INPUT_TYPE_DATA;
+                input_type_alt <= INPUT_TYPE_DATA;
+            end else begin
+                // control
+                case (encoded_rx_data_reg[7:4])
+                    BLOCK_TYPE_CTRL[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_OS_4[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_START_4[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_START;
+                    end
+                    BLOCK_TYPE_OS_START[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_START;
+                    end
+                    BLOCK_TYPE_OS_04[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_START_0[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_START;
+                        input_type_alt <= INPUT_TYPE_DATA;
+                    end
+                    BLOCK_TYPE_OS_0[7:4]: begin
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_IDLE;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_TERM_0[7:4]: begin
+                        input_data_d0 <= 32'd0;
+                        input_type_d0 <= INPUT_TYPE_TERM_0;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_TERM_1[7:4]: begin
+                        input_data_d0 <= {24'd0, encoded_rx_data_reg[15:8]};
+                        input_type_d0 <= INPUT_TYPE_TERM_1;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_TERM_2[7:4]: begin
+                        input_data_d0 <= {16'd0, encoded_rx_data_reg[23:8]};
+                        input_type_d0 <= INPUT_TYPE_TERM_2;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_TERM_3[7:4]: begin
+                        input_data_d0 <= {8'd0, encoded_rx_data_reg[31:8]};
+                        input_type_d0 <= INPUT_TYPE_TERM_3;
+                        input_type_alt <= INPUT_TYPE_IDLE;
+                    end
+                    BLOCK_TYPE_TERM_4[7:4]: begin
+                        input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
+                        input_type_d0 <= INPUT_TYPE_DATA;
+                        input_type_alt <= INPUT_TYPE_TERM_0;
+                    end
+                    BLOCK_TYPE_TERM_5[7:4]: begin
+                        input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
+                        input_type_d0 <= INPUT_TYPE_DATA;
+                        input_type_alt <= INPUT_TYPE_TERM_1;
+                    end
+                    BLOCK_TYPE_TERM_6[7:4]: begin
+                        input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
+                        input_type_d0 <= INPUT_TYPE_DATA;
+                        input_type_alt <= INPUT_TYPE_TERM_2;
+                    end
+                    BLOCK_TYPE_TERM_7[7:4]: begin
+                        input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
+                        input_type_d0 <= INPUT_TYPE_DATA;
+                        input_type_alt <= INPUT_TYPE_TERM_3;
+                    end
+                    default: begin
+                        // invalid block type
+                        input_data_d0 <= encoded_rx_data_reg;
+                        input_type_d0 <= INPUT_TYPE_ERROR;
+                        input_type_alt <= INPUT_TYPE_ERROR;
+                    end
+                endcase
+            end
+        end else begin
+            case (input_type_alt)
+                INPUT_TYPE_IDLE: begin
+                    input_data_d0 <= encoded_rx_data_reg;
+                end
+                INPUT_TYPE_ERROR: begin
+                    input_data_d0 <= encoded_rx_data_reg;
+                end
+                INPUT_TYPE_START: begin
+                    input_data_d0 <= encoded_rx_data_reg;
+                end
+                INPUT_TYPE_DATA: begin
+                    input_data_d0 <= encoded_rx_data_reg;
+                end
+                INPUT_TYPE_TERM_0: begin
+                    input_data_d0 <= 32'd0;
+                end
+                INPUT_TYPE_TERM_1: begin
+                    input_data_d0 <= {24'd0, encoded_rx_data_reg[15:8]};
+                end
+                INPUT_TYPE_TERM_2: begin
+                    input_data_d0 <= {16'd0, encoded_rx_data_reg[23:8]};
+                end
+                INPUT_TYPE_TERM_3: begin
+                    input_data_d0 <= {8'd0, encoded_rx_data_reg[31:8]};
+                end
+                default: begin
+                    input_data_d0 <= encoded_rx_data_reg;
+                end
+            endcase
+        end
+
+        if (reset_crc) begin
+            crc_state <= '1;
+        end else begin
+            crc_state <= crc_next;
+        end
+
+        crc_valid_save <= crc_valid;
+    end
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        m_axis_rx_tvalid_reg <= 1'b0;
+
+        start_packet_reg <= 1'b0;
+
+        stat_rx_byte_reg <= '0;
+        stat_rx_pkt_len_reg <= '0;
+        stat_rx_pkt_fragment_reg <= 1'b0;
+        stat_rx_pkt_jabber_reg <= 1'b0;
+        stat_rx_pkt_ucast_reg <= 1'b0;
+        stat_rx_pkt_mcast_reg <= 1'b0;
+        stat_rx_pkt_bcast_reg <= 1'b0;
+        stat_rx_pkt_vlan_reg <= 1'b0;
+        stat_rx_pkt_good_reg <= 1'b0;
+        stat_rx_pkt_bad_reg <= 1'b0;
+        stat_rx_err_oversize_reg <= 1'b0;
+        stat_rx_err_bad_fcs_reg <= 1'b0;
+        stat_rx_err_bad_block_reg <= 1'b0;
+        stat_rx_err_framing_reg <= 1'b0;
+        stat_rx_err_preamble_reg <= 1'b0;
+
+        input_type_alt <= INPUT_TYPE_IDLE;
+        input_type_d0 <= INPUT_TYPE_IDLE;
+        input_type_d1 <= INPUT_TYPE_IDLE;
+        input_type_d2 <= INPUT_TYPE_IDLE;
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/src/eth/tb/taxi_axis_baser_rx_32/Makefile b/src/eth/tb/taxi_axis_baser_rx_32/Makefile
new file mode 100644
index 0000000..051a8fa
--- /dev/null
+++ b/src/eth/tb/taxi_axis_baser_rx_32/Makefile
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_baser_rx_32
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_HDR_W := 2
+export PARAM_GBX_IF_EN := 1
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/src/eth/tb/taxi_axis_baser_rx_32/baser.py b/src/eth/tb/taxi_axis_baser_rx_32/baser.py
new file mode 120000
index 0000000..33a2368
--- /dev/null
+++ b/src/eth/tb/taxi_axis_baser_rx_32/baser.py
@@ -0,0 +1 @@
+../baser.py
\ No newline at end of file
diff --git a/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.py b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.py
new file mode 100644
index 0000000..34fa021
--- /dev/null
+++ b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.py
@@ -0,0 +1,364 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+try:
+    from baser import BaseRSerdesSource
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut, gbx_cfg=None):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if gbx_cfg:
+            self.clk_period = 3.102
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.clk, self.clk_period, units="ns").start())
+
+        self.source = BaseRSerdesSource(
+            data=dut.encoded_rx_data,
+            data_valid=dut.encoded_rx_data_valid,
+            hdr=dut.encoded_rx_hdr,
+            hdr_valid=dut.encoded_rx_hdr_valid,
+            clock=dut.clk,
+            scramble=False,
+            gbx_cfg=gbx_cfg
+        )
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_rx_byte"] = 0
+        self.stats["stat_rx_pkt_len"] = 0
+        self.stats["stat_rx_pkt_fragment"] = 0
+        self.stats["stat_rx_pkt_jabber"] = 0
+        self.stats["stat_rx_pkt_ucast"] = 0
+        self.stats["stat_rx_pkt_mcast"] = 0
+        self.stats["stat_rx_pkt_bcast"] = 0
+        self.stats["stat_rx_pkt_vlan"] = 0
+        self.stats["stat_rx_pkt_good"] = 0
+        self.stats["stat_rx_pkt_bad"] = 0
+        self.stats["stat_rx_err_oversize"] = 0
+        self.stats["stat_rx_err_bad_fcs"] = 0
+        self.stats["stat_rx_err_bad_block"] = 0
+        self.stats["stat_rx_err_framing"] = 0
+        self.stats["stat_rx_err_preamble"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        if gbx_cfg is None:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*3) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_rx_byte"] == total_bytes
+    assert tb.stats["stat_rx_pkt_len"] == total_bytes
+    assert tb.stats["stat_rx_pkt_fragment"] == 0
+    assert tb.stats["stat_rx_pkt_jabber"] == 0
+    assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_rx_pkt_mcast"] == 0
+    assert tb.stats["stat_rx_pkt_bcast"] == 0
+    assert tb.stats["stat_rx_pkt_vlan"] == 0
+    assert tb.stats["stat_rx_pkt_good"] == total_pkts
+    assert tb.stats["stat_rx_pkt_bad"] == 0
+    assert tb.stats["stat_rx_err_oversize"] == 0
+    assert tb.stats["stat_rx_err_bad_fcs"] == 0
+    assert tb.stats["stat_rx_err_bad_block"] == 0
+    assert tb.stats["stat_rx_err_framing"] == 0
+    assert tb.stats["stat_rx_err_preamble"] == 0
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_rx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = XgmiiFrame.from_payload(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        frame_error = rx_frame.tuser[-1] & 1
+                        assert frame_error
+                    else:
+                        frame_error = rx_frame.tuser & 1
+                        assert rx_frame.tdata == test_data_2
+                        assert frame_error == 0
+                else:
+                    frame_error = rx_frame.tuser & 1
+                    assert rx_frame.tdata == test_data_1
+                    assert frame_error == 0
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_rx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_fragment"] == 0
+        assert tb.stats["stat_rx_pkt_jabber"] == 0
+        assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_rx_pkt_mcast"] == 0
+        assert tb.stats["stat_rx_pkt_bcast"] == 0
+        assert tb.stats["stat_rx_pkt_vlan"] == 0
+        assert tb.stats["stat_rx_pkt_good"] == total_pkts-oversz_pkts
+        assert tb.stats["stat_rx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_rx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_rx_err_bad_fcs"] == 0
+        assert tb.stats["stat_rx_err_bad_block"] == 0
+        assert tb.stats["stat_rx_err_framing"] == 0
+        assert tb.stats["stat_rx_err_preamble"] == 0
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    gbx_cfgs = [None]
+
+    if cocotb.top.GBX_IF_EN.value:
+        gbx_cfgs.append((33, [32]))
+        gbx_cfgs.append((66, [64, 65]))
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.add_option("gbx_cfg", gbx_cfgs)
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_oversize)
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.add_option("gbx_cfg", gbx_cfgs)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("gbx_en", [1, 0])
+def test_taxi_axis_baser_rx_32(request, gbx_en):
+    dut = "taxi_axis_baser_rx_32"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 32
+    parameters['HDR_W'] = 2
+    parameters['GBX_IF_EN'] = gbx_en
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
diff --git a/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv
new file mode 100644
index 0000000..dd6a558
--- /dev/null
+++ b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame receiver testbench
+ */
+module test_taxi_axis_baser_rx_32 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter HDR_W = 2,
+    parameter logic GBX_IF_EN = 1'b0,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] encoded_rx_data;
+logic encoded_rx_data_valid;
+logic [HDR_W-1:0] encoded_rx_hdr;
+logic encoded_rx_hdr_valid;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+logic rx_start_packet;
+logic [2:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+
+taxi_axis_baser_rx_32 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .GBX_IF_EN(GBX_IF_EN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded input
+     */
+    .encoded_rx_data(encoded_rx_data),
+    .encoded_rx_data_valid(encoded_rx_data_valid),
+    .encoded_rx_hdr(encoded_rx_hdr),
+    .encoded_rx_hdr_valid(encoded_rx_hdr_valid),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble)
+);
+
+endmodule
+
+`resetall