From 2bb2710bbdb392c96652c6884fda534d25838b57 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 8 Mar 2026 17:38:04 -0700 Subject: [PATCH] pcie: Add IRQ rate limit module and testbench Signed-off-by: Alex Forencich --- src/pcie/rtl/taxi_irq_rate_limit.sv | 253 ++++++++++++++++++ src/pcie/tb/taxi_irq_rate_limit/Makefile | 51 ++++ .../test_taxi_irq_rate_limit.py | 193 +++++++++++++ .../test_taxi_irq_rate_limit.sv | 62 +++++ 4 files changed, 559 insertions(+) create mode 100644 src/pcie/rtl/taxi_irq_rate_limit.sv create mode 100644 src/pcie/tb/taxi_irq_rate_limit/Makefile create mode 100644 src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py create mode 100644 src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.sv diff --git a/src/pcie/rtl/taxi_irq_rate_limit.sv b/src/pcie/rtl/taxi_irq_rate_limit.sv new file mode 100644 index 0000000..f494214 --- /dev/null +++ b/src/pcie/rtl/taxi_irq_rate_limit.sv @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2022-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * IRQ rate limit module + */ +module taxi_irq_rate_limit +( + input wire logic clk, + input wire logic rst, + + /* + * Interrupt request input + */ + taxi_axis_if.snk s_axis_irq, + + /* + * Interrupt request output + */ + taxi_axis_if.src m_axis_irq, + + /* + * Configuration + */ + input wire logic [15:0] prescale, + input wire logic [15:0] min_interval +); + +localparam IRQN_W = s_axis_irq.DATA_W; + +localparam TSTAMP_W = 17; + +// check configuration +if (m_axis_irq.DATA_W != IRQN_W) + $fatal(0, "Error: AXI stream width mismatch (instance %m)"); + +typedef enum logic [1:0] { + STATE_INIT, + STATE_IDLE, + STATE_IRQ_IN, + STATE_IRQ_OUT +} state_t; + +state_t state_reg = STATE_INIT, state_next; + +logic [IRQN_W-1:0] cur_index_reg = '0, cur_index_next; +logic [IRQN_W-1:0] irqn_reg = '0, irqn_next; + +localparam MEM_W = TSTAMP_W+1+1; + +logic mem_rd_en; +logic mem_wr_en; +logic [IRQN_W-1:0] mem_addr; +logic [MEM_W-1:0] mem_wr_data; +logic [MEM_W-1:0] mem_rd_data_reg; +logic mem_rd_data_valid_reg = 1'b0, mem_rd_data_valid_next; + +(* ramstyle = "no_rw_check, mlab" *) +logic [MEM_W-1:0] mem_reg[2**IRQN_W] = '{default: '0}; + +logic s_axis_irq_tready_reg = 0, s_axis_irq_tready_next; + +logic [IRQN_W-1:0] m_axis_irq_irqn_reg = '0, m_axis_irq_irqn_next; +logic m_axis_irq_tvalid_reg = 1'b0, m_axis_irq_tvalid_next; + +assign s_axis_irq.tready = s_axis_irq_tready_reg; + +assign m_axis_irq.tdata = m_axis_irq_irqn_reg; +assign m_axis_irq.tkeep = '1; +assign m_axis_irq.tstrb = m_axis_irq.tkeep; +assign m_axis_irq.tvalid = m_axis_irq_tvalid_reg; +assign m_axis_irq.tlast = 1'b1; +assign m_axis_irq.tid = '0; +assign m_axis_irq.tdest = '0; +assign m_axis_irq.tuser = '0; + +logic [15:0] prescale_count_reg = '0; +logic [TSTAMP_W-1:0] time_count_reg = '0; + +always_ff @(posedge clk) begin + if (prescale_count_reg != 0) begin + prescale_count_reg <= prescale_count_reg - 1; + end else begin + prescale_count_reg <= prescale; + time_count_reg <= time_count_reg + 1; + end + + if (rst) begin + prescale_count_reg <= '0; + time_count_reg <= '0; + end +end + +always_comb begin + state_next = STATE_INIT; + + cur_index_next = cur_index_reg; + irqn_next = irqn_reg; + + s_axis_irq_tready_next = 1'b0; + + m_axis_irq_irqn_next = m_axis_irq_irqn_reg; + m_axis_irq_tvalid_next = m_axis_irq_tvalid_reg && !m_axis_irq.tready; + + mem_rd_en = 1'b0; + mem_wr_en = 1'b0; + mem_addr = cur_index_reg; + mem_wr_data = mem_rd_data_reg; + mem_rd_data_valid_next = mem_rd_data_valid_reg; + + case (state_reg) + STATE_INIT: begin + // init - clear all timers + mem_addr = cur_index_reg; + mem_wr_data[0] = 1'b0; + mem_wr_data[1] = 1'b0; + mem_wr_data[2 +: TSTAMP_W] = '0; + mem_wr_en = 1'b1; + cur_index_next = cur_index_reg + 1; + if (&cur_index_reg) begin + state_next = STATE_IDLE; + end else begin + state_next = STATE_INIT; + end + end + STATE_IDLE: begin + // idle - wait for requests and check timers + if (s_axis_irq.tvalid) begin + // new interrupt request + irqn_next = s_axis_irq.tdata; + mem_addr = s_axis_irq.tdata; + mem_rd_en = 1'b1; + mem_rd_data_valid_next = 1'b1; + s_axis_irq_tready_next = 1'b1; + state_next = STATE_IRQ_IN; + end else if (mem_rd_data_valid_reg && mem_rd_data_reg[1] && (mem_rd_data_reg[2 +: TSTAMP_W] - time_count_reg) >> (TSTAMP_W-1) != 0) begin + // timer expired + state_next = STATE_IRQ_OUT; + end else begin + // read next timer + irqn_next = cur_index_reg; + mem_addr = cur_index_reg; + mem_rd_en = 1'b1; + mem_rd_data_valid_next = 1'b1; + cur_index_next = cur_index_reg + 1; + state_next = STATE_IDLE; + end + end + STATE_IRQ_IN: begin + // pass through IRQ + if (mem_rd_data_reg[1]) begin + // timer running, set pending bit + mem_addr = irqn_reg; + mem_wr_data[0] = 1'b1; + mem_wr_data[1] = 1'b1; + mem_wr_data[2 +: TSTAMP_W] = mem_rd_data_reg[2 +: TSTAMP_W]; + mem_wr_en = 1'b1; + mem_rd_data_valid_next = 1'b0; + + state_next = STATE_IDLE; + end else if (!m_axis_irq_tvalid_reg || m_axis_irq.tready) begin + // timer not running, start timer and generate IRQ + mem_addr = irqn_reg; + mem_wr_data[0] = 1'b0; + mem_wr_data[1] = min_interval != 0; + mem_wr_data[2 +: TSTAMP_W] = time_count_reg + min_interval; + mem_wr_en = 1'b1; + mem_rd_data_valid_next = 1'b0; + + m_axis_irq_tvalid_next = 1'b1; + m_axis_irq_irqn_next = irqn_reg; + + state_next = STATE_IDLE; + end else begin + state_next = STATE_IRQ_IN; + end + end + STATE_IRQ_OUT: begin + // handle timer expiration + if (mem_rd_data_reg[0]) begin + // pending bit set, generate IRQ and restart timer + if (!m_axis_irq_tvalid_reg || m_axis_irq.tready) begin + mem_addr = irqn_reg; + mem_wr_data[0] = 1'b0; + mem_wr_data[1] = min_interval != 0; + mem_wr_data[2 +: TSTAMP_W] = time_count_reg + min_interval; + mem_wr_en = 1'b1; + mem_rd_data_valid_next = 1'b0; + + m_axis_irq_tvalid_next = 1'b1; + m_axis_irq_irqn_next = irqn_reg; + + state_next = STATE_IDLE; + end else begin + state_next = STATE_IRQ_OUT; + end + end else begin + // pending bit not set, reset timer + mem_addr = irqn_reg; + mem_wr_data[0] = 1'b0; + mem_wr_data[1] = 1'b0; + mem_wr_data[2 +: TSTAMP_W] = '0; + mem_wr_en = 1'b1; + mem_rd_data_valid_next = 1'b0; + + state_next = STATE_IDLE; + end + end + endcase +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + cur_index_reg <= cur_index_next; + irqn_reg <= irqn_next; + + s_axis_irq_tready_reg <= s_axis_irq_tready_next; + + m_axis_irq_irqn_reg <= m_axis_irq_irqn_next; + m_axis_irq_tvalid_reg <= m_axis_irq_tvalid_next; + + if (mem_wr_en) begin + mem_reg[mem_addr] <= mem_wr_data; + end else if (mem_rd_en) begin + mem_rd_data_reg <= mem_reg[mem_addr]; + end + + mem_rd_data_valid_reg <= mem_rd_data_valid_next; + + if (rst) begin + state_reg <= STATE_INIT; + cur_index_reg <= '0; + s_axis_irq_tready_reg <= 1'b0; + m_axis_irq_tvalid_reg <= 1'b0; + mem_rd_data_valid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/pcie/tb/taxi_irq_rate_limit/Makefile b/src/pcie/tb/taxi_irq_rate_limit/Makefile new file mode 100644 index 0000000..59b117b --- /dev/null +++ b/src/pcie/tb/taxi_irq_rate_limit/Makefile @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_irq_rate_limit +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_IRQN_W := 11 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py new file mode 100644 index 0000000..7bbab4c --- /dev/null +++ b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.py @@ -0,0 +1,193 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) + + self.irq_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_irq), dut.clk, dut.rst) + self.irq_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_irq), dut.clk, dut.rst) + + dut.prescale.setimmediatevalue(0) + dut.min_interval.setimmediatevalue(0) + + def set_idle_generator(self, generator=None): + if generator: + self.irq_source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.irq_sink.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_irq(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + dut.prescale.setimmediatevalue(249) + dut.min_interval.setimmediatevalue(100) + + tb.log.info("Test interrupts (single shot)") + + for k in range(8): + await tb.irq_source.send([k]) + + for k in range(8): + irq = await tb.irq_sink.recv() + tb.log.info(irq) + assert irq.tdata[0] == k + + assert tb.irq_sink.empty() + + await Timer(110, 'us') + + assert tb.irq_sink.empty() + + tb.log.info("Test interrupts (multiple)") + + for n in range(5): + for k in range(8): + await tb.irq_source.send([k]) + + for k in range(8): + irq = await tb.irq_sink.recv() + tb.log.info(irq) + assert irq.tdata[0] == k + + assert tb.irq_sink.empty() + + await Timer(99, 'us') + + assert tb.irq_sink.empty() + + await Timer(11, 'us') + + assert not tb.irq_sink.empty() + + for k in range(8): + irq = await tb.irq_sink.recv() + tb.log.info(irq) + assert irq.tdata[0] == k + + assert tb.irq_sink.empty() + + await Timer(110, 'us') + + assert tb.irq_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + for test in [ + run_test_irq + ]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_irq_rate_limit(request): + dut = "taxi_irq_rate_limit" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['IRQN_W'] = 11 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.sv b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.sv new file mode 100644 index 0000000..13b41b3 --- /dev/null +++ b/src/pcie/tb/taxi_irq_rate_limit/test_taxi_irq_rate_limit.sv @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * IRQ rate limit module testbench + */ +module test_taxi_irq_rate_limit # +( + /* verilator lint_off WIDTHTRUNC */ + parameter IRQN_W = 11 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axis_if #( + .DATA_W(IRQN_W), + .KEEP_EN(0), + .KEEP_W(1) +) s_axis_irq(), m_axis_irq(); + +logic [15:0] prescale; +logic [15:0] min_interval; + +taxi_irq_rate_limit +uut ( + .clk(clk), + .rst(rst), + + /* + * Interrupt request input + */ + .s_axis_irq(s_axis_irq), + + /* + * Interrupt request output + */ + .m_axis_irq(m_axis_irq), + + /* + * Configuration + */ + .prescale(prescale), + .min_interval(min_interval) +); + +endmodule + +`resetall