From 2e35f5b5ffbe3900ab9ffe05d234ba7cee9a0ea6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 18 Feb 2025 18:08:25 -0800 Subject: [PATCH] example/KCU105: Add example design for KCU105 Signed-off-by: Alex Forencich --- README.md | 1 + example/KCU105/fpga/README.md | 31 + example/KCU105/fpga/common/vivado.mk | 153 +++++ example/KCU105/fpga/fpga.xdc | 618 ++++++++++++++++++ example/KCU105/fpga/fpga_1g/Makefile | 48 ++ example/KCU105/fpga/ip/basex_pcs_pma_0.tcl | 21 + example/KCU105/fpga/ip/basex_pcs_pma_1.tcl | 21 + example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl | 17 + example/KCU105/fpga/lib/taxi | 1 + example/KCU105/fpga/rtl/fpga.sv | 599 +++++++++++++++++ example/KCU105/fpga/rtl/fpga_core.sv | 345 ++++++++++ example/KCU105/fpga/tb/fpga_core/Makefile | 50 ++ .../fpga/tb/fpga_core/test_fpga_core.py | 234 +++++++ 13 files changed, 2139 insertions(+) create mode 100644 example/KCU105/fpga/README.md create mode 100644 example/KCU105/fpga/common/vivado.mk create mode 100644 example/KCU105/fpga/fpga.xdc create mode 100644 example/KCU105/fpga/fpga_1g/Makefile create mode 100644 example/KCU105/fpga/ip/basex_pcs_pma_0.tcl create mode 100644 example/KCU105/fpga/ip/basex_pcs_pma_1.tcl create mode 100644 example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl create mode 120000 example/KCU105/fpga/lib/taxi create mode 100644 example/KCU105/fpga/rtl/fpga.sv create mode 100644 example/KCU105/fpga/rtl/fpga_core.sv create mode 100644 example/KCU105/fpga/tb/fpga_core/Makefile create mode 100644 example/KCU105/fpga/tb/fpga_core/test_fpga_core.py diff --git a/README.md b/README.md index 7bda77f..df9c79a 100644 --- a/README.md +++ b/README.md @@ -93,6 +93,7 @@ Example designs are provided for several different FPGA boards, showcasing many * Digilent Arty A7 (Xilinx Artix 7 XC7A35T) * Xilinx KC705 (Xilinx Kintex 7 XC7K325T) +* Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040) * Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) ## Testing diff --git a/example/KCU105/fpga/README.md b/example/KCU105/fpga/README.md new file mode 100644 index 0000000..5f89af6 --- /dev/null +++ b/example/KCU105/fpga/README.md @@ -0,0 +1,31 @@ +# Taxi Example Design for KCU105 + +## Introduction + +This example design targets the Xilinx KCU105 FPGA board. + +The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as a looped-back UART on on the USB UART connection. + +* USB UART + * Looped-back UART +* RJ-45 Ethernet port with Marvell 88E1111 PHY + * Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES +* SFP+ cages + * Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver + +## Board details + +* FPGA: xcku040-ffva1156-2-e +* 1000BASE-T PHY: Marvell 88E1111 via SGMII + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run `make program` to program the board with Vivado. + +To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification. + +To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/example/KCU105/fpga/common/vivado.mk b/example/KCU105/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/example/KCU105/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/example/KCU105/fpga/fpga.xdc b/example/KCU105/fpga/fpga.xdc new file mode 100644 index 0000000..bac1845 --- /dev/null +++ b/example/KCU105/fpga/fpga.xdc @@ -0,0 +1,618 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the Xilinx KCU105 board +# part: xcku040-ffva1156-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# 300 MHz system clock +#set_property -dict {LOC AK17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] ;# from U122 Si5335 +#set_property -dict {LOC AK16 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] ;# from U122 Si5335 +#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] + +# 125 MHz system clock +set_property -dict {LOC G10 IOSTANDARD LVDS} [get_ports clk_125mhz_p] ;# from U122 Si5335 +set_property -dict {LOC F10 IOSTANDARD LVDS} [get_ports clk_125mhz_n] ;# from U122 Si5335 +create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] + +# Si570 user clock (156.25 MHz default) +#set_property -dict {LOC M25 IOSTANDARD LVDS_25} [get_ports clk_user_p] ;# from U122 Si5335 +#set_property -dict {LOC M26 IOSTANDARD LVDS_25} [get_ports clk_user_n] ;# from U122 Si5335 +#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] + +# 90 MHz +#set_property -dict {LOC K20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] ;# from U122 Si5335 +#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] + +# User SMA clock J34/J35 +#set_property -dict {LOC D23 IOSTANDARD LVDS} [get_ports clk_user_sma_p] ;# J34 +#set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35 +#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p] + +# LEDs +set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7 +set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6 +set_property -dict {LOC P20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# to DS8 +set_property -dict {LOC P21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# to DS9 +set_property -dict {LOC N22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] ;# to DS10 +set_property -dict {LOC M22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] ;# to DS33 +set_property -dict {LOC R23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] ;# to DS32 +set_property -dict {LOC P23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] ;# to DS31 + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC AN8 IOSTANDARD LVCMOS18} [get_ports reset] ;# from SW5 + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# Push buttons +set_property -dict {LOC AD10 IOSTANDARD LVCMOS18} [get_ports btnu] ;# from SW10 +set_property -dict {LOC AF9 IOSTANDARD LVCMOS18} [get_ports btnl] ;# from SW6 +set_property -dict {LOC AF8 IOSTANDARD LVCMOS18} [get_ports btnd] ;# from SW8 +set_property -dict {LOC AE8 IOSTANDARD LVCMOS18} [get_ports btnr] ;# from SW9 +set_property -dict {LOC AE10 IOSTANDARD LVCMOS18} [get_ports btnc] ;# from SW7 + +set_false_path -from [get_ports {btnu btnl btnd btnr btnc}] +set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}] + +# DIP switches +set_property -dict {LOC AN16 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# from SW12.4 +set_property -dict {LOC AN19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# from SW12.3 +set_property -dict {LOC AP18 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# from SW12.2 +set_property -dict {LOC AN14 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# from SW12.1 + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# PMOD0 +#set_property -dict {LOC AK25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] +#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] +#set_property -dict {LOC AH18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] +#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] +#set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] +#set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] +#set_property -dict {LOC AE21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] +#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] + +#set_false_path -to [get_ports {pmod0[*]}] +#set_output_delay 0 [get_ports {pmod0[*]}] + +# PMOD1 +#set_property -dict {LOC AL14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] +#set_property -dict {LOC AM14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] +#set_property -dict {LOC AP16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] +#set_property -dict {LOC AP15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] +#set_property -dict {LOC AM16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] +#set_property -dict {LOC AM15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] +#set_property -dict {LOC AN18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] +#set_property -dict {LOC AN17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] + +#set_false_path -to [get_ports {pmod1[*]}] +#set_output_delay 0 [get_ports {pmod1[*]}] + +# UART +set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports uart_rxd] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] +set_property -dict {LOC K27 IOSTANDARD LVCMOS18} [get_ports uart_cts] + +set_false_path -to [get_ports {uart_txd uart_rts}] +set_output_delay 0 [get_ports {uart_txd uart_rts}] +set_false_path -from [get_ports {uart_rxd uart_cts}] +set_input_delay 0 [get_ports {uart_rxd uart_cts}] + +# I2C interface +#set_property -dict {LOC J24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +#set_property -dict {LOC J25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +#set_false_path -to [get_ports {i2c_sda i2c_scl}] +#set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +#set_false_path -from [get_ports {i2c_sda i2c_scl}] +#set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# Gigabit Ethernet SGMII PHY +set_property -dict {LOC P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p] +set_property -dict {LOC P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_n] +set_property -dict {LOC N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p] +set_property -dict {LOC M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_n] +set_property -dict {LOC P26 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_p] +set_property -dict {LOC N26 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_n] +set_property -dict {LOC J23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18} [get_ports phy_int_n] +#set_property -dict {LOC H26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] +#set_property -dict {LOC L25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] + +# 625 MHz ref clock from SGMII PHY +#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] + +set_false_path -to [get_ports {phy_reset_n}] +set_output_delay 0 [get_ports {phy_reset_n}] +set_false_path -from [get_ports {phy_int_n}] +set_input_delay 0 [get_ports {phy_int_n}] + +#set_false_path -to [get_ports {phy_mdio phy_mdc}] +#set_output_delay 0 [get_ports {phy_mdio phy_mdc}] +#set_false_path -from [get_ports {phy_mdio}] +#set_input_delay 0 [get_ports {phy_mdio}] + +# SFP+ interface +set_property -dict {LOC T2 } [get_ports {sfp0_rx_p}] ;# MGTYRXP2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC T1 } [get_ports {sfp0_rx_n}] ;# MGTYRXN2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC U4 } [get_ports {sfp0_tx_p}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC U3 } [get_ports {sfp0_tx_n}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC V2 } [get_ports {sfp1_rx_p}] ;# MGTYRXP1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC V1 } [get_ports {sfp1_rx_n}] ;# MGTYRXN1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC W4 } [get_ports {sfp1_tx_p}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC W3 } [get_ports {sfp1_tx_n}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC P6 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_227 from U32 Si570 via U104 Si53340 +set_property -dict {LOC P5 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_227 from U32 Si570 via U104 Si53340 +#set_property -dict {LOC M6 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_227 from U57 Si5328B +#set_property -dict {LOC M5 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_227 from U57 Si5328B +#set_property -dict {LOC AG11 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U57 CKIN1 SI5328 +#set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328 + +set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp0_tx_disable_b}] +set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp1_tx_disable_b}] + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] +#create_clock -period 6.400 -name sfp_mgt_refclk_1 [get_ports sfp_mgt_refclk_1_p] + +set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] +set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] + +# PCIe Interface +#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AE4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AE3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AG4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AG3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AH6 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AH5 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AK6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AK5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AL4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AL3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AM6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AM5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AN4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AN3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AB6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225 +#set_property -dict {LOC AB5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225 +#set_property -dict {LOC K22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# FMC interface +# FMC HPC J22 +#set_property -dict {LOC H11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[0]"] ;# J22.G9 LA00_P_CC +#set_property -dict {LOC G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[0]"] ;# J22.G10 LA00_N_CC +#set_property -dict {LOC G9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[1]"] ;# J22.D8 LA01_P_CC +#set_property -dict {LOC F9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[1]"] ;# J22.D9 LA01_N_CC +#set_property -dict {LOC K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[2]"] ;# J22.H7 LA02_P +#set_property -dict {LOC J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[2]"] ;# J22.H8 LA02_N +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[3]"] ;# J22.G12 LA03_P +#set_property -dict {LOC A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[3]"] ;# J22.G13 LA03_N +#set_property -dict {LOC L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[4]"] ;# J22.H10 LA04_P +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[4]"] ;# J22.H11 LA04_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[5]"] ;# J22.D11 LA05_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[5]"] ;# J22.D12 LA05_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[6]"] ;# J22.C10 LA06_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[6]"] ;# J22.C11 LA06_N +#set_property -dict {LOC F8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[7]"] ;# J22.H13 LA07_P +#set_property -dict {LOC E8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[7]"] ;# J22.H14 LA07_N +#set_property -dict {LOC J8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[8]"] ;# J22.G12 LA08_P +#set_property -dict {LOC H8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[8]"] ;# J22.G13 LA08_N +#set_property -dict {LOC J9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[9]"] ;# J22.D14 LA09_P +#set_property -dict {LOC H9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[9]"] ;# J22.D15 LA09_N +#set_property -dict {LOC L8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[10]"] ;# J22.C14 LA10_P +#set_property -dict {LOC K8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[10]"] ;# J22.C15 LA10_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[11]"] ;# J22.H16 LA11_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[11]"] ;# J22.H17 LA11_N +#set_property -dict {LOC E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[12]"] ;# J22.G15 LA12_P +#set_property -dict {LOC D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[12]"] ;# J22.G16 LA12_N +#set_property -dict {LOC D9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[13]"] ;# J22.D17 LA13_P +#set_property -dict {LOC C9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[13]"] ;# J22.D18 LA13_N +#set_property -dict {LOC B10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[14]"] ;# J22.C18 LA14_P +#set_property -dict {LOC A10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[14]"] ;# J22.C19 LA14_N +#set_property -dict {LOC D8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[15]"] ;# J22.H19 LA15_P +#set_property -dict {LOC C8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[15]"] ;# J22.H20 LA15_N +#set_property -dict {LOC B9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[16]"] ;# J22.G18 LA16_P +#set_property -dict {LOC A9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[16]"] ;# J22.G19 LA16_N +#set_property -dict {LOC D24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[17]"] ;# J22.D20 LA17_P_CC +#set_property -dict {LOC C24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[17]"] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC E22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[18]"] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC E23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[18]"] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[19]"] ;# J22.H22 LA19_P +#set_property -dict {LOC C22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[19]"] ;# J22.H23 LA19_N +#set_property -dict {LOC B24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[20]"] ;# J22.G21 LA20_P +#set_property -dict {LOC A24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[20]"] ;# J22.G22 LA20_N +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[21]"] ;# J22.H25 LA21_P +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[21]"] ;# J22.H26 LA21_N +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[22]"] ;# J22.G24 LA22_P +#set_property -dict {LOC F25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[22]"] ;# J22.G25 LA22_N +#set_property -dict {LOC G22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[23]"] ;# J22.D23 LA23_P +#set_property -dict {LOC F22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[23]"] ;# J22.D24 LA23_N +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[24]"] ;# J22.H28 LA24_P +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[24]"] ;# J22.H29 LA24_N +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[25]"] ;# J22.G27 LA25_P +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[25]"] ;# J22.G28 LA25_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[26]"] ;# J22.D26 LA26_P +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[26]"] ;# J22.D27 LA26_N +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[27]"] ;# J22.C26 LA27_P +#set_property -dict {LOC G21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[27]"] ;# J22.C27 LA27_N +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[28]"] ;# J22.H31 LA28_P +#set_property -dict {LOC B22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[28]"] ;# J22.H32 LA28_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[29]"] ;# J22.G30 LA29_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[29]"] ;# J22.G31 LA29_N +#set_property -dict {LOC C26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[30]"] ;# J22.H34 LA30_P +#set_property -dict {LOC B26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[30]"] ;# J22.H35 LA30_N +#set_property -dict {LOC B25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[31]"] ;# J22.G33 LA31_P +#set_property -dict {LOC A25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[31]"] ;# J22.G34 LA31_N +#set_property -dict {LOC E26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[32]"] ;# J22.H37 LA32_P +#set_property -dict {LOC D26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[32]"] ;# J22.H38 LA32_N +#set_property -dict {LOC A27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[33]"] ;# J22.G36 LA33_P +#set_property -dict {LOC A28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[33]"] ;# J22.G37 LA33_N + +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[0]"] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[0]"] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[1]"] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[1]"] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[2]"] ;# J22.K7 HA02_P +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[2]"] ;# J22.K8 HA02_N +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[3]"] ;# J22.J6 HA03_P +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[3]"] ;# J22.J7 HA03_N +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[4]"] ;# J22.F7 HA04_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[4]"] ;# J22.F8 HA04_N +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[5]"] ;# J22.E6 HA05_P +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[5]"] ;# J22.E7 HA05_N +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[6]"] ;# J22.K10 HA06_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[6]"] ;# J22.K11 HA06_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[7]"] ;# J22.J9 HA07_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[7]"] ;# J22.J10 HA07_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[8]"] ;# J22.F10 HA08_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[8]"] ;# J22.F11 HA08_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[9]"] ;# J22.E9 HA09_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[9]"] ;# J22.E10 HA09_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[10]"] ;# J22.K13 HA10_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[10]"] ;# J22.K14 HA10_N +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[11]"] ;# J22.J12 HA11_P +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[11]"] ;# J22.J13 HA11_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[12]"] ;# J22.F13 HA12_P +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[12]"] ;# J22.F14 HA12_N +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[13]"] ;# J22.E12 HA13_P +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[13]"] ;# J22.E13 HA13_N +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[14]"] ;# J22.J15 HA14_P +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[14]"] ;# J22.J16 HA14_N +#set_property -dict {LOC D14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[15]"] ;# J22.F14 HA15_P +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[15]"] ;# J22.F16 HA15_N +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[16]"] ;# J22.E15 HA16_P +#set_property -dict {LOC A18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[16]"] ;# J22.E16 HA16_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[17]"] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[17]"] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[18]"] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[18]"] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[19]"] ;# J22.F19 HA19_P +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[19]"] ;# J22.F20 HA19_N +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[20]"] ;# J22.E18 HA20_P +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[20]"] ;# J22.E19 HA20_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[21]"] ;# J22.K19 HA21_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[21]"] ;# J22.K20 HA21_N +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[22]"] ;# J22.J21 HA22_P +#set_property -dict {LOC C17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[22]"] ;# J22.J22 HA22_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[23]"] ;# J22.K22 HA23_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[23]"] ;# J22.K23 HA23_N + +#set_property -dict {LOC H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk0_m2c_p"] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk0_m2c_n"] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC E25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk1_m2c_p"] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC D25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk1_m2c_n"] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC L27 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC H24 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L + +#set_property -dict {LOC F6} [get_ports {fmc_hpc_dp_c2m_p[0]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C2 DP0_C2M_P +#set_property -dict {LOC F5} [get_ports {fmc_hpc_dp_c2m_n[0]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C3 DP0_C2M_N +#set_property -dict {LOC E4} [get_ports {fmc_hpc_dp_m2c_p[0]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C6 DP0_M2C_P +#set_property -dict {LOC E3} [get_ports {fmc_hpc_dp_m2c_n[0]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C7 DP0_M2C_N +#set_property -dict {LOC D6} [get_ports {fmc_hpc_dp_c2m_p[1]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A22 DP1_C2M_P +#set_property -dict {LOC D5} [get_ports {fmc_hpc_dp_c2m_n[1]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A23 DP1_C2M_N +#set_property -dict {LOC D2} [get_ports {fmc_hpc_dp_m2c_p[1]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A2 DP1_M2C_P +#set_property -dict {LOC D1} [get_ports {fmc_hpc_dp_m2c_n[1]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A3 DP1_M2C_N +#set_property -dict {LOC C4} [get_ports {fmc_hpc_dp_c2m_p[2]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A26 DP2_C2M_P +#set_property -dict {LOC C3} [get_ports {fmc_hpc_dp_c2m_n[2]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A27 DP2_C2M_N +#set_property -dict {LOC B2} [get_ports {fmc_hpc_dp_m2c_p[2]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A6 DP2_M2C_P +#set_property -dict {LOC B1} [get_ports {fmc_hpc_dp_m2c_n[2]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A7 DP2_M2C_N +#set_property -dict {LOC B6} [get_ports {fmc_hpc_dp_c2m_p[3]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A30 DP3_C2M_P +#set_property -dict {LOC B5} [get_ports {fmc_hpc_dp_c2m_n[3]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A31 DP3_C2M_N +#set_property -dict {LOC A4} [get_ports {fmc_hpc_dp_m2c_p[3]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A10 DP3_M2C_P +#set_property -dict {LOC A3} [get_ports {fmc_hpc_dp_m2c_n[3]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A11 DP3_M2C_N +#set_property -dict {LOC K6 } [get_ports fmc_hpc_mgt_refclk_0_p] ;# MGTREFCLK0P_228 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC K5 } [get_ports fmc_hpc_mgt_refclk_0_n] ;# MGTREFCLK0N_228 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC H6 } [get_ports fmc_hpc_mgt_refclk_1_p] ;# MGTREFCLK1P_228 from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC H5 } [get_ports fmc_hpc_mgt_refclk_1_n] ;# MGTREFCLK1N_228 from J22.B21 GBTCLK1_M2C_N + +#set_property -dict {LOC N4} [get_ports {fmc_hpc_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A34 DP4_C2M_P +#set_property -dict {LOC N3} [get_ports {fmc_hpc_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A35 DP4_C2M_N +#set_property -dict {LOC M2} [get_ports {fmc_hpc_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A14 DP4_M2C_P +#set_property -dict {LOC M1} [get_ports {fmc_hpc_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A15 DP4_M2C_N +#set_property -dict {LOC L4} [get_ports {fmc_hpc_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A38 DP5_C2M_P +#set_property -dict {LOC L3} [get_ports {fmc_hpc_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A39 DP5_C2M_N +#set_property -dict {LOC K2} [get_ports {fmc_hpc_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A18 DP5_M2C_P +#set_property -dict {LOC K1} [get_ports {fmc_hpc_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A19 DP5_M2C_N +#set_property -dict {LOC J4} [get_ports {fmc_hpc_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B36 DP6_C2M_P +#set_property -dict {LOC J3} [get_ports {fmc_hpc_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B37 DP6_C2M_N +#set_property -dict {LOC H2} [get_ports {fmc_hpc_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B16 DP6_M2C_P +#set_property -dict {LOC H1} [get_ports {fmc_hpc_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B17 DP6_M2C_N +#set_property -dict {LOC G4} [get_ports {fmc_hpc_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B32 DP7_C2M_P +#set_property -dict {LOC G3} [get_ports {fmc_hpc_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B33 DP7_C2M_N +#set_property -dict {LOC F2} [get_ports {fmc_hpc_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B12 DP7_M2C_P +#set_property -dict {LOC F1} [get_ports {fmc_hpc_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B13 DP7_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_0 [get_ports fmc_hpc_mgt_refclk_0_p] +#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_1 [get_ports fmc_hpc_mgt_refclk_1_p] + +# FMC LPC J2 +#set_property -dict {LOC W23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[0]"] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC W24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[0]"] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC W25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[1]"] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC Y25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[1]"] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC AA22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[2]"] ;# J2.H7 LA02_P +#set_property -dict {LOC AB22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[2]"] ;# J2.H8 LA02_N +#set_property -dict {LOC W28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[3]"] ;# J2.G12 LA03_P +#set_property -dict {LOC Y28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[3]"] ;# J2.G13 LA03_N +#set_property -dict {LOC U26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[4]"] ;# J2.H10 LA04_P +#set_property -dict {LOC U27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[4]"] ;# J2.H11 LA04_N +#set_property -dict {LOC V27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[5]"] ;# J2.D11 LA05_P +#set_property -dict {LOC V28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[5]"] ;# J2.D12 LA05_N +#set_property -dict {LOC V29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[6]"] ;# J2.C10 LA06_P +#set_property -dict {LOC W29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[6]"] ;# J2.C11 LA06_N +#set_property -dict {LOC V22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[7]"] ;# J2.H13 LA07_P +#set_property -dict {LOC V23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[7]"] ;# J2.H14 LA07_N +#set_property -dict {LOC U24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[8]"] ;# J2.G12 LA08_P +#set_property -dict {LOC U25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[8]"] ;# J2.G13 LA08_N +#set_property -dict {LOC V26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[9]"] ;# J2.D14 LA09_P +#set_property -dict {LOC W26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[9]"] ;# J2.D15 LA09_N +#set_property -dict {LOC T22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[10]"] ;# J2.C14 LA10_P +#set_property -dict {LOC T23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[10]"] ;# J2.C15 LA10_N +#set_property -dict {LOC V21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[11]"] ;# J2.H16 LA11_P +#set_property -dict {LOC W21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[11]"] ;# J2.H17 LA11_N +#set_property -dict {LOC AC22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[12]"] ;# J2.G15 LA12_P +#set_property -dict {LOC AC23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[12]"] ;# J2.G16 LA12_N +#set_property -dict {LOC AA20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[13]"] ;# J2.D17 LA13_P +#set_property -dict {LOC AB20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[13]"] ;# J2.D18 LA13_N +#set_property -dict {LOC U21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[14]"] ;# J2.C18 LA14_P +#set_property -dict {LOC U22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[14]"] ;# J2.C19 LA14_N +#set_property -dict {LOC AB25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[15]"] ;# J2.H19 LA15_P +#set_property -dict {LOC AB26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[15]"] ;# J2.H20 LA15_N +#set_property -dict {LOC AB21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[16]"] ;# J2.G18 LA16_P +#set_property -dict {LOC AC21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[16]"] ;# J2.G19 LA16_N +#set_property -dict {LOC AA32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[17]"] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AB32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[17]"] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AB30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[18]"] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AB31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[18]"] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AA29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[19]"] ;# J2.H22 LA19_P +#set_property -dict {LOC AB29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[19]"] ;# J2.H23 LA19_N +#set_property -dict {LOC AA34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[20]"] ;# J2.G21 LA20_P +#set_property -dict {LOC AB34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[20]"] ;# J2.G22 LA20_N +#set_property -dict {LOC AC33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[21]"] ;# J2.H25 LA21_P +#set_property -dict {LOC AD33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[21]"] ;# J2.H26 LA21_N +#set_property -dict {LOC AC34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[22]"] ;# J2.G24 LA22_P +#set_property -dict {LOC AD34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[22]"] ;# J2.G25 LA22_N +#set_property -dict {LOC AD30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[23]"] ;# J2.D23 LA23_P +#set_property -dict {LOC AD31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[23]"] ;# J2.D24 LA23_N +#set_property -dict {LOC AE32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[24]"] ;# J2.H28 LA24_P +#set_property -dict {LOC AF32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[24]"] ;# J2.H29 LA24_N +#set_property -dict {LOC AE33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[25]"] ;# J2.G27 LA25_P +#set_property -dict {LOC AF34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[25]"] ;# J2.G28 LA25_N +#set_property -dict {LOC AF33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[26]"] ;# J2.D26 LA26_P +#set_property -dict {LOC AG34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[26]"] ;# J2.D27 LA26_N +#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[27]"] ;# J2.C26 LA27_P +#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[27]"] ;# J2.C27 LA27_N +#set_property -dict {LOC V31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[28]"] ;# J2.H31 LA28_P +#set_property -dict {LOC W31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[28]"] ;# J2.H32 LA28_N +#set_property -dict {LOC U34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[29]"] ;# J2.G30 LA29_P +#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[29]"] ;# J2.G31 LA29_N +#set_property -dict {LOC Y31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[30]"] ;# J2.H34 LA30_P +#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[30]"] ;# J2.H35 LA30_N +#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[31]"] ;# J2.G33 LA31_P +#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[31]"] ;# J2.G34 LA31_N +#set_property -dict {LOC W30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[32]"] ;# J2.H37 LA32_P +#set_property -dict {LOC Y30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[32]"] ;# J2.H38 LA32_N +#set_property -dict {LOC W33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[33]"] ;# J2.G36 LA33_P +#set_property -dict {LOC Y33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[33]"] ;# J2.G37 LA33_N + +#set_property -dict {LOC AA24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk0_m2c_p"] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC AA25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk0_m2c_n"] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AC31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk1_m2c_p"] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AC32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk1_m2c_n"] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC J26 IOSTANDARD LVCMOS18} [get_ports {fmc_lpc_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +#set_property -dict {LOC AA4 } [get_ports {fmc_lpc_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C2 DP0_C2M_P +#set_property -dict {LOC AA3 } [get_ports {fmc_lpc_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C3 DP0_C2M_N +#set_property -dict {LOC Y2 } [get_ports {fmc_lpc_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C6 DP0_M2C_P +#set_property -dict {LOC Y1 } [get_ports {fmc_lpc_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C7 DP0_M2C_N +#set_property -dict {LOC T6 } [get_ports fmc_lpc_mgt_refclk_p] ;# MGTREFCLK1P_226 from J2.D4 GBTCLK0_M2C_P +#set_property -dict {LOC T5 } [get_ports fmc_lpc_mgt_refclk_n] ;# MGTREFCLK1N_226 from J2.D5 GBTCLK0_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_lpc_mgt_refclk [get_ports fmc_lpc_mgt_refclk_p] + +# DDR4 C1 +# 4x MT40A256M16GE-075E +#set_property -dict {LOC AE17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AH17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AJ15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AG16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AL17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AK18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC AG17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC AH19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AG19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AD16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AG14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AF17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC AG15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AE16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC AE15 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC AD15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC AH14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AJ18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AL18 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC AJ16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC AH16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC AG22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC AG24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC AF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC AH23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC AG25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC AG21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC AH21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC AH24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC AJ25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC AK23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC AN24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC AK20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC AP20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC AM21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AH28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC AK27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC AM26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC AL27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC AN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC AN26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC AH32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC AJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC AK32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC AN33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC AP33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC AM34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC AM32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC AL34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC AH33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC AJ33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC AN34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC AP34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC AL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +# QSPI flash +#set_property -dict {LOC M20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC L20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC R21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC R22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC G26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/example/KCU105/fpga/fpga_1g/Makefile b/example/KCU105/fpga/fpga_1g/Makefile new file mode 100644 index 0000000..0994f06 --- /dev/null +++ b/example/KCU105/fpga/fpga_1g/Makefile @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku040-ffva1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexu + +# Files for synthesis +SYN_FILES = ../rtl/fpga.sv +SYN_FILES += ../rtl/fpga_core.sv +SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f +SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv +SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl + +# IP +IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl +IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl +IP_TCL_FILES += ../ip/basex_pcs_pma_1.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl b/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl new file mode 100644 index 0000000..43a289a --- /dev/null +++ b/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {1000BASEX} \ + CONFIG.Physical_Interface {Transceiver} \ + CONFIG.Management_Interface {false} \ + CONFIG.Auto_Negotiation {false} \ + CONFIG.TransceiverControl {false} \ + CONFIG.RefClkRate {156.25} \ + CONFIG.DrpClkRate {62.5} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.GT_Location {X0Y10} \ +] [get_ips basex_pcs_pma_0] diff --git a/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl b/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl new file mode 100644 index 0000000..bca6438 --- /dev/null +++ b/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_1 + +set_property -dict [list \ + CONFIG.Standard {1000BASEX} \ + CONFIG.Physical_Interface {Transceiver} \ + CONFIG.Management_Interface {false} \ + CONFIG.Auto_Negotiation {false} \ + CONFIG.TransceiverControl {false} \ + CONFIG.RefClkRate {156.25} \ + CONFIG.DrpClkRate {62.5} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ + CONFIG.GT_Location {X0Y9} \ +] [get_ips basex_pcs_pma_1] diff --git a/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl b/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl new file mode 100644 index 0000000..d62c25c --- /dev/null +++ b/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ +] [get_ips sgmii_pcs_pma_0] diff --git a/example/KCU105/fpga/lib/taxi b/example/KCU105/fpga/lib/taxi new file mode 120000 index 0000000..11a54ed --- /dev/null +++ b/example/KCU105/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/example/KCU105/fpga/rtl/fpga.sv b/example/KCU105/fpga/rtl/fpga.sv new file mode 100644 index 0000000..e08176f --- /dev/null +++ b/example/KCU105/fpga/rtl/fpga.sv @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga +( + /* + * Clock: 125MHz LVDS + * Reset: Push button, active high + */ + input wire logic clk_125mhz_p, + input wire logic clk_125mhz_n, + input wire logic reset, + + /* + * GPIO + */ + input wire logic btnu, + input wire logic btnl, + input wire logic btnd, + input wire logic btnr, + input wire logic btnc, + input wire logic [3:0] sw, + output wire logic [7:0] led, + + /* + * UART: 115200 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + output wire logic uart_rts, + input wire logic uart_cts, + + /* + * Ethernet: 1000BASE-T SGMII + */ + input wire logic phy_sgmii_rx_p, + input wire logic phy_sgmii_rx_n, + output wire logic phy_sgmii_tx_p, + output wire logic phy_sgmii_tx_n, + input wire logic phy_sgmii_clk_p, + input wire logic phy_sgmii_clk_n, + output wire logic phy_reset_n, + input wire logic phy_int_n, + + /* + * Ethernet: SFP+ + */ + input wire logic sfp0_rx_p, + input wire logic sfp0_rx_n, + output wire logic sfp0_tx_p, + output wire logic sfp0_tx_n, + input wire logic sfp1_rx_p, + input wire logic sfp1_rx_n, + output wire logic sfp1_tx_p, + output wire logic sfp1_tx_n, + input wire logic sfp_mgt_refclk_0_p, + input wire logic sfp_mgt_refclk_0_n, + + output wire logic sfp0_tx_disable_b, + output wire logic sfp1_tx_disable_b +); + +// Clock and reset + +wire clk_125mhz_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 62.5 MHz clock +wire clk_62mhz_mmcm_out; +wire clk_62mhz_int; + +wire mmcm_rst = reset; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_125mhz_ibufg_inst ( + .O (clk_125mhz_ibufg), + .I (clk_125mhz_p), + .IB (clk_125mhz_n) +); + +// MMCM instance +MMCME3_BASE #( + // 125 MHz input + .CLKIN1_PERIOD(8.0), + .REF_JITTER1(0.010), + // 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 125 MHz PFD * 10 = 1250 MHz VCO (range 600 MHz to 1440 MHz) + .CLKFBOUT_MULT_F(10), + .CLKFBOUT_PHASE(0), + // 1250 MHz / 10 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(5), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // 1250 MHz / 20 = 62.5 MHz, 0 degrees + .CLKOUT1_DIVIDE(20), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 125 MHz input + .CLKIN1(clk_125mhz_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // 125 MHz, 0 degrees + .CLKOUT1(clk_62mhz_mmcm_out), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +BUFG +clk_62mhz_bufg_inst ( + .I(clk_62mhz_mmcm_out), + .O(clk_62mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btnu_int; +wire btnl_int; +wire btnd_int; +wire btnr_int; +wire btnc_int; +wire [3:0] sw_int; + +taxi_debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({btnu, + btnl, + btnd, + btnr, + btnc, + sw}), + .out({btnu_int, + btnl_int, + btnd_int, + btnr_int, + btnc_int, + sw_int}) +); + +wire uart_rxd_int; +wire uart_cts_int; + +taxi_sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_rxd, uart_cts}), + .out({uart_rxd_int, uart_cts_int}) +); + +wire [7:0] led_int; + +// SGMII interface to PHY +wire phy_gmii_clk_int; +wire phy_gmii_rst_int; +wire phy_gmii_clk_en_int; +wire [7:0] phy_gmii_txd_int; +wire phy_gmii_tx_en_int; +wire phy_gmii_tx_er_int; +wire [7:0] phy_gmii_rxd_int; +wire phy_gmii_rx_dv_int; +wire phy_gmii_rx_er_int; + +wire [15:0] sgmii_status_vect; + +wire sgmii_status_link_status = sgmii_status_vect[0]; +wire sgmii_status_link_synchronization = sgmii_status_vect[1]; +wire sgmii_status_rudi_c = sgmii_status_vect[2]; +wire sgmii_status_rudi_i = sgmii_status_vect[3]; +wire sgmii_status_rudi_invalid = sgmii_status_vect[4]; +wire sgmii_status_rxdisperr = sgmii_status_vect[5]; +wire sgmii_status_rxnotintable = sgmii_status_vect[6]; +wire sgmii_status_phy_link_status = sgmii_status_vect[7]; +wire [1:0] sgmii_status_remote_fault_encdg = sgmii_status_vect[9:8]; +wire [1:0] sgmii_status_speed = sgmii_status_vect[11:10]; +wire sgmii_status_duplex = sgmii_status_vect[12]; +wire sgmii_status_remote_fault = sgmii_status_vect[13]; +wire [1:0] sgmii_status_pause = sgmii_status_vect[15:14]; + +wire [4:0] sgmii_config_vect; + +assign sgmii_config_vect[4] = 1'b1; // autonegotiation enable +assign sgmii_config_vect[3] = 1'b0; // isolate +assign sgmii_config_vect[2] = 1'b0; // power down +assign sgmii_config_vect[1] = 1'b0; // loopback enable +assign sgmii_config_vect[0] = 1'b0; // unidirectional enable + +wire [15:0] sgmii_an_config_vect; + +assign sgmii_an_config_vect[15] = 1'b1; // SGMII link status +assign sgmii_an_config_vect[14] = 1'b1; // SGMII Acknowledge +assign sgmii_an_config_vect[13:12] = 2'b01; // full duplex +assign sgmii_an_config_vect[11:10] = 2'b10; // SGMII speed +assign sgmii_an_config_vect[9] = 1'b0; // reserved +assign sgmii_an_config_vect[8:7] = 2'b00; // pause frames - SGMII reserved +assign sgmii_an_config_vect[6] = 1'b0; // reserved +assign sgmii_an_config_vect[5] = 1'b0; // full duplex - SGMII reserved +assign sgmii_an_config_vect[4:1] = 4'b0000; // reserved +assign sgmii_an_config_vect[0] = 1'b1; // SGMII + +sgmii_pcs_pma_0 +eth_pcspma ( + // SGMII + .txp (phy_sgmii_tx_p), + .txn (phy_sgmii_tx_n), + .rxp (phy_sgmii_rx_p), + .rxn (phy_sgmii_rx_n), + + // Ref clock from PHY + .refclk625_p (phy_sgmii_clk_p), + .refclk625_n (phy_sgmii_clk_n), + + // async reset + .reset (rst_125mhz_int), + + // clock and reset outputs + .clk125_out (phy_gmii_clk_int), + .clk625_out (), + .clk312_out (), + .rst_125_out (phy_gmii_rst_int), + .idelay_rdy_out (), + .mmcm_locked_out (), + + // MAC clocking + .sgmii_clk_r (), + .sgmii_clk_f (), + .sgmii_clk_en (phy_gmii_clk_en_int), + + // Speed control + .speed_is_10_100 (sgmii_status_speed != 2'b10), + .speed_is_100 (sgmii_status_speed == 2'b01), + + // Internal GMII + .gmii_txd (phy_gmii_txd_int), + .gmii_tx_en (phy_gmii_tx_en_int), + .gmii_tx_er (phy_gmii_tx_er_int), + .gmii_rxd (phy_gmii_rxd_int), + .gmii_rx_dv (phy_gmii_rx_dv_int), + .gmii_rx_er (phy_gmii_rx_er_int), + .gmii_isolate (), + + // Configuration + .configuration_vector (sgmii_config_vect), + + .an_interrupt (), + .an_adv_config_vector (sgmii_an_config_vect), + .an_restart_config (1'b0), + + // Status + .status_vector (sgmii_status_vect), + .signal_detect (1'b1) +); + +// 1000BASE-X SFP +wire sfp0_gmii_clk_int; +wire sfp0_gmii_rst_int; +wire sfp0_gmii_clk_en_int; +wire [7:0] sfp0_gmii_txd_int; +wire sfp0_gmii_tx_en_int; +wire sfp0_gmii_tx_er_int; +wire [7:0] sfp0_gmii_rxd_int; +wire sfp0_gmii_rx_dv_int; +wire sfp0_gmii_rx_er_int; + +wire sfp0_gmii_gtrefclk; +wire sfp0_gmii_txuserclk; +wire sfp0_gmii_txuserclk2; +wire sfp0_gmii_rxuserclk; +wire sfp0_gmii_rxuserclk2; +wire sfp0_gmii_resetdone; +wire sfp0_gmii_pmareset; +wire sfp0_gmii_mmcm_locked; + +assign sfp0_gmii_clk_int = sfp0_gmii_txuserclk2; + +taxi_sync_reset #( + .N(4) +) +sync_reset_sfp0_inst ( + .clk(sfp0_gmii_clk_int), + .rst(rst_125mhz_int || !sfp0_gmii_resetdone), + .out(sfp0_gmii_rst_int) +); + +wire [15:0] sfp0_status_vect; + +wire sfp0_status_link_status = sfp0_status_vect[0]; +wire sfp0_status_link_synchronization = sfp0_status_vect[1]; +wire sfp0_status_rudi_c = sfp0_status_vect[2]; +wire sfp0_status_rudi_i = sfp0_status_vect[3]; +wire sfp0_status_rudi_invalid = sfp0_status_vect[4]; +wire sfp0_status_rxdisperr = sfp0_status_vect[5]; +wire sfp0_status_rxnotintable = sfp0_status_vect[6]; +wire sfp0_status_phy_link_status = sfp0_status_vect[7]; +wire [1:0] sfp0_status_remote_fault_encdg = sfp0_status_vect[9:8]; +wire [1:0] sfp0_status_speed = sfp0_status_vect[11:10]; +wire sfp0_status_duplex = sfp0_status_vect[12]; +wire sfp0_status_remote_fault = sfp0_status_vect[13]; +wire [1:0] sfp0_status_pause = sfp0_status_vect[15:14]; + +wire [4:0] sfp0_config_vect; + +assign sfp0_config_vect[4] = 1'b0; // autonegotiation enable +assign sfp0_config_vect[3] = 1'b0; // isolate +assign sfp0_config_vect[2] = 1'b0; // power down +assign sfp0_config_vect[1] = 1'b0; // loopback enable +assign sfp0_config_vect[0] = 1'b0; // unidirectional enable + +basex_pcs_pma_0 +sfp0_pcspma ( + .gtrefclk_p(sfp_mgt_refclk_0_p), + .gtrefclk_n(sfp_mgt_refclk_0_n), + .gtrefclk_out(sfp0_gmii_gtrefclk), + .txn(sfp0_tx_n), + .txp(sfp0_tx_p), + .rxn(sfp0_rx_n), + .rxp(sfp0_rx_p), + .independent_clock_bufg(clk_62mhz_int), + .userclk_out(sfp0_gmii_txuserclk), + .userclk2_out(sfp0_gmii_txuserclk2), + .rxuserclk_out(sfp0_gmii_rxuserclk), + .rxuserclk2_out(sfp0_gmii_rxuserclk2), + .gtpowergood(), + .resetdone(sfp0_gmii_resetdone), + .pma_reset_out(sfp0_gmii_pmareset), + .mmcm_locked_out(sfp0_gmii_mmcm_locked), + .gmii_txd(sfp0_gmii_txd_int), + .gmii_tx_en(sfp0_gmii_tx_en_int), + .gmii_tx_er(sfp0_gmii_tx_er_int), + .gmii_rxd(sfp0_gmii_rxd_int), + .gmii_rx_dv(sfp0_gmii_rx_dv_int), + .gmii_rx_er(sfp0_gmii_rx_er_int), + .gmii_isolate(), + .configuration_vector(sfp0_config_vect), + .status_vector(sfp0_status_vect), + .reset(rst_125mhz_int), + .signal_detect(1'b1) +); + +assign sfp0_gmii_clk_en_int = 1'b1; + +wire sfp1_gmii_clk_int; +wire sfp1_gmii_rst_int; +wire sfp1_gmii_clk_en_int; +wire [7:0] sfp1_gmii_txd_int; +wire sfp1_gmii_tx_en_int; +wire sfp1_gmii_tx_er_int; +wire [7:0] sfp1_gmii_rxd_int; +wire sfp1_gmii_rx_dv_int; +wire sfp1_gmii_rx_er_int; + +wire sfp1_gmii_txuserclk2 = sfp0_gmii_txuserclk2; +wire sfp1_gmii_resetdone; + +assign sfp1_gmii_clk_int = sfp1_gmii_txuserclk2; + +taxi_sync_reset #( + .N(4) +) +sync_reset_sfp1_inst ( + .clk(sfp1_gmii_clk_int), + .rst(rst_125mhz_int || !sfp1_gmii_resetdone), + .out(sfp1_gmii_rst_int) +); + +wire [15:0] sfp1_status_vect; + +wire sfp1_status_link_status = sfp1_status_vect[0]; +wire sfp1_status_link_synchronization = sfp1_status_vect[1]; +wire sfp1_status_rudi_c = sfp1_status_vect[2]; +wire sfp1_status_rudi_i = sfp1_status_vect[3]; +wire sfp1_status_rudi_invalid = sfp1_status_vect[4]; +wire sfp1_status_rxdisperr = sfp1_status_vect[5]; +wire sfp1_status_rxnotintable = sfp1_status_vect[6]; +wire sfp1_status_phy_link_status = sfp1_status_vect[7]; +wire [1:0] sfp1_status_remote_fault_encdg = sfp1_status_vect[9:8]; +wire [1:0] sfp1_status_speed = sfp1_status_vect[11:10]; +wire sfp1_status_duplex = sfp1_status_vect[12]; +wire sfp1_status_remote_fault = sfp1_status_vect[13]; +wire [1:0] sfp1_status_pause = sfp1_status_vect[15:14]; + +wire [4:0] sfp1_config_vect; + +assign sfp1_config_vect[4] = 1'b0; // autonegotiation enable +assign sfp1_config_vect[3] = 1'b0; // isolate +assign sfp1_config_vect[2] = 1'b0; // power down +assign sfp1_config_vect[1] = 1'b0; // loopback enable +assign sfp1_config_vect[0] = 1'b0; // unidirectional enable + +basex_pcs_pma_1 +sfp1_pcspma ( + .gtrefclk(sfp0_gmii_gtrefclk), + .txn(sfp1_tx_n), + .txp(sfp1_tx_p), + .rxn(sfp1_rx_n), + .rxp(sfp1_rx_p), + .independent_clock_bufg(clk_62mhz_int), + .txoutclk(), + .gtpowergood(), + .rxoutclk(), + .resetdone(sfp1_gmii_resetdone), + .cplllock(), + .mmcm_reset(), + .userclk(sfp0_gmii_txuserclk), + .userclk2(sfp0_gmii_txuserclk2), + .pma_reset(sfp0_gmii_pmareset), + .mmcm_locked(sfp0_gmii_mmcm_locked), + .rxuserclk(sfp0_gmii_txuserclk), + .rxuserclk2(sfp0_gmii_txuserclk2), + .gmii_txd(sfp1_gmii_txd_int), + .gmii_tx_en(sfp1_gmii_tx_en_int), + .gmii_tx_er(sfp1_gmii_tx_er_int), + .gmii_rxd(sfp1_gmii_rxd_int), + .gmii_rx_dv(sfp1_gmii_rx_dv_int), + .gmii_rx_er(sfp1_gmii_rx_er_int), + .gmii_isolate(), + .configuration_vector(sfp1_config_vect), + .status_vector(sfp1_status_vect), + .reset(rst_125mhz_int), + .signal_detect(1'b1) +); + +assign sfp1_gmii_clk_en_int = 1'b1; + +// SGMII interface debug: +// SW12:1 (sw[3]) off for payload byte, on for status vector +// SW12:2 (sw[2]) off for BASE-T port (SGMII), on for SFP +// SW12:3 (sw[1]) off for SFP0, on for SFP1 +// SW12:4 (sw[0]) off for LSB of status vector, on for MSB +wire [15:0] sel_sv = sw[2] ? (sw[1] ? sfp1_status_vect : sfp0_status_vect) : sgmii_status_vect; +assign led = sw[3] ? (sw[0] ? sel_sv[15:8] : sel_sv[7:0]) : led_int; + +fpga_core +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + + /* + * GPIO + */ + .btnu(btnu_int), + .btnl(btnl_int), + .btnd(btnd_int), + .btnr(btnr_int), + .btnc(btnc_int), + .sw(sw_int), + .led(led_int), + + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd_int), + .uart_txd(uart_txd), + .uart_rts(uart_rts), + .uart_cts(uart_cts_int), + + /* + * Ethernet: 1000BASE-T SGMII + */ + .phy_gmii_clk(phy_gmii_clk_int), + .phy_gmii_rst(phy_gmii_rst_int), + .phy_gmii_clk_en(phy_gmii_clk_en_int), + .phy_gmii_rxd(phy_gmii_rxd_int), + .phy_gmii_rx_dv(phy_gmii_rx_dv_int), + .phy_gmii_rx_er(phy_gmii_rx_er_int), + .phy_gmii_txd(phy_gmii_txd_int), + .phy_gmii_tx_en(phy_gmii_tx_en_int), + .phy_gmii_tx_er(phy_gmii_tx_er_int), + .phy_reset_n(phy_reset_n), + .phy_int_n(phy_int_n), + + /* + * Ethernet: 1000BASE-X SFP + */ + .sfp0_gmii_clk(sfp0_gmii_clk_int), + .sfp0_gmii_rst(sfp0_gmii_rst_int), + .sfp0_gmii_clk_en(sfp0_gmii_clk_en_int), + .sfp0_gmii_rxd(sfp0_gmii_rxd_int), + .sfp0_gmii_rx_dv(sfp0_gmii_rx_dv_int), + .sfp0_gmii_rx_er(sfp0_gmii_rx_er_int), + .sfp0_gmii_txd(sfp0_gmii_txd_int), + .sfp0_gmii_tx_en(sfp0_gmii_tx_en_int), + .sfp0_gmii_tx_er(sfp0_gmii_tx_er_int), + .sfp0_tx_disable_b(sfp0_tx_disable_b), + + .sfp1_gmii_clk(sfp1_gmii_clk_int), + .sfp1_gmii_rst(sfp1_gmii_rst_int), + .sfp1_gmii_clk_en(sfp1_gmii_clk_en_int), + .sfp1_gmii_rxd(sfp1_gmii_rxd_int), + .sfp1_gmii_rx_dv(sfp1_gmii_rx_dv_int), + .sfp1_gmii_rx_er(sfp1_gmii_rx_er_int), + .sfp1_gmii_txd(sfp1_gmii_txd_int), + .sfp1_gmii_tx_en(sfp1_gmii_tx_en_int), + .sfp1_gmii_tx_er(sfp1_gmii_tx_er_int), + .sfp1_tx_disable_b(sfp1_tx_disable_b) +); + +endmodule + +`resetall diff --git a/example/KCU105/fpga/rtl/fpga_core.sv b/example/KCU105/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..3ceb98b --- /dev/null +++ b/example/KCU105/fpga/rtl/fpga_core.sv @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk, + input wire logic rst, + + /* + * GPIO + */ + input wire logic btnu, + input wire logic btnl, + input wire logic btnd, + input wire logic btnr, + input wire logic btnc, + input wire logic [7:0] sw, + output wire logic [7:0] led, + + /* + * UART: 115200 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + output wire logic uart_rts, + input wire logic uart_cts, + + /* + * Ethernet: 1000BASE-T + */ + input wire logic phy_gmii_clk, + input wire logic phy_gmii_rst, + input wire logic phy_gmii_clk_en, + input wire logic [7:0] phy_gmii_rxd, + input wire logic phy_gmii_rx_dv, + input wire logic phy_gmii_rx_er, + output wire logic [7:0] phy_gmii_txd, + output wire logic phy_gmii_tx_en, + output wire logic phy_gmii_tx_er, + output wire logic phy_reset_n, + input wire logic phy_int_n, + + /* + * Ethernet: 1000BASE-X SFP + */ + input wire logic sfp0_gmii_clk, + input wire logic sfp0_gmii_rst, + input wire logic sfp0_gmii_clk_en, + input wire logic [7:0] sfp0_gmii_rxd, + input wire logic sfp0_gmii_rx_dv, + input wire logic sfp0_gmii_rx_er, + output wire logic [7:0] sfp0_gmii_txd, + output wire logic sfp0_gmii_tx_en, + output wire logic sfp0_gmii_tx_er, + output wire logic sfp0_tx_disable_b, + + input wire logic sfp1_gmii_clk, + input wire logic sfp1_gmii_rst, + input wire logic sfp1_gmii_clk_en, + input wire logic [7:0] sfp1_gmii_rxd, + input wire logic sfp1_gmii_rx_dv, + input wire logic sfp1_gmii_rx_er, + output wire logic [7:0] sfp1_gmii_txd, + output wire logic sfp1_gmii_tx_en, + output wire logic sfp1_gmii_tx_er, + output wire logic sfp1_tx_disable_b +); + +assign led = sw; + +// UART +assign uart_rts = 0; + +taxi_axis_if #(.DATA_W(8)) axis_uart(); + +taxi_uart +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Stream input (sink) + */ + .s_axis_tx(axis_uart), + + /* + * AXI4-Stream output (source) + */ + .m_axis_rx(axis_uart), + + /* + * UART interface + */ + .rxd(uart_rxd), + .txd(uart_txd), + + /* + * Status + */ + .tx_busy(), + .rx_busy(), + .rx_overrun_error(), + .rx_frame_error(), + + /* + * Configuration + */ + .prescale(16'(125000000/115200/8)) +); + +// BASE-T PHY +assign phy_reset_n = !rst; + +taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth(); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); + +taxi_eth_mac_1g_fifo #( + .PADDING_EN(1), + .MIN_FRAME_LEN(64), + .TX_FIFO_DEPTH(16384), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(16384), + .RX_FRAME_FIFO(1) +) +eth_mac_inst ( + .rx_clk(phy_gmii_clk), + .rx_rst(phy_gmii_rst), + .tx_clk(phy_gmii_clk), + .tx_rst(phy_gmii_rst), + .logic_clk(clk), + .logic_rst(rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_eth), + .m_axis_tx_cpl(axis_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_eth), + + /* + * GMII interface + */ + .gmii_rxd(phy_gmii_rxd), + .gmii_rx_dv(phy_gmii_rx_dv), + .gmii_rx_er(phy_gmii_rx_er), + .gmii_txd(phy_gmii_txd), + .gmii_tx_en(phy_gmii_tx_en), + .gmii_tx_er(phy_gmii_tx_er), + + /* + * Control + */ + .rx_clk_enable(phy_gmii_clk_en), + .tx_clk_enable(phy_gmii_clk_en), + .rx_mii_select(1'b0), + .tx_mii_select(1'b0), + + /* + * Status + */ + .tx_error_underflow(), + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) +); + +// SFP+ +assign sfp0_tx_disable_b = 1'b1; +assign sfp1_tx_disable_b = 1'b1; + +taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp0_eth(); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp0_tx_cpl(); + +taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp1_eth(); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp1_tx_cpl(); + +taxi_eth_mac_1g_fifo #( + .PADDING_EN(1), + .MIN_FRAME_LEN(64), + .TX_FIFO_DEPTH(16384), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(16384), + .RX_FRAME_FIFO(1) +) +sfp0_eth_mac_inst ( + .rx_clk(sfp0_gmii_clk), + .rx_rst(sfp0_gmii_rst), + .tx_clk(sfp0_gmii_clk), + .tx_rst(sfp0_gmii_rst), + .logic_clk(clk), + .logic_rst(rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_sfp0_eth), + .m_axis_tx_cpl(axis_sfp0_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_sfp0_eth), + + /* + * GMII interface + */ + .gmii_rxd(sfp0_gmii_rxd), + .gmii_rx_dv(sfp0_gmii_rx_dv), + .gmii_rx_er(sfp0_gmii_rx_er), + .gmii_txd(sfp0_gmii_txd), + .gmii_tx_en(sfp0_gmii_tx_en), + .gmii_tx_er(sfp0_gmii_tx_er), + + /* + * Control + */ + .rx_clk_enable(sfp0_gmii_clk_en), + .tx_clk_enable(sfp0_gmii_clk_en), + .rx_mii_select(1'b0), + .tx_mii_select(1'b0), + + /* + * Status + */ + .tx_error_underflow(), + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) +); + +taxi_eth_mac_1g_fifo #( + .PADDING_EN(1), + .MIN_FRAME_LEN(64), + .TX_FIFO_DEPTH(16384), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(16384), + .RX_FRAME_FIFO(1) +) +sfp1_eth_mac_inst ( + .rx_clk(sfp1_gmii_clk), + .rx_rst(sfp1_gmii_rst), + .tx_clk(sfp1_gmii_clk), + .tx_rst(sfp1_gmii_rst), + .logic_clk(clk), + .logic_rst(rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_sfp1_eth), + .m_axis_tx_cpl(axis_sfp1_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_sfp1_eth), + + /* + * GMII interface + */ + .gmii_rxd(sfp1_gmii_rxd), + .gmii_rx_dv(sfp1_gmii_rx_dv), + .gmii_rx_er(sfp1_gmii_rx_er), + .gmii_txd(sfp1_gmii_txd), + .gmii_tx_en(sfp1_gmii_tx_en), + .gmii_tx_er(sfp1_gmii_tx_er), + + /* + * Control + */ + .rx_clk_enable(sfp1_gmii_clk_en), + .tx_clk_enable(sfp1_gmii_clk_en), + .rx_mii_select(1'b0), + .tx_mii_select(1'b0), + + /* + * Status + */ + .tx_error_underflow(), + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) +); + +endmodule + +`resetall diff --git a/example/KCU105/fpga/tb/fpga_core/Makefile b/example/KCU105/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..a9ae733 --- /dev/null +++ b/example/KCU105/fpga/tb/fpga_core/Makefile @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../rtl/$(DUT).sv +VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f +VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +#export PARAM_A := value + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..8ad6fc4 --- /dev/null +++ b/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,234 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Combine + +from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink +from cocotbext.uart import UartSource, UartSink + + +class TB: + def __init__(self, dut, speed=1000e6): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) + cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start()) + cocotb.start_soon(Clock(dut.sfp0_gmii_clk, 8, units="ns").start()) + cocotb.start_soon(Clock(dut.sfp1_gmii_clk, 8, units="ns").start()) + + self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv, + dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en) + self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en, + dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en) + + self.sfp0_source = GmiiSource(dut.sfp0_gmii_rxd, dut.sfp0_gmii_rx_er, dut.sfp0_gmii_rx_dv, + dut.sfp0_gmii_clk, dut.sfp0_gmii_rst, dut.sfp0_gmii_clk_en) + self.sfp0_sink = GmiiSink(dut.sfp0_gmii_txd, dut.sfp0_gmii_tx_er, dut.sfp0_gmii_tx_en, + dut.sfp0_gmii_clk, dut.sfp0_gmii_rst, dut.sfp0_gmii_clk_en) + + self.sfp1_source = GmiiSource(dut.sfp1_gmii_rxd, dut.sfp1_gmii_rx_er, dut.sfp1_gmii_rx_dv, + dut.sfp1_gmii_clk, dut.sfp1_gmii_rst, dut.sfp1_gmii_clk_en) + self.sfp1_sink = GmiiSink(dut.sfp1_gmii_txd, dut.sfp1_gmii_tx_er, dut.sfp1_gmii_tx_en, + dut.sfp1_gmii_clk, dut.sfp1_gmii_rst, dut.sfp1_gmii_clk_en) + + self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1) + + dut.phy_gmii_clk_en.setimmediatevalue(1) + + dut.btnu.setimmediatevalue(0) + dut.btnl.setimmediatevalue(0) + dut.btnd.setimmediatevalue(0) + dut.btnr.setimmediatevalue(0) + dut.btnc.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + dut.uart_rts.setimmediatevalue(0) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + self.dut.phy_gmii_rst.setimmediatevalue(0) + self.dut.sfp0_gmii_rst.setimmediatevalue(0) + self.dut.sfp1_gmii_rst.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + self.dut.phy_gmii_rst.value = 1 + self.dut.sfp0_gmii_rst.value = 1 + self.dut.sfp1_gmii_rst.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + self.dut.phy_gmii_rst.value = 0 + self.dut.sfp0_gmii_rst.value = 0 + self.dut.sfp1_gmii_rst.value = 0 + + +async def uart_test(tb, source, sink): + tb.log.info("Test UART") + + tx_data = b"FPGA Ninja" + + tb.log.info("UART TX: %s", tx_data) + + await source.write(tx_data) + + rx_data = bytearray() + + while len(rx_data) < len(tx_data): + rx_data.extend(await sink.read()) + + tb.log.info("UART RX: %s", rx_data) + + tb.log.info("UART test done") + + +async def mac_test(tb, source, sink): + tb.log.info("Test MAC") + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + for p in pkts: + await source.send(GmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + assert rx_frame.error is None + + tb.log.info("Multiple large packets") + + count = 32 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + for p in pkts: + await source.send(GmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + assert rx_frame.error is None + + tb.log.info("MAC test done") + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Start UART test") + + uart_test_cr = cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)) + + tb.log.info("Start BASE-T MAC loopback test") + + baset_test_cr = cocotb.start_soon(mac_test(tb, tb.gmii_source, tb.gmii_sink)) + + tb.log.info("Start SFP0 MAC loopback test") + + sfp0_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp0_source, tb.sfp0_sink)) + + tb.log.info("Start SFP1 MAC loopback test") + + sfp1_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp1_source, tb.sfp1_sink)) + + await Combine(uart_test_cr, baset_test_cr, sfp0_test_cr, sfp1_test_cr) + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"), + os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), + os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )