diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 1263eb1..03e2b32 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -176,8 +176,10 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -229,7 +231,6 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .tx_clk(qsfp_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -245,10 +246,18 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv index b0c69d5..d9b375c 100644 --- a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv +++ b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv @@ -177,8 +177,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -230,7 +232,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{2{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{2{1'b0}}), /* * Transmit interface (AXI stream) @@ -246,10 +247,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{2{'0}}), - .tx_ptp_ts_step('{2{1'b0}}), - .rx_ptp_ts('{2{'0}}), - .rx_ptp_ts_step('{2{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{2{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{2{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index d0b58c8..191b9f0 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -347,8 +347,10 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -406,7 +408,6 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -422,10 +423,18 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index cf84942..226e75f 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -428,8 +428,10 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -503,7 +505,6 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -519,10 +520,18 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv index 755fe19..9e5dc6b 100644 --- a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv @@ -372,8 +372,10 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -434,7 +436,6 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -450,10 +451,18 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv index 5ad67ff..8f4b40c 100644 --- a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv +++ b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv @@ -519,8 +519,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -582,7 +584,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{1{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{1{1'b0}}), /* * Transmit interface (AXI stream) @@ -598,10 +599,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{1{'0}}), - .tx_ptp_ts_step('{1{1'b0}}), - .rx_ptp_ts('{1{'0}}), - .rx_ptp_ts_step('{1{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{1{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{1{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv index d527823..9ab99a2 100644 --- a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv @@ -606,8 +606,10 @@ end else begin : sfp_mac .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -666,7 +668,6 @@ end else begin : sfp_mac .tx_clk(sfp_tx_clk), .tx_rst_in('{2{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{2{1'b0}}), /* * Transmit interface (AXI stream) @@ -682,10 +683,18 @@ end else begin : sfp_mac /* * PTP clock */ - .tx_ptp_ts('{2{'0}}), - .tx_ptp_ts_step('{2{1'b0}}), - .rx_ptp_ts('{2{'0}}), - .rx_ptp_ts_step('{2{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{2{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{2{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/KR260/fpga/rtl/fpga_core.sv b/src/eth/example/KR260/fpga/rtl/fpga_core.sv index fc90b24..ea11972 100644 --- a/src/eth/example/KR260/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KR260/fpga/rtl/fpga_core.sv @@ -420,8 +420,10 @@ end else begin : sfp_mac .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -473,7 +475,6 @@ end else begin : sfp_mac .tx_clk(sfp_tx_clk), .tx_rst_in('{1{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{1{1'b0}}), /* * Transmit interface (AXI stream) @@ -489,10 +490,18 @@ end else begin : sfp_mac /* * PTP clock */ - .tx_ptp_ts('{1{'0}}), - .tx_ptp_ts_step('{1{1'b0}}), - .rx_ptp_ts('{1{'0}}), - .rx_ptp_ts_step('{1{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{1{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{1{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv index 9625025..7eb90cf 100644 --- a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv @@ -309,8 +309,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -368,7 +370,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{4{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{4{1'b0}}), /* * Transmit interface (AXI stream) @@ -384,10 +385,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{4{'0}}), - .tx_ptp_ts_step('{4{1'b0}}), - .rx_ptp_ts('{4{'0}}), - .rx_ptp_ts_step('{4{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{4{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{4{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv index 1cd60ff..16dbd3b 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv @@ -195,8 +195,10 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -248,7 +250,6 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .tx_clk(qsfp_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -264,10 +265,18 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv index 510f319..d490855 100644 --- a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv @@ -171,8 +171,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -224,7 +226,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{2{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{2{1'b0}}), /* * Transmit interface (AXI stream) @@ -240,10 +241,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{2{'0}}), - .tx_ptp_ts_step('{2{1'b0}}), - .rx_ptp_ts('{2{'0}}), - .rx_ptp_ts_step('{2{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{2{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{2{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/VC709/fpga/rtl/fpga_core.sv b/src/eth/example/VC709/fpga/rtl/fpga_core.sv index 060a7d4..896718b 100644 --- a/src/eth/example/VC709/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VC709/fpga/rtl/fpga_core.sv @@ -314,8 +314,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -373,7 +375,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{4{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{4{1'b0}}), /* * Transmit interface (AXI stream) @@ -389,10 +390,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{4{'0}}), - .tx_ptp_ts_step('{4{1'b0}}), - .rx_ptp_ts('{4{'0}}), - .rx_ptp_ts_step('{4{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{4{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{4{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index 40803cd..70329a2 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -402,8 +402,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -461,7 +463,6 @@ qsfp_mac_inst ( .tx_clk(qsfp_tx_clk), .tx_rst_in('{4{1'b0}}), .tx_rst_out(qsfp_tx_rst), - .ptp_sample_clk('{4{1'b0}}), /* * Transmit interface (AXI stream) @@ -477,10 +478,18 @@ qsfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{4{'0}}), - .tx_ptp_ts_step('{4{1'b0}}), - .rx_ptp_ts('{4{'0}}), - .rx_ptp_ts_step('{4{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{4{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{4{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index 7cb9ab7..2e423d3 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -599,8 +599,10 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -658,7 +660,6 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .tx_clk(qsfp_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -674,10 +675,18 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index 3de5ce0..0b7c2d3 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -326,8 +326,10 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -387,7 +389,6 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -403,10 +404,18 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv index b638f6d..ab80410 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv @@ -661,8 +661,10 @@ end else begin : sfp_mac .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -720,7 +722,6 @@ end else begin : sfp_mac .tx_clk(sfp_tx_clk), .tx_rst_in('{4{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{4{1'b0}}), /* * Transmit interface (AXI stream) @@ -736,10 +737,18 @@ end else begin : sfp_mac /* * PTP clock */ - .tx_ptp_ts('{4{'0}}), - .tx_ptp_ts_step('{4{1'b0}}), - .rx_ptp_ts('{4{'0}}), - .rx_ptp_ts_step('{4{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{4{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{4{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv index c06ed40..5651d6e 100644 --- a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv @@ -476,8 +476,10 @@ end else begin : sfp_mac .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -536,7 +538,6 @@ end else begin : sfp_mac .tx_clk(sfp_tx_clk), .tx_rst_in('{2{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{2{1'b0}}), /* * Transmit interface (AXI stream) @@ -552,10 +553,18 @@ end else begin : sfp_mac /* * PTP clock */ - .tx_ptp_ts('{2{'0}}), - .tx_ptp_ts_step('{2{1'b0}}), - .rx_ptp_ts('{2{'0}}), - .rx_ptp_ts_step('{2{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{2{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{2{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv index 6b3823c..4f359b4 100644 --- a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv @@ -383,8 +383,10 @@ taxi_eth_mac_25g_us #( .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -442,7 +444,6 @@ sfp_mac_inst ( .tx_clk(sfp_tx_clk), .tx_rst_in('{4{1'b0}}), .tx_rst_out(sfp_tx_rst), - .ptp_sample_clk('{4{1'b0}}), /* * Transmit interface (AXI stream) @@ -458,10 +459,18 @@ sfp_mac_inst ( /* * PTP clock */ - .tx_ptp_ts('{4{'0}}), - .tx_ptp_ts_step('{4{1'b0}}), - .rx_ptp_ts('{4{'0}}), - .rx_ptp_ts_step('{4{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{4{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{4{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index e613c9b..9858ba2 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -223,8 +223,10 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .DIC_EN(1'b1), .MIN_FRAME_LEN(64), .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), .PTP_TS_FMT_TOD(1'b1), .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), .PRBS31_EN(1'b0), .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), @@ -276,7 +278,6 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad .tx_clk(qsfp_tx_clk[n*CNT +: CNT]), .tx_rst_in('{CNT{1'b0}}), .tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]), - .ptp_sample_clk('{CNT{1'b0}}), /* * Transmit interface (AXI stream) @@ -292,10 +293,18 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad /* * PTP clock */ - .tx_ptp_ts('{CNT{'0}}), - .tx_ptp_ts_step('{CNT{1'b0}}), - .rx_ptp_ts('{CNT{'0}}), - .rx_ptp_ts_step('{CNT{1'b0}}), + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), /* * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)