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cndm: Fix widths

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-01 14:02:39 -08:00
parent e27b5c0b94
commit 32b073ade9
1 changed files with 12 additions and 12 deletions
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24
src/cndm/rtl/cndm_micro_dp_mgr.sv
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@@ -225,7 +225,7 @@ always_comb begin
CMD_OP_DESTROY_EQ: CMD_OP_DESTROY_EQ:
begin begin
// EQ // EQ
block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 16'h0000); block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0000);
end end
CMD_OP_CREATE_CQ, CMD_OP_CREATE_CQ,
CMD_OP_MODIFY_CQ, CMD_OP_MODIFY_CQ,
@@ -234,9 +234,9 @@ always_comb begin
begin begin
// CQ // CQ
if (qn_reg[0]) begin if (qn_reg[0]) begin
block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 16'h0300); block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0300);
end else begin end else begin
block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 16'h0400); block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0400);
end end
end end
CMD_OP_CREATE_SQ, CMD_OP_CREATE_SQ,
@@ -245,7 +245,7 @@ always_comb begin
CMD_OP_DESTROY_SQ: CMD_OP_DESTROY_SQ:
begin begin
// SQ // SQ
block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 16'h0100); block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0100);
end end
CMD_OP_CREATE_RQ, CMD_OP_CREATE_RQ,
CMD_OP_MODIFY_RQ, CMD_OP_MODIFY_RQ,
@@ -253,7 +253,7 @@ always_comb begin
CMD_OP_DESTROY_RQ: CMD_OP_DESTROY_RQ:
begin begin
// RQ // RQ
block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 16'h0200); block_base_addr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0200);
end end
default: begin end default: begin end
endcase endcase
@@ -324,7 +324,7 @@ always_comb begin
STATE_Q_RESET_1: begin STATE_Q_RESET_1: begin
// reset queue 1 // reset queue 1
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h0000; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h0000;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = 32'h00000000; m_apb_dp_ctrl_pwdata_next = 32'h00000000;
@@ -338,12 +338,12 @@ always_comb begin
STATE_Q_RESET_2: begin STATE_Q_RESET_2: begin
// reset queue 2 // reset queue 2
cmd_ram_wr_data = 32'(block_base_addr_reg + 16'h0004) + PORT_BASE_ADDR; cmd_ram_wr_data = 32'(block_base_addr_reg + 'h0004) + PORT_BASE_ADDR;
cmd_ram_wr_addr = 7; cmd_ram_wr_addr = 7;
cmd_ram_wr_en = 1'b1; cmd_ram_wr_en = 1'b1;
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h0004; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h0004;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = 32'h00000000; m_apb_dp_ctrl_pwdata_next = 32'h00000000;
@@ -358,7 +358,7 @@ always_comb begin
// set queue base addr (LSB) // set queue base addr (LSB)
cmd_ram_rd_addr = 8; cmd_ram_rd_addr = 8;
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h0008; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h0008;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = cmd_ram_rd_data; m_apb_dp_ctrl_pwdata_next = cmd_ram_rd_data;
@@ -373,7 +373,7 @@ always_comb begin
// set queue base addr (MSB) // set queue base addr (MSB)
cmd_ram_rd_addr = 9; cmd_ram_rd_addr = 9;
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h000C; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h000C;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = cmd_ram_rd_data; m_apb_dp_ctrl_pwdata_next = cmd_ram_rd_data;
@@ -388,7 +388,7 @@ always_comb begin
// enable queue // enable queue
cmd_ram_rd_addr = 6; cmd_ram_rd_addr = 6;
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h0000; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h0000;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = '0; m_apb_dp_ctrl_pwdata_next = '0;
@@ -408,7 +408,7 @@ always_comb begin
STATE_Q_DISABLE: begin STATE_Q_DISABLE: begin
// disable queue // disable queue
if (!m_apb_dp_ctrl_psel_reg) begin if (!m_apb_dp_ctrl_psel_reg) begin
m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 16'h0000; m_apb_dp_ctrl_paddr_next = block_base_addr_reg + 'h0000;
m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_psel_next = 1'b1;
m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1;
m_apb_dp_ctrl_pwdata_next = 32'h00000000; m_apb_dp_ctrl_pwdata_next = 32'h00000000;