bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

dma: Clean up casts in DMA PSDPRAM model

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-09-07 14:37:41 -07:00
parent e42a2dd8b4
commit 32ed95893c
1 changed files with 23 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
src/dma/tb/dma_psdp_ram.py
View File

@@ -318,11 +318,11 @@ class PsdpRamMasterWrite(Region):
while True: while True:
await clock_edge_event await clock_edge_event
cmd_ready_sample = self.bus.wr_cmd_ready.value cmd_ready_sample = int(self.bus.wr_cmd_ready.value)
done_sample = self.bus.wr_done.value done_sample = int(self.bus.wr_done.value)
if self.reset is not None and self.reset.value: if self.reset is not None and int(self.reset.value):
self.bus.wr_cmd_valid.setimmediatevalue(0) self.bus.wr_cmd_valid.value = 0
continue continue
# process segments # process segments
@@ -541,15 +541,15 @@ class PsdpRamMasterRead(Region):
while True: while True:
await clock_edge_event await clock_edge_event
cmd_ready_sample = self.bus.rd_cmd_ready.value cmd_ready_sample = int(self.bus.rd_cmd_ready.value)
resp_valid_sample = self.bus.rd_resp_valid.value resp_valid_sample = int(self.bus.rd_resp_valid.value)
if resp_valid_sample: if resp_valid_sample:
resp_data_sample = self.bus.rd_resp_data.value resp_data_sample = int(self.bus.rd_resp_data.value)
if self.reset is not None and self.reset.value: if self.reset is not None and int(self.reset.value):
self.bus.rd_cmd_valid.setimmediatevalue(0) self.bus.rd_cmd_valid.value = 0
self.bus.rd_resp_ready.setimmediatevalue(0) self.bus.rd_resp_ready.value = 0
cmd_valid = 0 cmd_valid = 0
resp_ready = 0 resp_ready = 0
continue continue
@@ -698,16 +698,16 @@ class PsdpRamWrite(Memory):
wr_done = 0 wr_done = 0
cmd_valid_sample = self.bus.wr_cmd_valid.value cmd_valid_sample = int(self.bus.wr_cmd_valid.value)
if cmd_valid_sample: if cmd_valid_sample:
cmd_be_sample = self.bus.wr_cmd_be.value cmd_be_sample = int(self.bus.wr_cmd_be.value)
cmd_addr_sample = self.bus.wr_cmd_addr.value cmd_addr_sample = int(self.bus.wr_cmd_addr.value)
cmd_data_sample = self.bus.wr_cmd_data.value cmd_data_sample = int(self.bus.wr_cmd_data.value)
if self.reset is not None and self.reset.value: if self.reset is not None and int(self.reset.value):
self.bus.wr_cmd_ready.setimmediatevalue(0) self.bus.wr_cmd_ready.value = 0
self.bus.wr_done.setimmediatevalue(0) self.bus.wr_done.value = 0
continue continue
# process segments # process segments
@@ -831,16 +831,16 @@ class PsdpRamRead(Memory):
while True: while True:
await clock_edge_event await clock_edge_event
cmd_valid_sample = self.bus.rd_cmd_valid.value cmd_valid_sample = int(self.bus.rd_cmd_valid.value)
if cmd_valid_sample: if cmd_valid_sample:
cmd_addr_sample = self.bus.rd_cmd_addr.value cmd_addr_sample = int(self.bus.rd_cmd_addr.value)
resp_ready_sample = self.bus.rd_resp_ready.value resp_ready_sample = int(self.bus.rd_resp_ready.value)
if self.reset is not None and self.reset.value: if self.reset is not None and int(self.reset.value):
self.bus.rd_cmd_ready.setimmediatevalue(0) self.bus.rd_cmd_ready.value = 0
self.bus.rd_resp_valid.setimmediatevalue(0) self.bus.rd_resp_valid.value = 0
cmd_ready = 0 cmd_ready = 0
resp_valid = 0 resp_valid = 0
continue continue