example/ZCU111: Add example design for ZCU111

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-09 17:08:38 -08:00 · 2025-02-23 17:32:21 -08:00
parent 27033384d9
commit 34266fe25d
12 changed files with 1399 additions and 0 deletions
--- a/example/ZCU111/fpga/rtl/fpga.sv
+++ b/example/ZCU111/fpga/rtl/fpga.sv
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "zynquplusRFSOC"
+)
+(
+    /*
+     * Clock: 125MHz LVDS
+     * Reset: Push button, active low
+     */
+    input  wire logic        clk_125mhz_p,
+    input  wire logic        clk_125mhz_n,
+    input  wire logic        reset,
+
+    /*
+     * GPIO
+     */
+    input  wire logic        btnu,
+    input  wire logic        btnl,
+    input  wire logic        btnd,
+    input  wire logic        btnr,
+    input  wire logic        btnc,
+    input  wire logic [7:0]  sw,
+    output wire logic [7:0]  led,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire logic        uart_rxd,
+    output wire logic        uart_txd,
+    input  wire logic        uart_rts,
+    output wire logic        uart_cts,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic [3:0]  sfp_rx_p,
+    input  wire logic [3:0]  sfp_rx_n,
+    output wire logic [3:0]  sfp_tx_p,
+    output wire logic [3:0]  sfp_tx_n,
+    input  wire logic        sfp_mgt_refclk_0_p,
+    input  wire logic        sfp_mgt_refclk_0_n,
+    output wire logic [3:0]  sfp_tx_disable_b
+);
+
+wire clk_125mhz_ibufg;
+wire clk_125mhz_bufg;
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = reset;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+clk_125mhz_ibufg_inst (
+   .O   (clk_125mhz_ibufg),
+   .I   (clk_125mhz_p),
+   .IB  (clk_125mhz_n) 
+);
+
+BUFG
+clk_125mhz_bufg_in_inst (
+    .I(clk_125mhz_ibufg),
+    .O(clk_125mhz_bufg)
+);
+
+// MMCM instance
+MMCME4_BASE #(
+    // 125 MHz input
+    .CLKIN1_PERIOD(8.0),
+    .REF_JITTER1(0.010),
+    // 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 125 MHz PFD * 10 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(10),
+    .CLKFBOUT_PHASE(0),
+    // 1250 MHz / 10 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(10),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 125 MHz input
+    .CLKIN1(clk_125mhz_bufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+// GPIO
+wire btnu_int;
+wire btnl_int;
+wire btnd_int;
+wire btnr_int;
+wire btnc_int;
+wire [7:0] sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(5+8),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+    .in({btnu,
+        btnl,
+        btnd,
+        btnr,
+        btnc,
+        sw}),
+    .out({btnu_int,
+        btnl_int,
+        btnd_int,
+        btnr_int,
+        btnc_int,
+        sw_int})
+);
+
+wire uart_rxd_int;
+wire uart_rts_int;
+
+taxi_sync_signal #(
+    .WIDTH(2),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({uart_rxd, uart_rts}),
+    .out({uart_rxd_int, uart_rts_int})
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+    .btnu(btnu_int),
+    .btnl(btnl_int),
+    .btnd(btnd_int),
+    .btnr(btnr_int),
+    .btnc(btnc_int),
+    .sw(sw_int),
+    .led(led),
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    .uart_rxd(uart_rxd_int),
+    .uart_txd(uart_txd),
+    .uart_rts(uart_rts_int),
+    .uart_cts(uart_cts),
+
+    /*
+     * Ethernet: SFP+
+     */
+    .sfp_rx_p(sfp_rx_p),
+    .sfp_rx_n(sfp_rx_n),
+    .sfp_tx_p(sfp_tx_p),
+    .sfp_tx_n(sfp_tx_n),
+    .sfp_mgt_refclk_0_p(sfp_mgt_refclk_0_p),
+    .sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
+
+    .sfp_tx_disable_b(sfp_tx_disable_b)
+);
+
+endmodule
+
+`resetall