diff --git a/README.md b/README.md
index ad6e3ee..5366ded 100644
--- a/README.md
+++ b/README.md
@@ -245,6 +245,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250)
 *  Xilinx Alveo U280 (Xilinx Virtex UltraScale+ XCU280)
 *  Xilinx Alveo X3/X3522 (Xilinx Virtex UltraScale+ XCUX35)
+*  Xilinx AC701 (Xilinx Artix 7 XC7A200T)
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
 *  Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
diff --git a/src/eth/example/AC701/fpga/README.md b/src/eth/example/AC701/fpga/README.md
new file mode 100644
index 0000000..53dcffc
--- /dev/null
+++ b/src/eth/example/AC701/fpga/README.md
@@ -0,0 +1,35 @@
+# Taxi Example Design for AC701
+
+## Introduction
+
+This example design targets the Xilinx AC701 FPGA board.
+
+The design places a looped-back MACs the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
+
+*  USB UART
+    *  XFCP (921600 baud)
+*  RJ-45 Ethernet port with Marvell 88E1116 PHY
+    *  Looped-back MAC via RGMII
+
+## Board details
+
+*  FPGA: XC7A200T-2FBG676C
+*  USB UART: Silicon Labs CP2103
+*  1000BASE-T PHY: Marvell 88E1116 via RGMII
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
diff --git a/src/eth/example/AC701/fpga/common/vivado.mk b/src/eth/example/AC701/fpga/common/vivado.mk
new file mode 100644
index 0000000..07c56e2
--- /dev/null
+++ b/src/eth/example/AC701/fpga/common/vivado.mk
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
diff --git a/src/eth/example/AC701/fpga/fpga/Makefile b/src/eth/example/AC701/fpga/fpga/Makefile
new file mode 100644
index 0000000..c2a7eaa
--- /dev/null
+++ b/src/eth/example/AC701/fpga/fpga/Makefile
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a200tfbg676-2
+FPGA_TOP = fpga
+FPGA_ARCH = artix7
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES += ../syn/fpga.xdc
+XDC_FILES += ../syn/gpio.xdc
+XDC_FILES += ../syn/i2c.xdc
+XDC_FILES += ../syn/phy.xdc
+XDC_FILES += ../syn/eth_rgmii.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+
+# Configuration
+#CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
diff --git a/src/eth/example/AC701/fpga/lib/taxi b/src/eth/example/AC701/fpga/lib/taxi
new file mode 120000
index 0000000..477cbaa
--- /dev/null
+++ b/src/eth/example/AC701/fpga/lib/taxi
@@ -0,0 +1 @@
+../../../../../../
\ No newline at end of file
diff --git a/src/eth/example/AC701/fpga/rtl/fpga.sv b/src/eth/example/AC701/fpga/rtl/fpga.sv
new file mode 100644
index 0000000..0bfbc85
--- /dev/null
+++ b/src/eth/example/AC701/fpga/rtl/fpga.sv
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "artix7",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1
+)
+(
+    /*
+     * Clock: 200MHz
+     * Reset: Push button, active high
+     */
+    input  wire logic        clk_200mhz_p,
+    input  wire logic        clk_200mhz_n,
+    input  wire logic        reset,
+
+    /*
+     * GPIO
+     */
+    input  wire logic        btnu,
+    input  wire logic        btnl,
+    input  wire logic        btnd,
+    input  wire logic        btnr,
+    input  wire logic        btnc,
+    input  wire logic [3:0]  sw,
+    output wire logic [3:0]  led,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire logic        uart_rxd,
+    output wire logic        uart_txd,
+    input  wire logic        uart_rts,
+    output wire logic        uart_cts,
+
+    /*
+     * I2C
+     */
+    inout  wire logic        i2c_scl,
+    inout  wire logic        i2c_sda,
+    output wire logic        i2c_mux_reset,
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire logic        phy_rx_clk,
+    input  wire logic [3:0]  phy_rxd,
+    input  wire logic        phy_rx_ctl,
+    output wire logic        phy_tx_clk,
+    output wire logic [3:0]  phy_txd,
+    output wire logic        phy_tx_ctl,
+    output wire logic        phy_reset_n
+);
+
+// Clock and reset
+
+wire clk_200mhz_ibufg;
+
+// Internal 125 MHz clock
+wire clk_mmcm_out;
+wire clk_int;
+wire clk90_mmcm_out;
+wire clk90_int;
+wire rst_int;
+
+wire clk_200mhz_mmcm_out;
+wire clk_200mhz_int;
+
+wire mmcm_rst = reset;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS
+clk_200mhz_ibufgds_inst(
+    .I(clk_200mhz_p),
+    .IB(clk_200mhz_n),
+    .O(clk_200mhz_ibufg)
+);
+
+// MMCM instance
+MMCME2_BASE #(
+    // 200 MHz input
+    .CLKIN1_PERIOD(5.0),
+    .REF_JITTER1(0.010),
+    // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 550 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1200 MHz)
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz VCO / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // 1000 MHz VCO / 8 = 125 MHz, 90 degrees
+    .CLKOUT1_DIVIDE(8),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    // 1000 MHz VCO / 5 = 200 MHz, 0 degrees
+    .CLKOUT2_DIVIDE(5),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 200 MHz input
+    .CLKIN1(clk_200mhz_ibufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_mmcm_out),
+    .CLKOUT0B(),
+    // 125 MHz, 90 degrees
+    .CLKOUT1(clk90_mmcm_out),
+    .CLKOUT1B(),
+    // 200 MHz, 0 degrees
+    .CLKOUT2(clk_200mhz_mmcm_out),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_bufg_inst (
+    .I(clk_mmcm_out),
+    .O(clk_int)
+);
+
+BUFG
+clk90_bufg_inst (
+    .I(clk90_mmcm_out),
+    .O(clk90_int)
+);
+
+BUFG
+clk_200mhz_bufg_inst (
+    .I(clk_200mhz_mmcm_out),
+    .O(clk_200mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_inst (
+    .clk(clk_int),
+    .rst(~mmcm_locked),
+    .out(rst_int)
+);
+
+// GPIO
+wire btnu_int;
+wire btnl_int;
+wire btnd_int;
+wire btnr_int;
+wire btnc_int;
+wire [3:0] sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(9),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_int),
+    .rst(rst_int),
+    .in({btnu,
+        btnl,
+        btnd,
+        btnr,
+        btnc,
+        sw}),
+    .out({btnu_int,
+        btnl_int,
+        btnd_int,
+        btnr_int,
+        btnc_int,
+        sw_int})
+);
+
+wire uart_rxd_int;
+wire uart_rts_int;
+
+taxi_sync_signal #(
+    .WIDTH(2),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_int),
+    .in({uart_rxd, uart_rts}),
+    .out({uart_rxd_int, uart_rts_int})
+);
+
+wire [3:0] led_int;
+
+// I2C
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+
+wire [3:0] phy_rxd_int;
+wire phy_rx_ctl_int;
+
+// IODELAY elements for RGMII interface to PHY
+IDELAYCTRL
+idelayctrl_inst (
+    .REFCLK(clk_200mhz_int),
+    .RST(rst_int),
+    .RDY()
+);
+
+for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
+
+    IDELAYE2 #(
+        .IDELAY_TYPE("FIXED")
+    )
+    idelay_inst (
+        .IDATAIN(phy_rxd[n]),
+        .DATAOUT(phy_rxd_int[n]),
+        .DATAIN(1'b0),
+        .C(1'b0),
+        .CE(1'b0),
+        .INC(1'b0),
+        .CINVCTRL(1'b0),
+        .CNTVALUEIN(5'd0),
+        .CNTVALUEOUT(),
+        .LD(1'b0),
+        .LDPIPEEN(1'b0),
+        .REGRST(1'b0)
+    );
+
+end
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rx_ctl_idelay (
+    .IDATAIN(phy_rx_ctl),
+    .DATAOUT(phy_rx_ctl_int),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk(clk_int),
+    .clk90(clk90_int),
+    .rst(rst_int),
+
+    /*
+     * GPIO
+     */
+    .btnu(btnu_int),
+    .btnl(btnl_int),
+    .btnd(btnd_int),
+    .btnr(btnr_int),
+    .btnc(btnc_int),
+    .sw(sw_int),
+    .led(led_int),
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    .uart_rxd(uart_rxd_int),
+    .uart_txd(uart_txd),
+    .uart_rts(uart_rts_int),
+    .uart_cts(uart_cts),
+
+    /*
+     * I2C
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o),
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    .phy_rx_clk(phy_rx_clk),
+    .phy_rxd(phy_rxd_int),
+    .phy_rx_ctl(phy_rx_ctl_int),
+    .phy_tx_clk(phy_tx_clk),
+    .phy_txd(phy_txd),
+    .phy_tx_ctl(phy_tx_ctl),
+    .phy_reset_n(phy_reset_n)
+);
+
+endmodule
+
+`resetall
diff --git a/src/eth/example/AC701/fpga/rtl/fpga_core.sv b/src/eth/example/AC701/fpga/rtl/fpga_core.sv
new file mode 100644
index 0000000..8662468
--- /dev/null
+++ b/src/eth/example/AC701/fpga/rtl/fpga_core.sv
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "kintex7",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire logic        clk,
+    input  wire logic        clk90,
+    input  wire logic        rst,
+
+    /*
+     * GPIO
+     */
+    input  wire logic        btnu,
+    input  wire logic        btnl,
+    input  wire logic        btnd,
+    input  wire logic        btnr,
+    input  wire logic        btnc,
+    input  wire logic [3:0]  sw,
+    output wire logic [3:0]  led,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire logic        uart_rxd,
+    output wire logic        uart_txd,
+    input  wire logic        uart_rts,
+    output wire logic        uart_cts,
+
+    /*
+     * I2C
+     */
+    input  wire logic        i2c_scl_i,
+    output wire logic        i2c_scl_o,
+    input  wire logic        i2c_sda_i,
+    output wire logic        i2c_sda_o,
+
+    /*
+     * Ethernet: 1000BASE-T
+     */
+    input  wire logic        phy_rx_clk,
+    input  wire logic [3:0]  phy_rxd,
+    input  wire logic        phy_rx_ctl,
+    output wire logic        phy_tx_clk,
+    output wire logic [3:0]  phy_txd,
+    output wire logic        phy_tx_ctl,
+    output wire logic        phy_reset_n
+);
+
+assign led = sw;
+
+// XFCP
+assign uart_cts = 1'b0;
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
+
+taxi_xfcp_if_uart #(
+    .TX_FIFO_DEPTH(512),
+    .RX_FIFO_DEPTH(512)
+)
+xfcp_if_uart_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * UART interface
+     */
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+
+    /*
+     * XFCP downstream interface
+     */
+    .xfcp_dsp_ds(xfcp_ds),
+    .xfcp_dsp_us(xfcp_us),
+
+    /*
+     * Configuration
+     */
+    .prescale(16'(125000000/921600))
+);
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2]();
+
+taxi_xfcp_switch #(
+    .XFCP_ID_STR("AC701"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR("Taxi example"),
+    .PORTS($size(xfcp_sw_us))
+)
+xfcp_sw_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_ds),
+    .xfcp_usp_us(xfcp_us),
+
+    /*
+     * XFCP downstream ports
+     */
+    .xfcp_dsp_ds(xfcp_sw_ds),
+    .xfcp_dsp_us(xfcp_sw_us)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
+
+taxi_xfcp_mod_stats #(
+    .XFCP_ID_STR("Statistics"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR(""),
+    .STAT_COUNT_W(64),
+    .STAT_PIPELINE(2)
+)
+xfcp_stats_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[0]),
+    .xfcp_usp_us(xfcp_sw_us[0]),
+
+    /*
+     * Statistics increment input
+     */
+    .s_axis_stat(axis_stat)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[1]();
+
+taxi_axis_arb_mux #(
+    .S_COUNT($size(axis_eth_stat)),
+    .UPDATE_TID(1'b0),
+    .ARB_ROUND_ROBIN(1'b1),
+    .ARB_LSB_HIGH_PRIO(1'b0)
+)
+stat_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream inputs (sink)
+     */
+    .s_axis(axis_eth_stat),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(axis_stat)
+);
+
+// I2C
+taxi_xfcp_mod_i2c_master #(
+    .XFCP_EXT_ID_STR("I2C"),
+    .DEFAULT_PRESCALE(16'(125000000/200000/4))
+)
+xfcp_mod_i2c_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[1]),
+    .xfcp_usp_us(xfcp_sw_us[1]),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o)
+);
+
+// BASE-T PHY
+assign phy_reset_n = !rst;
+
+taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
+
+taxi_eth_mac_1g_rgmii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .PADDING_EN(1),
+    .MIN_FRAME_LEN(64),
+    .STAT_EN(1),
+    .STAT_TX_LEVEL(1),
+    .STAT_RX_LEVEL(1),
+    .STAT_ID_BASE(0),
+    .STAT_UPDATE_PERIOD(1024),
+    .STAT_STR_EN(1),
+    .STAT_PREFIX_STR("BASET"),
+    .TX_FIFO_DEPTH(16384),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_DEPTH(16384),
+    .RX_FRAME_FIFO(1)
+)
+eth_mac_inst (
+    .gtx_clk(clk),
+    .gtx_clk90(clk90),
+    .gtx_rst(rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_eth),
+    .m_axis_tx_cpl(axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_eth),
+
+    /*
+     * RGMII interface
+     */
+    .rgmii_rx_clk(phy_rx_clk),
+    .rgmii_rxd(phy_rxd),
+    .rgmii_rx_ctl(phy_rx_ctl),
+    .rgmii_tx_clk(phy_tx_clk),
+    .rgmii_txd(phy_txd),
+    .rgmii_tx_ctl(phy_tx_ctl),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(clk),
+    .stat_rst(rst),
+    .m_axis_stat(axis_eth_stat[0]),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(),
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .link_speed(),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(16'd9218),
+    .cfg_tx_ifg(8'd12),
+    .cfg_tx_enable(1'b1),
+    .cfg_rx_max_pkt_len(16'd9218),
+    .cfg_rx_enable(1'b1)
+);
+
+endmodule
+
+`resetall
diff --git a/src/eth/example/AC701/fpga/syn/eth_rgmii.xdc b/src/eth/example/AC701/fpga/syn/eth_rgmii.xdc
new file mode 100644
index 0000000..3dd7923
--- /dev/null
+++ b/src/eth/example/AC701/fpga/syn/eth_rgmii.xdc
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Ethernet constraints
+
+# IDELAY from PHY chip (RGMII)
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}]
+
+# MMCM phase (RGMII)
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
diff --git a/src/eth/example/AC701/fpga/syn/fpga.xdc b/src/eth/example/AC701/fpga/syn/fpga.xdc
new file mode 100644
index 0000000..2ad9d6f
--- /dev/null
+++ b/src/eth/example/AC701/fpga/syn/fpga.xdc
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx AC701 board
+# part: xc7a200tfbg676-2
+
+# General configuration
+set_property CFGBVS VCCO                      [current_design]
+set_property CONFIG_VOLTAGE 3.3               [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true  [current_design]
+
+# System clocks
+# 200 MHz system clock
+set_property -dict {LOC R3  IOSTANDARD LVDS_25} [get_ports clk_200mhz_p] ;# from SiT9102 U51.4
+set_property -dict {LOC P3  IOSTANDARD LVDS_25} [get_ports clk_200mhz_n] ;# from SiT9102 U51.5
+create_clock -period 5.000 -name clk_200mhz [get_ports clk_200mhz_p]
+
+# Si570 user clock (156.25 MHz default)
+#set_property -dict {LOC M21  IOSTANDARD LVDS_25} [get_ports clk_user_p] ;# from Si570 U34.4
+#set_property -dict {LOC M22  IOSTANDARD LVDS_25} [get_ports clk_user_n] ;# from Si570 U34.5
+#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
+
+# User SMA clock
+#set_property -dict {LOC J23 IOSTANDARD LVDS_25} [get_ports clk_user_sma_p] ;# from J31
+#set_property -dict {LOC H23 IOSTANDARD LVDS_25} [get_ports clk_user_sma_n] ;# from J32
+#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
+
+# User SMA GPIO J33/J34
+#set_property -dict {LOC T8  IOSTANDARD LVDS_25} [get_ports user_sma_gpio_p] ;# J33
+#set_property -dict {LOC T7  IOSTANDARD LVDS_25} [get_ports user_sma_gpio_n] ;# J34
diff --git a/src/eth/example/AC701/fpga/syn/gpio.xdc b/src/eth/example/AC701/fpga/syn/gpio.xdc
new file mode 100644
index 0000000..3cf70c8
--- /dev/null
+++ b/src/eth/example/AC701/fpga/syn/gpio.xdc
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx AC701 board
+# part: xc7a200tfbg676-2
+
+# LEDs
+set_property -dict {LOC M26  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# to DS2
+set_property -dict {LOC T24  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# to DS3
+set_property -dict {LOC T25  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# to DS4
+set_property -dict {LOC R26  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# to DS5
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Reset button
+set_property -dict {LOC U4   IOSTANDARD LVCMOS15} [get_ports reset] ;# from SW7
+
+set_false_path -from [get_ports {reset}]
+set_input_delay 0 [get_ports {reset}]
+
+# Push buttons
+set_property -dict {LOC P6   IOSTANDARD LVCMOS15} [get_ports btnu] ;# from SW3
+set_property -dict {LOC R5   IOSTANDARD LVCMOS15} [get_ports btnl] ;# from SW7
+set_property -dict {LOC T5   IOSTANDARD LVCMOS15} [get_ports btnd] ;# from SW5
+set_property -dict {LOC U5   IOSTANDARD LVCMOS15} [get_ports btnr] ;# from SW4
+set_property -dict {LOC U6   IOSTANDARD LVCMOS15} [get_ports btnc] ;# from SW6
+
+set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
+set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
+
+# DIP switches
+set_property -dict {LOC R8   IOSTANDARD LVCMOS15} [get_ports {sw[0]}] ;# from SW2.1
+set_property -dict {LOC P8   IOSTANDARD LVCMOS15} [get_ports {sw[1]}] ;# from SW2.2
+set_property -dict {LOC R7   IOSTANDARD LVCMOS15} [get_ports {sw[2]}] ;# from SW2.3
+set_property -dict {LOC R6   IOSTANDARD LVCMOS15} [get_ports {sw[3]}] ;# from SW2.4
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# PMOD
+#set_property -dict {LOC P26  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod[0]}] ;# J48.1
+#set_property -dict {LOC T22  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod[1]}] ;# J48.2
+#set_property -dict {LOC R22  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod[2]}] ;# J48.3
+#set_property -dict {LOC T23  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod[3]}] ;# J48.4
+
+#set_false_path -to [get_ports {pmod[*]}]
+#set_output_delay 0 [get_ports {pmod[*]}]
+
+# UART (U12 CP2103)
+set_property -dict {LOC U19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U44.24 RXD_I
+set_property -dict {LOC T19  IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U44.25 TXD_O
+set_property -dict {LOC V19  IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U44.23 RTS_O_B
+set_property -dict {LOC W19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U44.22 CTS_I_B
+
+set_false_path -to [get_ports {uart_txd uart_cts}]
+set_output_delay 0 [get_ports {uart_txd uart_cts}]
+set_false_path -from [get_ports {uart_rxd uart_rts}]
+set_input_delay 0 [get_ports {uart_rxd uart_rts}]
diff --git a/src/eth/example/AC701/fpga/syn/i2c.xdc b/src/eth/example/AC701/fpga/syn/i2c.xdc
new file mode 100644
index 0000000..914fad2
--- /dev/null
+++ b/src/eth/example/AC701/fpga/syn/i2c.xdc
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx AC701 board
+# part: xc7a200tfbg676-2
+
+# I2C interface
+set_property -dict {LOC N18  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC K25  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC R17  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
+
+set_false_path -to [get_ports {i2c_sda i2c_scl}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
diff --git a/src/eth/example/AC701/fpga/syn/phy.xdc b/src/eth/example/AC701/fpga/syn/phy.xdc
new file mode 100644
index 0000000..212df2d
--- /dev/null
+++ b/src/eth/example/AC701/fpga/syn/phy.xdc
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx AC701 board
+# part: xc7a200tfbg676-2
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {LOC U21  IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# from U12.53 RX_CLK
+set_property -dict {LOC U17  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U12.50 RXD0
+set_property -dict {LOC V17  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U12.51 RXD1
+set_property -dict {LOC V16  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U12.54 RXD2
+set_property -dict {LOC V14  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U12.55 RXD3
+set_property -dict {LOC U14  IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# from U12.49 RX_CTRL
+set_property -dict {LOC U22  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports phy_tx_clk] ;# from U12.60 TX_CLK
+set_property -dict {LOC U16  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}] ;# from U12.58 TXD0
+set_property -dict {LOC U15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}] ;# from U12.59 TXD1
+set_property -dict {LOC T18  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}] ;# from U12.61 TXD2
+set_property -dict {LOC T17  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}] ;# from U12.62 TXD3
+set_property -dict {LOC T15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl] ;# from U12.63 TX_CTRL
+set_property -dict {LOC V18  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# from U12.10 RESET_B
+#set_property -dict {LOC T14  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# from U12.45 MDIO
+#set_property -dict {LOC W18  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# from U12.48 MDC
+
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+
+set_false_path -to [get_ports {phy_reset_n}]
+set_output_delay 0 [get_ports {phy_reset_n}]
+
+#set_false_path -to [get_ports {phy_mdio phy_mdc}]
+#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
+#set_false_path -from [get_ports {phy_mdio}]
+#set_input_delay 0 [get_ports {phy_mdio}]
diff --git a/src/eth/example/AC701/fpga/tb/fpga_core/Makefile b/src/eth/example/AC701/fpga/tb/fpga_core/Makefile
new file mode 100644
index 0000000..9f29be3
--- /dev/null
+++ b/src/eth/example/AC701/fpga/tb/fpga_core/Makefile
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"artix7\""
+export PARAM_USE_CLK90 := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/src/eth/example/AC701/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/AC701/fpga/tb/fpga_core/test_fpga_core.py
new file mode 100644
index 0000000..8664a8d
--- /dev/null
+++ b/src/eth/example/AC701/fpga/tb/fpga_core/test_fpga_core.py
@@ -0,0 +1,200 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, Combine
+
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, RgmiiPhy
+from cocotbext.uart import UartSource, UartSink
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # cocotb.start_soon(Clock(dut.phy_sgmii_clk, 8, units="ns").start())
+
+        self.baset_phy = RgmiiPhy(dut.phy_txd, dut.phy_tx_ctl, dut.phy_tx_clk,
+            dut.phy_rxd, dut.phy_rx_ctl, dut.phy_rx_clk, speed=speed)
+
+        self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
+        self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
+
+        dut.btnu.setimmediatevalue(0)
+        dut.btnl.setimmediatevalue(0)
+        dut.btnd.setimmediatevalue(0)
+        dut.btnr.setimmediatevalue(0)
+        dut.btnc.setimmediatevalue(0)
+        dut.sw.setimmediatevalue(0)
+        dut.uart_rts.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_clk())
+
+    async def init(self):
+
+        self.dut.rst.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 0
+
+    async def _run_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.clk.value = 1
+            await t
+            self.dut.clk90.value = 1
+            await t
+            self.dut.clk.value = 0
+            await t
+            self.dut.clk90.value = 0
+            await t
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    tb.log.info("Start BASE-T MAC loopback test")
+
+    tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+        os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"artix7\""
+    parameters['USE_CLK90'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )