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cndm: Update designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-05-12 12:09:48 -07:00
parent 09c583c7be
commit 39a53f0dd7
11 changed files with 67 additions and 56 deletions
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9
src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
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@@ -347,9 +347,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// PHY parameters // PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -478,6 +476,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -524,10 +523,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),

9
src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
View File

@@ -469,9 +469,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -600,6 +598,7 @@ sfp_mac_inst (
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -646,10 +645,12 @@ sfp_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{2{16'd9218}}), .cfg_tx_pad_en('{2{1'b1}}),
.cfg_tx_min_pkt_len('{2{8'd60-1}}),
.cfg_tx_max_pkt_len('{2{16'd9218-1}}),
.cfg_tx_ifg('{2{8'd12}}), .cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('{2{1'b1}}), .cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}), .cfg_rx_max_pkt_len('{2{16'd9218-1}}),
.cfg_rx_enable('{2{1'b1}}), .cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}), .cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}), .cfg_rx_prbs31_enable('{2{1'b0}}),

9
src/cndm/board/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -515,9 +515,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -652,6 +650,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -698,10 +697,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),

9
src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.sv
View File

@@ -502,9 +502,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -639,6 +637,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -685,10 +684,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),

17
src/cndm/board/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -492,8 +492,6 @@ taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
taxi_eth_mac_1g_fifo #( taxi_eth_mac_1g_fifo #(
.PADDING_EN(1),
.MIN_FRAME_LEN(64),
.STAT_EN(1), .STAT_EN(1),
.STAT_TX_LEVEL(1), .STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1), .STAT_RX_LEVEL(1),
@@ -566,10 +564,12 @@ eth_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len(16'd9218), .cfg_tx_pad_en(1'b1),
.cfg_tx_min_pkt_len(8'd60-1),
.cfg_tx_max_pkt_len(16'd9218-1),
.cfg_tx_ifg(8'd12), .cfg_tx_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(1'b1),
.cfg_rx_max_pkt_len(16'd9218), .cfg_rx_max_pkt_len(16'd9218-1),
.cfg_rx_enable(1'b1) .cfg_rx_enable(1'b1)
); );
@@ -691,9 +691,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -829,6 +827,7 @@ sfp_mac_inst (
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -875,10 +874,12 @@ sfp_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{2{16'd9218}}), .cfg_tx_pad_en('{2{1'b1}}),
.cfg_tx_min_pkt_len('{2{8'd60-1}}),
.cfg_tx_max_pkt_len('{2{16'd9218-1}}),
.cfg_tx_ifg('{2{8'd12}}), .cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('{2{1'b1}}), .cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}), .cfg_rx_max_pkt_len('{2{16'd9218-1}}),
.cfg_rx_enable('{2{1'b1}}), .cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}), .cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}), .cfg_rx_prbs31_enable('{2{1'b0}}),

9
src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv
View File

@@ -377,9 +377,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -514,6 +512,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -560,10 +559,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),

9
src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
View File

@@ -557,9 +557,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -694,6 +692,7 @@ qsfp_mac_inst (
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -740,10 +739,12 @@ qsfp_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{4{16'd9218}}), .cfg_tx_pad_en('{4{1'b1}}),
.cfg_tx_min_pkt_len('{4{8'd60-1}}),
.cfg_tx_max_pkt_len('{4{16'd9218-1}}),
.cfg_tx_ifg('{4{8'd12}}), .cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('{4{1'b1}}), .cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}), .cfg_rx_max_pkt_len('{4{16'd9218-1}}),
.cfg_rx_enable('{4{1'b1}}), .cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}), .cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}), .cfg_rx_prbs31_enable('{4{1'b0}}),

17
src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -361,8 +361,6 @@ taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
taxi_eth_mac_1g_fifo #( taxi_eth_mac_1g_fifo #(
.PADDING_EN(1),
.MIN_FRAME_LEN(64),
.STAT_EN(1), .STAT_EN(1),
.STAT_TX_LEVEL(1), .STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1), .STAT_RX_LEVEL(1),
@@ -435,10 +433,12 @@ eth_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len(16'd9218), .cfg_tx_pad_en(1'b1),
.cfg_tx_min_pkt_len(8'd60-1),
.cfg_tx_max_pkt_len(16'd9218-1),
.cfg_tx_ifg(8'd12), .cfg_tx_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(1'b1),
.cfg_rx_max_pkt_len(16'd9218), .cfg_rx_max_pkt_len(16'd9218-1),
.cfg_rx_enable(1'b1) .cfg_rx_enable(1'b1)
); );
@@ -572,9 +572,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -709,6 +707,7 @@ qsfp_mac_inst (
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -755,10 +754,12 @@ qsfp_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{4{16'd9218}}), .cfg_tx_pad_en('{4{1'b1}}),
.cfg_tx_min_pkt_len('{4{8'd60-1}}),
.cfg_tx_max_pkt_len('{4{16'd9218-1}}),
.cfg_tx_ifg('{4{8'd12}}), .cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('{4{1'b1}}), .cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}), .cfg_rx_max_pkt_len('{4{16'd9218-1}}),
.cfg_rx_enable('{4{1'b1}}), .cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}), .cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}), .cfg_rx_prbs31_enable('{4{1'b0}}),

17
src/cndm/board/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -385,8 +385,6 @@ taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
taxi_eth_mac_1g_fifo #( taxi_eth_mac_1g_fifo #(
.PADDING_EN(1),
.MIN_FRAME_LEN(64),
.STAT_EN(1), .STAT_EN(1),
.STAT_TX_LEVEL(1), .STAT_TX_LEVEL(1),
.STAT_RX_LEVEL(1), .STAT_RX_LEVEL(1),
@@ -459,10 +457,12 @@ eth_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len(16'd9218), .cfg_tx_pad_en(1'b1),
.cfg_tx_min_pkt_len(8'd60-1),
.cfg_tx_max_pkt_len(16'd9218-1),
.cfg_tx_ifg(8'd12), .cfg_tx_ifg(8'd12),
.cfg_tx_enable(1'b1), .cfg_tx_enable(1'b1),
.cfg_rx_max_pkt_len(16'd9218), .cfg_rx_max_pkt_len(16'd9218-1),
.cfg_rx_enable(1'b1) .cfg_rx_enable(1'b1)
); );
@@ -765,9 +765,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -902,6 +900,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -948,10 +947,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),

9
src/cndm/board/ZCU106/fpga/rtl/fpga_core.sv
View File

@@ -378,9 +378,7 @@ taxi_eth_mac_25g_us #(
// PHY parameters // PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -516,6 +514,7 @@ sfp_mac_inst (
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -562,10 +561,12 @@ sfp_mac_inst (
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{2{16'd9218}}), .cfg_tx_pad_en('{2{1'b1}}),
.cfg_tx_min_pkt_len('{2{8'd60-1}}),
.cfg_tx_max_pkt_len('{2{16'd9218-1}}),
.cfg_tx_ifg('{2{8'd12}}), .cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('{2{1'b1}}), .cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}), .cfg_rx_max_pkt_len('{2{16'd9218-1}}),
.cfg_rx_enable('{2{1'b1}}), .cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}), .cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}), .cfg_rx_prbs31_enable('{2{1'b0}}),

9
src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv
View File

@@ -390,9 +390,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config // MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS), .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W), .DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1), .DIC_EN(1'b1),
.MIN_FRAME_LEN(64),
.PTP_TS_EN(PTP_TS_EN), .PTP_TS_EN(PTP_TS_EN),
.PTP_TD_EN(PTP_TS_EN), .PTP_TD_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
@@ -521,6 +519,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
.stat_tx_pkt_vlan(), .stat_tx_pkt_vlan(),
.stat_tx_pkt_good(), .stat_tx_pkt_good(),
.stat_tx_pkt_bad(), .stat_tx_pkt_bad(),
.stat_tx_pad_frame(),
.stat_tx_err_oversize(), .stat_tx_err_oversize(),
.stat_tx_err_user(), .stat_tx_err_user(),
.stat_tx_err_underflow(), .stat_tx_err_underflow(),
@@ -567,10 +566,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
/* /*
* Configuration * Configuration
*/ */
.cfg_tx_max_pkt_len('{CNT{16'd9218}}), .cfg_tx_pad_en('{CNT{1'b1}}),
.cfg_tx_min_pkt_len('{CNT{8'd60-1}}),
.cfg_tx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_tx_ifg('{CNT{8'd12}}), .cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('{CNT{1'b1}}), .cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}), .cfg_rx_max_pkt_len('{CNT{16'd9218-1}}),
.cfg_rx_enable('{CNT{1'b1}}), .cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}), .cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}), .cfg_rx_prbs31_enable('{CNT{1'b0}}),