From 3ac7484e163a7b0ab25975f32e26a8e68e601cfc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 8 Mar 2026 14:42:31 -0700 Subject: [PATCH] pcie: Clean up array init Signed-off-by: Alex Forencich --- src/pcie/rtl/taxi_pcie_msix_apb.sv | 13 ++----------- src/pcie/rtl/taxi_pcie_msix_axil.sv | 13 ++----------- 2 files changed, 4 insertions(+), 22 deletions(-) diff --git a/src/pcie/rtl/taxi_pcie_msix_apb.sv b/src/pcie/rtl/taxi_pcie_msix_apb.sv index 6e81101..0de1ac9 100644 --- a/src/pcie/rtl/taxi_pcie_msix_apb.sv +++ b/src/pcie/rtl/taxi_pcie_msix_apb.sv @@ -139,11 +139,11 @@ logic msix_mask_reg = 1'b0; // MSI-X table (* ramstyle = "no_rw_check, mlab" *) -logic [63:0] tbl_mem[2**TBL_ADDR_W]; +logic [63:0] tbl_mem[2**TBL_ADDR_W] = '{default: '0}; // MSI-X PBA (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -logic [63:0] pba_mem[2**PBA_ADDR_W]; +logic [63:0] pba_mem[2**PBA_ADDR_W] = '{default: '0}; logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next; logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next; @@ -176,15 +176,6 @@ assign tx_wr_req_tlp.valid = tx_wr_req_tlp_valid_reg; assign tx_wr_req_tlp.sop = 1'b1; assign tx_wr_req_tlp.eop = 1'b1; -initial begin - for (integer i = 0; i < 2**TBL_ADDR_W; i = i + 1) begin - tbl_mem[i] = '0; - end - for (integer i = 0; i < 2**PBA_ADDR_W; i = i + 1) begin - pba_mem[i] = '0; - end -end - always_comb begin state_next = STATE_IDLE; diff --git a/src/pcie/rtl/taxi_pcie_msix_axil.sv b/src/pcie/rtl/taxi_pcie_msix_axil.sv index 40bac83..bcb1251 100644 --- a/src/pcie/rtl/taxi_pcie_msix_axil.sv +++ b/src/pcie/rtl/taxi_pcie_msix_axil.sv @@ -149,11 +149,11 @@ logic msix_mask_reg = 1'b0; // MSI-X table (* ramstyle = "no_rw_check, mlab" *) -logic [63:0] tbl_mem[2**TBL_ADDR_W]; +logic [63:0] tbl_mem[2**TBL_ADDR_W] = '{default: '0}; // MSI-X PBA (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -logic [63:0] pba_mem[2**PBA_ADDR_W]; +logic [63:0] pba_mem[2**PBA_ADDR_W] = '{default: '0}; logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next; logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next; @@ -194,15 +194,6 @@ assign tx_wr_req_tlp.valid = tx_wr_req_tlp_valid_reg; assign tx_wr_req_tlp.sop = 1'b1; assign tx_wr_req_tlp.eop = 1'b1; -initial begin - for (integer i = 0; i < 2**TBL_ADDR_W; i = i + 1) begin - tbl_mem[i] = '0; - end - for (integer i = 0; i < 2**PBA_ADDR_W; i = i + 1) begin - pba_mem[i] = '0; - end -end - always_comb begin state_next = STATE_IDLE;