diff --git a/README.md b/README.md index 904d3b5..6f0d321 100644 --- a/README.md +++ b/README.md @@ -31,6 +31,7 @@ To facilitate the dual-license model, contributions to the project can only be a * AXI * SV interface for AXI * AXI to AXI lite adapter + * Interconnect * Register slice * Width converter * Synchronous FIFO diff --git a/src/axi/rtl/taxi_axi_interconnect.f b/src/axi/rtl/taxi_axi_interconnect.f new file mode 100644 index 0000000..6f354b3 --- /dev/null +++ b/src/axi/rtl/taxi_axi_interconnect.f @@ -0,0 +1,6 @@ +taxi_axi_interconnect.sv +taxi_axi_interconnect_rd.sv +taxi_axi_interconnect_wr.sv +taxi_axi_if.sv +../lib/taxi/src/prim/rtl/taxi_arbiter.sv +../lib/taxi/src/prim/rtl/taxi_penc.sv diff --git a/src/axi/rtl/taxi_axi_interconnect.sv b/src/axi/rtl/taxi_axi_interconnect.sv new file mode 100644 index 0000000..b18ef42 --- /dev/null +++ b/src/axi/rtl/taxi_axi_interconnect.sv @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 interconnect + */ +module taxi_axi_interconnect # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Read connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}}, + // Write connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interfaces + */ + taxi_axi_if.wr_slv s_axi_wr[S_COUNT], + taxi_axi_if.rd_slv s_axi_rd[S_COUNT], + + /* + * AXI4 master interfaces + */ + taxi_axi_if.wr_mst m_axi_wr[M_COUNT], + taxi_axi_if.rd_mst m_axi_rd[M_COUNT] +); + +taxi_axi_interconnect_wr #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT_WR), + .M_SECURE(M_SECURE) +) +wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interfaces + */ + .s_axi_wr(s_axi_wr), + + /* + * AXI4 master interfaces + */ + .m_axi_wr(m_axi_wr) +); + +taxi_axi_interconnect_rd #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT_RD), + .M_SECURE(M_SECURE) +) +rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interfaces + */ + .s_axi_rd(s_axi_rd), + + /* + * AXI4 master interfaces + */ + .m_axi_rd(m_axi_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_interconnect_rd.sv b/src/axi/rtl/taxi_axi_interconnect_rd.sv new file mode 100644 index 0000000..9033cce --- /dev/null +++ b/src/axi/rtl/taxi_axi_interconnect_rd.sv @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 interconnect + */ +module taxi_axi_interconnect_rd # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // Number of regions per master interface + parameter M_REGIONS = 1, + // TODO fix parametrization once verilator issue 5890 is fixed + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Read connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interfaces + */ + taxi_axi_if.rd_slv s_axi_rd[S_COUNT], + + /* + * AXI4 master interfaces + */ + taxi_axi_if.rd_mst m_axi_rd[M_COUNT] +); + +// extract parameters +localparam DATA_W = s_axi_rd.DATA_W; +localparam S_ADDR_W = s_axi_rd.ADDR_W; +localparam STRB_W = s_axi_rd.STRB_W; +localparam S_ID_W = s_axi_rd.ID_W; +localparam M_ID_W = m_axi_rd.ID_W; +localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN; +localparam ARUSER_W = s_axi_rd.ARUSER_W; +localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN; +localparam RUSER_W = s_axi_rd.RUSER_W; + +localparam CL_S_COUNT = $clog2(S_COUNT); +localparam CL_M_COUNT = $clog2(M_COUNT); +localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1; +localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1; + +localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W; +localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT; +localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE; + +// default address computation +function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy); + logic [ADDR_W-1:0] base; + logic [ADDR_W-1:0] width; + logic [ADDR_W-1:0] size; + logic [ADDR_W-1:0] mask; + begin + calcBaseAddrs = '0; + base = 0; + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + width = M_ADDR_W_INT[i]; + mask = {ADDR_W{1'b1}} >> (ADDR_W - width); + size = mask + 1; + if (width > 0) begin + if ((base & mask) != 0) begin + base = base + size - (base & mask); // align + end + calcBaseAddrs[i] = base; + base = base + size; // increment + end + end + end +endfunction + +localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0); + +// check configuration +if (s_axi_rd.ADDR_W != ADDR_W) + $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)"); + +if (m_axi_rd.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axi_rd.STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +initial begin + if (M_REGIONS < 1 || M_REGIONS > 16) begin + $error("Error: M_REGIONS must be between 1 and 16 (instance %m)"); + $finish; + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + /* verilator lint_off UNSIGNED */ + if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin + $error("Error: address width out of range (instance %m)"); + $finish; + end + /* verilator lint_on UNSIGNED */ + end + + $display("Addressing configuration for axi_interconnect instance %m"); + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if (M_ADDR_W_INT[i] != 0) begin + $display("%2d (%2d): %x / %02d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin + $display("Region not aligned:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $error("Error: address range not aligned (instance %m)"); + $finish; + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin + if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])))) + && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin + $display("Overlapping regions:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $display("%2d (%2d): %x / %2d -- %x-%x", + j/M_REGIONS, j%M_REGIONS, + M_BASE_ADDR_INT[j], + M_ADDR_W_INT[j], + M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]), + M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])) + ); + $error("Error: address ranges overlap (instance %m)"); + $finish; + end + end + end + end +end + +localparam logic [2:0] + STATE_IDLE = 3'd0, + STATE_DECODE = 3'd1, + STATE_READ = 3'd2, + STATE_READ_DROP = 3'd3, + STATE_WAIT_IDLE = 3'd4; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +logic match; + +logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next; +logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next; +logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next; +logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next; +logic [7:0] axi_len_reg = 8'd0, axi_len_next; +logic [2:0] axi_size_reg = 3'd0, axi_size_next; +logic [1:0] axi_burst_reg = 2'd0, axi_burst_next; +logic axi_lock_reg = 1'b0, axi_lock_next; +logic [3:0] axi_cache_reg = 4'd0, axi_cache_next; +logic [2:0] axi_prot_reg = 3'b000, axi_prot_next; +logic [3:0] axi_qos_reg = 4'd0, axi_qos_next; +logic [3:0] axi_region_reg = 4'd0, axi_region_next; +logic [ARUSER_W-1:0] axi_aruser_reg = '0, axi_aruser_next; + +logic [S_COUNT-1:0] s_axi_arready_reg = '0, s_axi_arready_next; + +logic [M_COUNT-1:0] m_axi_arvalid_reg = '0, m_axi_arvalid_next; +logic [M_COUNT-1:0] m_axi_rready_reg = '0, m_axi_rready_next; + +// internal datapath +logic [S_ID_W-1:0] s_axi_rid_int; +logic [DATA_W-1:0] s_axi_rdata_int; +logic [1:0] s_axi_rresp_int; +logic s_axi_rlast_int; +logic [RUSER_W-1:0] s_axi_ruser_int; +logic [S_COUNT-1:0] s_axi_rvalid_int; +logic s_axi_rready_int_reg = 1'b0; +wire s_axi_rready_int_early; + +// unpack interface array +wire [S_ID_W-1:0] s_axi_arid[S_COUNT]; +wire [ADDR_W-1:0] s_axi_araddr[S_COUNT]; +wire [7:0] s_axi_arlen[S_COUNT]; +wire [2:0] s_axi_arsize[S_COUNT]; +wire [1:0] s_axi_arburst[S_COUNT]; +wire s_axi_arlock[S_COUNT]; +wire [3:0] s_axi_arcache[S_COUNT]; +wire [2:0] s_axi_prot[S_COUNT]; +wire [3:0] s_axi_arqos[S_COUNT]; +wire [ARUSER_W-1:0] s_axi_aruser[S_COUNT]; +wire [S_COUNT-1:0] s_axi_arvalid; + +wire [M_COUNT-1:0] m_axi_arready; +wire [M_ID_W-1:0] m_axi_rid[M_COUNT]; +wire [DATA_W-1:0] m_axi_rdata[M_COUNT]; +wire [1:0] m_axi_rresp[M_COUNT]; +wire m_axi_rlast[M_COUNT]; +wire [RUSER_W-1:0] m_axi_ruser[M_COUNT]; +wire [M_COUNT-1:0] m_axi_rvalid; + +for (genvar n = 0; n < S_COUNT; n = n + 1) begin + assign s_axi_arid[n] = s_axi_rd[n].arid; + assign s_axi_araddr[n] = s_axi_rd[n].araddr; + assign s_axi_arlen[n] = s_axi_rd[n].arlen; + assign s_axi_arsize[n] = s_axi_rd[n].arsize; + assign s_axi_arburst[n] = s_axi_rd[n].arburst; + assign s_axi_arlock[n] = s_axi_rd[n].arlock; + assign s_axi_arcache[n] = s_axi_rd[n].arcache; + assign s_axi_prot[n] = s_axi_rd[n].arprot; + assign s_axi_arqos[n] = s_axi_rd[n].arqos; + assign s_axi_aruser[n] = s_axi_rd[n].aruser; + assign s_axi_arvalid[n] = s_axi_rd[n].arvalid; + assign s_axi_rd[n].arready = s_axi_arready_reg[n]; +end + +for (genvar n = 0; n < M_COUNT; n = n + 1) begin + assign m_axi_rd[n].arid = axi_id_reg; + assign m_axi_rd[n].araddr = axi_addr_reg; + assign m_axi_rd[n].arlen = axi_len_reg; + assign m_axi_rd[n].arsize = axi_size_reg; + assign m_axi_rd[n].arburst = axi_burst_reg; + assign m_axi_rd[n].arlock = axi_lock_reg; + assign m_axi_rd[n].arcache = axi_cache_reg; + assign m_axi_rd[n].arprot = axi_prot_reg; + assign m_axi_rd[n].arqos = axi_qos_reg; + assign m_axi_rd[n].aruser = ARUSER_EN ? axi_aruser_reg : '0; + assign m_axi_rd[n].arvalid = m_axi_arvalid_reg[n]; + assign m_axi_arready[n] = m_axi_rd[n].arready; + assign m_axi_rid[n] = m_axi_rd[n].rid; + assign m_axi_rdata[n] = m_axi_rd[n].rdata; + assign m_axi_rresp[n] = m_axi_rd[n].rresp; + assign m_axi_rlast[n] = m_axi_rd[n].rlast; + assign m_axi_ruser[n] = m_axi_rd[n].ruser; + assign m_axi_rvalid[n] = m_axi_rd[n].rvalid; + assign m_axi_rd[n].rready = m_axi_rready_reg[n]; +end + +// slave side mux +wire [CL_S_COUNT_INT-1:0] s_select; + +wire [S_ID_W-1:0] current_s_axi_arid = s_axi_arid[s_select]; +wire [ADDR_W-1:0] current_s_axi_araddr = s_axi_araddr[s_select]; +wire [7:0] current_s_axi_arlen = s_axi_arlen[s_select]; +wire [2:0] current_s_axi_arsize = s_axi_arsize[s_select]; +wire [1:0] current_s_axi_arburst = s_axi_arburst[s_select]; +wire current_s_axi_arlock = s_axi_arlock[s_select]; +wire [3:0] current_s_axi_arcache = s_axi_arcache[s_select]; +wire [2:0] current_s_axi_prot = s_axi_prot[s_select]; +wire [3:0] current_s_axi_arqos = s_axi_arqos[s_select]; +wire [ARUSER_W-1:0] current_s_axi_aruser = s_axi_aruser[s_select]; +wire current_s_axi_arvalid = s_axi_arvalid[s_select]; +wire current_s_axi_rready = s_axi_rready[s_select]; + +// master side mux +wire current_m_axi_arready = m_axi_arready[m_select_reg]; +wire [M_ID_W-1:0] current_m_axi_rid = m_axi_rid[m_select_reg]; +wire [DATA_W-1:0] current_m_axi_rdata = m_axi_rdata[m_select_reg]; +wire [1:0] current_m_axi_rresp = m_axi_rresp[m_select_reg]; +wire current_m_axi_rlast = m_axi_rlast[m_select_reg]; +wire [RUSER_W-1:0] current_m_axi_ruser = m_axi_ruser[m_select_reg]; +wire current_m_axi_rvalid = m_axi_rvalid[m_select_reg]; + +// arbiter instance +wire [S_COUNT-1:0] req; +wire [S_COUNT-1:0] ack; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT_INT-1:0] grant_index; + +assign s_select = grant_index; + +if (S_COUNT > 1) begin : arb + + taxi_arbiter #( + .PORTS(S_COUNT), + .ARB_ROUND_ROBIN(1), + .ARB_BLOCK(1), + .ARB_BLOCK_ACK(1), + .LSB_HIGH_PRIO(1) + ) + arb_inst ( + .clk(clk), + .rst(rst), + .req(req), + .ack(ack), + .grant(grant), + .grant_valid(grant_valid), + .grant_index(grant_index) + ); + +end else begin + + logic grant_valid_reg = 1'b0; + + always @(posedge clk) begin + if (req) begin + grant_valid_reg <= 1'b1; + end + + if (ack || rst) begin + grant_valid_reg <= 1'b0; + end + end + + assign grant_valid = grant_valid_reg; + assign grant = '1; + assign grant_index = '0; + +end + +// req generation +assign req = s_axi_arvalid; +assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0; + +always_comb begin + state_next = STATE_IDLE; + + match = 1'b0; + + m_select_next = m_select_reg; + axi_id_next = axi_id_reg; + axi_addr_next = axi_addr_reg; + axi_addr_valid_next = axi_addr_valid_reg; + axi_len_next = axi_len_reg; + axi_size_next = axi_size_reg; + axi_burst_next = axi_burst_reg; + axi_lock_next = axi_lock_reg; + axi_cache_next = axi_cache_reg; + axi_prot_next = axi_prot_reg; + axi_qos_next = axi_qos_reg; + axi_region_next = axi_region_reg; + axi_aruser_next = axi_aruser_reg; + + s_axi_arready_next = '0; + + m_axi_arvalid_next = m_axi_arvalid_reg & ~m_axi_arready; + m_axi_rready_next = '0; + + s_axi_rid_int = axi_id_reg; + s_axi_rdata_int = current_m_axi_rdata; + s_axi_rresp_int = current_m_axi_rresp; + s_axi_rlast_int = current_m_axi_rlast; + s_axi_ruser_int = current_m_axi_ruser; + s_axi_rvalid_int = '0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for arbitration + + axi_addr_valid_next = 1'b1; + axi_id_next = current_s_axi_arid; + axi_addr_next = current_s_axi_araddr; + axi_len_next = current_s_axi_arlen; + axi_size_next = current_s_axi_arsize; + axi_burst_next = current_s_axi_arburst; + axi_lock_next = current_s_axi_arlock; + axi_cache_next = current_s_axi_arcache; + axi_prot_next = current_s_axi_prot; + axi_qos_next = current_s_axi_arqos; + axi_aruser_next = current_s_axi_aruser; + + if (grant_valid) begin + s_axi_arready_next[s_select] = 1'b1; + state_next = STATE_DECODE; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DECODE: begin + // decode state; determine master interface + + match = 1'b0; + for (integer i = 0; i < M_COUNT; i = i + 1) begin + for (integer j = 0; j < M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin + m_select_next = CL_M_COUNT_INT'(i); + match = 1'b1; + end + end + end + + if (match) begin + m_axi_rready_next[m_select_reg] = s_axi_rready_int_early; + state_next = STATE_READ; + end else begin + // no match; return decode error + state_next = STATE_READ_DROP; + end + end + STATE_READ: begin + // read state; store and forward read response + m_axi_rready_next[m_select_reg] = s_axi_rready_int_early; + + if (axi_addr_valid_reg) begin + m_axi_arvalid_next[m_select_reg] = 1'b1; + end + axi_addr_valid_next = 1'b0; + + s_axi_rid_int = axi_id_reg; + s_axi_rdata_int = current_m_axi_rdata; + s_axi_rresp_int = current_m_axi_rresp; + s_axi_rlast_int = current_m_axi_rlast; + s_axi_ruser_int = current_m_axi_ruser; + + if (m_axi_rready_reg != 0 && current_m_axi_rvalid) begin + s_axi_rvalid_int[s_select] = 1'b1; + + if (current_m_axi_rlast) begin + m_axi_rready_next[m_select_reg] = 1'b0; + state_next = STATE_WAIT_IDLE; + end else begin + state_next = STATE_READ; + end + end else begin + state_next = STATE_READ; + end + end + STATE_READ_DROP: begin + // read drop state; generate decode error read response + + s_axi_rid_int = axi_id_reg; + s_axi_rdata_int = '0; + s_axi_rresp_int = 2'b11; + s_axi_rlast_int = axi_len_reg == 0; + s_axi_ruser_int = '0; + s_axi_rvalid_int[s_select] = 1'b1; + + if (s_axi_rready_int_reg) begin + axi_len_next = axi_len_reg - 1; + if (axi_len_reg == 0) begin + state_next = STATE_WAIT_IDLE; + end else begin + state_next = STATE_READ_DROP; + end + end else begin + state_next = STATE_READ_DROP; + end + end + STATE_WAIT_IDLE: begin + // wait for idle state; wait untl grant valid is deasserted + + if (grant_valid == 0 || ack != 0) begin + state_next = STATE_IDLE; + end else begin + state_next = STATE_WAIT_IDLE; + end + end + default: begin + // invalid state + state_next = STATE_IDLE; + end + endcase +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + s_axi_arready_reg <= s_axi_arready_next; + + m_axi_arvalid_reg <= m_axi_arvalid_next; + m_axi_rready_reg <= m_axi_rready_next; + + m_select_reg <= m_select_next; + axi_id_reg <= axi_id_next; + axi_addr_reg <= axi_addr_next; + axi_addr_valid_reg <= axi_addr_valid_next; + axi_len_reg <= axi_len_next; + axi_size_reg <= axi_size_next; + axi_burst_reg <= axi_burst_next; + axi_lock_reg <= axi_lock_next; + axi_cache_reg <= axi_cache_next; + axi_prot_reg <= axi_prot_next; + axi_qos_reg <= axi_qos_next; + axi_region_reg <= axi_region_next; + axi_aruser_reg <= axi_aruser_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_arready_reg <= '0; + + m_axi_arvalid_reg <= '0; + m_axi_rready_reg <= '0; + end +end + +// output datapath logic (R channel) +logic [S_ID_W-1:0] s_axi_rid_reg = '0; +logic [DATA_W-1:0] s_axi_rdata_reg = '0; +logic [1:0] s_axi_rresp_reg = 2'd0; +logic s_axi_rlast_reg = 1'b0; +logic [RUSER_W-1:0] s_axi_ruser_reg = 1'b0; +logic [S_COUNT-1:0] s_axi_rvalid_reg = '0, s_axi_rvalid_next; + +logic [S_ID_W-1:0] temp_s_axi_rid_reg = '0; +logic [DATA_W-1:0] temp_s_axi_rdata_reg = '0; +logic [1:0] temp_s_axi_rresp_reg = 2'd0; +logic temp_s_axi_rlast_reg = 1'b0; +logic [RUSER_W-1:0] temp_s_axi_ruser_reg = 1'b0; +logic [S_COUNT-1:0] temp_s_axi_rvalid_reg = '0, temp_s_axi_rvalid_next; + +// datapath control +logic store_axi_r_int_to_output; +logic store_axi_r_int_to_temp; +logic store_axi_r_temp_to_output; + +wire [S_COUNT-1:0] s_axi_rready; + +for (genvar n = 0; n < S_COUNT; n = n + 1) begin + assign s_axi_rd[n].rid = s_axi_rid_reg; + assign s_axi_rd[n].rdata = s_axi_rdata_reg; + assign s_axi_rd[n].rresp = s_axi_rresp_reg; + assign s_axi_rd[n].rlast = s_axi_rlast_reg; + assign s_axi_rd[n].ruser = RUSER_EN ? s_axi_ruser_reg : '0; + assign s_axi_rd[n].rvalid = s_axi_rvalid_reg[n]; + assign s_axi_rready[n] = s_axi_rd[n].rready; +end + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign s_axi_rready_int_early = (s_axi_rready & s_axi_rvalid_reg) != 0 || (temp_s_axi_rvalid_reg == 0 && (s_axi_rvalid_reg == 0 || s_axi_rvalid_int == 0)); + +always_comb begin + // transfer sink ready state to source + s_axi_rvalid_next = s_axi_rvalid_reg; + temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg; + + store_axi_r_int_to_output = 1'b0; + store_axi_r_int_to_temp = 1'b0; + store_axi_r_temp_to_output = 1'b0; + + if (s_axi_rready_int_reg) begin + // input is ready + if ((s_axi_rready & s_axi_rvalid_reg) != 0 || s_axi_rvalid_reg == 0) begin + // output is ready or currently not valid, transfer data to output + s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_temp = 1'b1; + end + end else if ((s_axi_rready & s_axi_rvalid_reg) != 0) begin + // input is not ready, but output is ready + s_axi_rvalid_next = temp_s_axi_rvalid_reg; + temp_s_axi_rvalid_next = '0; + store_axi_r_temp_to_output = 1'b1; + end +end + +always_ff @(posedge clk) begin + s_axi_rvalid_reg <= s_axi_rvalid_next; + s_axi_rready_int_reg <= s_axi_rready_int_early; + temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next; + + // datapath + if (store_axi_r_int_to_output) begin + s_axi_rid_reg <= s_axi_rid_int; + s_axi_rdata_reg <= s_axi_rdata_int; + s_axi_rresp_reg <= s_axi_rresp_int; + s_axi_rlast_reg <= s_axi_rlast_int; + s_axi_ruser_reg <= s_axi_ruser_int; + end else if (store_axi_r_temp_to_output) begin + s_axi_rid_reg <= temp_s_axi_rid_reg; + s_axi_rdata_reg <= temp_s_axi_rdata_reg; + s_axi_rresp_reg <= temp_s_axi_rresp_reg; + s_axi_rlast_reg <= temp_s_axi_rlast_reg; + s_axi_ruser_reg <= temp_s_axi_ruser_reg; + end + + if (store_axi_r_int_to_temp) begin + temp_s_axi_rid_reg <= s_axi_rid_int; + temp_s_axi_rdata_reg <= s_axi_rdata_int; + temp_s_axi_rresp_reg <= s_axi_rresp_int; + temp_s_axi_rlast_reg <= s_axi_rlast_int; + temp_s_axi_ruser_reg <= s_axi_ruser_int; + end + + if (rst) begin + s_axi_rvalid_reg <= '0; + s_axi_rready_int_reg <= 1'b0; + temp_s_axi_rvalid_reg <= '0; + end +end + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_interconnect_wr.sv b/src/axi/rtl/taxi_axi_interconnect_wr.sv new file mode 100644 index 0000000..dd8a95e --- /dev/null +++ b/src/axi/rtl/taxi_axi_interconnect_wr.sv @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 interconnect + */ +module taxi_axi_interconnect_wr # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // Number of regions per master interface + parameter M_REGIONS = 1, + // TODO fix parametrization once verilator issue 5890 is fixed + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = 0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Write connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interfaces + */ + taxi_axi_if.wr_slv s_axi_wr[S_COUNT], + + /* + * AXI4 master interfaces + */ + taxi_axi_if.wr_mst m_axi_wr[M_COUNT] +); + +// extract parameters +localparam DATA_W = s_axi_wr.DATA_W; +localparam S_ADDR_W = s_axi_wr.ADDR_W; +localparam STRB_W = s_axi_wr.STRB_W; +localparam S_ID_W = s_axi_wr.ID_W; +localparam M_ID_W = m_axi_wr.ID_W; +localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN; +localparam AWUSER_W = s_axi_wr.AWUSER_W; +localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN; +localparam WUSER_W = s_axi_wr.WUSER_W; +localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN; +localparam BUSER_W = s_axi_wr.BUSER_W; + +localparam CL_S_COUNT = $clog2(S_COUNT); +localparam CL_M_COUNT = $clog2(M_COUNT); +localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1; +localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1; + +localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W; +localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT; +localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE; + +// default address computation +function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy); + logic [ADDR_W-1:0] base; + logic [ADDR_W-1:0] width; + logic [ADDR_W-1:0] size; + logic [ADDR_W-1:0] mask; + begin + calcBaseAddrs = '0; + base = 0; + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + width = M_ADDR_W_INT[i]; + mask = {ADDR_W{1'b1}} >> (ADDR_W - width); + size = mask + 1; + if (width > 0) begin + if ((base & mask) != 0) begin + base = base + size - (base & mask); // align + end + calcBaseAddrs[i] = base; + base = base + size; // increment + end + end + end +endfunction + +localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0); + +// check configuration +if (s_axi_wr.ADDR_W != ADDR_W) + $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)"); + +if (m_axi_wr.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axi_wr.STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +initial begin + if (M_REGIONS < 1 || M_REGIONS > 16) begin + $error("Error: M_REGIONS must be between 1 and 16 (instance %m)"); + $finish; + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + /* verilator lint_off UNSIGNED */ + if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin + $error("Error: address width out of range (instance %m)"); + $finish; + end + /* verilator lint_on UNSIGNED */ + end + + $display("Addressing configuration for axi_interconnect instance %m"); + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if (M_ADDR_W_INT[i] != 0) begin + $display("%2d (%2d): %x / %02d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin + $display("Region not aligned:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $error("Error: address range not aligned (instance %m)"); + $finish; + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin + if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])))) + && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin + $display("Overlapping regions:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $display("%2d (%2d): %x / %2d -- %x-%x", + j/M_REGIONS, j%M_REGIONS, + M_BASE_ADDR_INT[j], + M_ADDR_W_INT[j], + M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]), + M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])) + ); + $error("Error: address ranges overlap (instance %m)"); + $finish; + end + end + end + end +end + +localparam logic [2:0] + STATE_IDLE = 3'd0, + STATE_DECODE = 3'd1, + STATE_WRITE = 3'd2, + STATE_WRITE_RESP = 3'd3, + STATE_WRITE_DROP = 3'd4, + STATE_WAIT_IDLE = 3'd5; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +logic match; + +logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next; +logic [S_ID_W-1:0] axi_id_reg = '0, axi_id_next; +logic [ADDR_W-1:0] axi_addr_reg = '0, axi_addr_next; +logic axi_addr_valid_reg = 1'b0, axi_addr_valid_next; +logic [7:0] axi_len_reg = 8'd0, axi_len_next; +logic [2:0] axi_size_reg = 3'd0, axi_size_next; +logic [1:0] axi_burst_reg = 2'd0, axi_burst_next; +logic axi_lock_reg = 1'b0, axi_lock_next; +logic [3:0] axi_cache_reg = 4'd0, axi_cache_next; +logic [2:0] axi_prot_reg = 3'b000, axi_prot_next; +logic [3:0] axi_qos_reg = 4'd0, axi_qos_next; +logic [3:0] axi_region_reg = 4'd0, axi_region_next; +logic [AWUSER_W-1:0] axi_awuser_reg = '0, axi_awuser_next; +logic [1:0] axi_bresp_reg = 2'b00, axi_bresp_next; +logic [BUSER_W-1:0] axi_buser_reg = '0, axi_buser_next; + +logic [S_COUNT-1:0] s_axi_awready_reg = '0, s_axi_awready_next; +logic [S_COUNT-1:0] s_axi_wready_reg = '0, s_axi_wready_next; +logic [S_COUNT-1:0] s_axi_bvalid_reg = '0, s_axi_bvalid_next; + +logic [M_COUNT-1:0] m_axi_awvalid_reg = '0, m_axi_awvalid_next; +logic [M_COUNT-1:0] m_axi_bready_reg = '0, m_axi_bready_next; + +// internal datapath +logic [DATA_W-1:0] m_axi_wdata_int; +logic [STRB_W-1:0] m_axi_wstrb_int; +logic m_axi_wlast_int; +logic [WUSER_W-1:0] m_axi_wuser_int; +logic [M_COUNT-1:0] m_axi_wvalid_int; +logic m_axi_wready_int_reg = 1'b0; +wire m_axi_wready_int_early; + +// unpack interface array +wire [S_ID_W-1:0] s_axi_awid[S_COUNT]; +wire [ADDR_W-1:0] s_axi_addr[S_COUNT]; +wire [7:0] s_axi_awlen[S_COUNT]; +wire [2:0] s_axi_awsize[S_COUNT]; +wire [1:0] s_axi_awburst[S_COUNT]; +wire s_axi_awlock[S_COUNT]; +wire [3:0] s_axi_awcache[S_COUNT]; +wire [2:0] s_axi_awprot[S_COUNT]; +wire [3:0] s_axi_awqos[S_COUNT]; +wire [AWUSER_W-1:0] s_axi_awuser[S_COUNT]; +wire [S_COUNT-1:0] s_axi_awvalid; +wire [DATA_W-1:0] s_axi_wdata[S_COUNT]; +wire [STRB_W-1:0] s_axi_wstrb[S_COUNT]; +wire s_axi_wlast[S_COUNT]; +wire [WUSER_W-1:0] s_axi_wuser[S_COUNT]; +wire [S_COUNT-1:0] s_axi_wvalid; +wire [S_COUNT-1:0] s_axi_bready; + +wire [M_COUNT-1:0] m_axi_awready; +wire [M_ID_W-1:0] m_axi_bid[M_COUNT]; +wire [1:0] m_axi_bresp[M_COUNT]; +wire [BUSER_W-1:0] m_axi_buser[M_COUNT]; +wire [M_COUNT-1:0] m_axi_bvalid; + +for (genvar n = 0; n < S_COUNT; n = n + 1) begin + assign s_axi_awid[n] = s_axi_wr[n].awid; + assign s_axi_addr[n] = s_axi_wr[n].awaddr; + assign s_axi_awlen[n] = s_axi_wr[n].awlen; + assign s_axi_awsize[n] = s_axi_wr[n].awsize; + assign s_axi_awburst[n] = s_axi_wr[n].awburst; + assign s_axi_awlock[n] = s_axi_wr[n].awlock; + assign s_axi_awcache[n] = s_axi_wr[n].awcache; + assign s_axi_awprot[n] = s_axi_wr[n].awprot; + assign s_axi_awqos[n] = s_axi_wr[n].awqos; + assign s_axi_awuser[n] = s_axi_wr[n].awuser; + assign s_axi_awvalid[n] = s_axi_wr[n].awvalid; + assign s_axi_wr[n].awready = s_axi_awready_reg[n]; + assign s_axi_wdata[n] = s_axi_wr[n].wdata; + assign s_axi_wstrb[n] = s_axi_wr[n].wstrb; + assign s_axi_wlast[n] = s_axi_wr[n].wlast; + assign s_axi_wuser[n] = s_axi_wr[n].wuser; + assign s_axi_wvalid[n] = s_axi_wr[n].wvalid; + assign s_axi_wr[n].wready = s_axi_wready_reg[n]; + assign s_axi_wr[n].bid = axi_id_reg; + assign s_axi_wr[n].bresp = axi_bresp_reg; + assign s_axi_wr[n].buser = BUSER_EN ? axi_buser_reg : '0; + assign s_axi_wr[n].bvalid = s_axi_bvalid_reg[n]; + assign s_axi_bready[n] = s_axi_wr[n].bready; +end + +for (genvar n = 0; n < M_COUNT; n = n + 1) begin + assign m_axi_wr[n].awid = axi_id_reg; + assign m_axi_wr[n].awaddr = axi_addr_reg; + assign m_axi_wr[n].awlen = axi_len_reg; + assign m_axi_wr[n].awsize = axi_size_reg; + assign m_axi_wr[n].awburst = axi_burst_reg; + assign m_axi_wr[n].awlock = axi_lock_reg; + assign m_axi_wr[n].awcache = axi_cache_reg; + assign m_axi_wr[n].awprot = axi_prot_reg; + assign m_axi_wr[n].awqos = axi_qos_reg; + assign m_axi_wr[n].awuser = AWUSER_EN ? axi_awuser_reg : '0; + assign m_axi_wr[n].awvalid = m_axi_awvalid_reg[n]; + assign m_axi_awready[n] = m_axi_wr[n].awready; + assign m_axi_bid[n] = m_axi_wr[n].bid; + assign m_axi_bresp[n] = m_axi_wr[n].bresp; + assign m_axi_buser[n] = m_axi_wr[n].buser; + assign m_axi_bvalid[n] = m_axi_wr[n].bvalid; + assign m_axi_wr[n].bready = m_axi_bready_reg[n]; +end + +// slave side mux +wire [CL_S_COUNT_INT-1:0] s_select; + +wire [S_ID_W-1:0] current_s_axi_awid = s_axi_awid[s_select]; +wire [ADDR_W-1:0] current_s_axi_addr = s_axi_addr[s_select]; +wire [7:0] current_s_axi_awlen = s_axi_awlen[s_select]; +wire [2:0] current_s_axi_awsize = s_axi_awsize[s_select]; +wire [1:0] current_s_axi_awburst = s_axi_awburst[s_select]; +wire current_s_axi_awlock = s_axi_awlock[s_select]; +wire [3:0] current_s_axi_awcache = s_axi_awcache[s_select]; +wire [2:0] current_s_axi_awprot = s_axi_awprot[s_select]; +wire [3:0] current_s_axi_awqos = s_axi_awqos[s_select]; +wire [AWUSER_W-1:0] current_s_axi_awuser = s_axi_awuser[s_select]; +wire current_s_axi_awvalid = s_axi_awvalid[s_select]; +wire [DATA_W-1:0] current_s_axi_wdata = s_axi_wdata[s_select]; +wire [STRB_W-1:0] current_s_axi_wstrb = s_axi_wstrb[s_select]; +wire current_s_axi_wlast = s_axi_wlast[s_select]; +wire [WUSER_W-1:0] current_s_axi_wuser = s_axi_wuser[s_select]; +wire current_s_axi_wvalid = s_axi_wvalid[s_select]; +wire current_s_axi_bready = s_axi_bready[s_select]; + +// master side mux +wire current_m_axi_awready = m_axi_awready[m_select_reg]; +wire current_m_axi_wready = m_axi_wready[m_select_reg]; +wire [M_ID_W-1:0] current_m_axi_bid = m_axi_bid[m_select_reg]; +wire [1:0] current_m_axi_bresp = m_axi_bresp[m_select_reg]; +wire [BUSER_W-1:0] current_m_axi_buser = m_axi_buser[m_select_reg]; +wire current_m_axi_bvalid = m_axi_bvalid[m_select_reg]; + +// arbiter instance +wire [S_COUNT-1:0] req; +wire [S_COUNT-1:0] ack; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT_INT-1:0] grant_index; + +assign s_select = grant_index; + +if (S_COUNT > 1) begin : arb + + taxi_arbiter #( + .PORTS(S_COUNT), + .ARB_ROUND_ROBIN(1), + .ARB_BLOCK(1), + .ARB_BLOCK_ACK(1), + .LSB_HIGH_PRIO(1) + ) + arb_inst ( + .clk(clk), + .rst(rst), + .req(req), + .ack(ack), + .grant(grant), + .grant_valid(grant_valid), + .grant_index(grant_index) + ); + +end else begin + + logic grant_valid_reg = 1'b0; + + always @(posedge clk) begin + if (req) begin + grant_valid_reg <= 1'b1; + end + + if (ack || rst) begin + grant_valid_reg <= 1'b0; + end + end + + assign grant_valid = grant_valid_reg; + assign grant = '1; + assign grant_index = '0; + +end + +assign req = s_axi_awvalid; +assign ack = state_reg == STATE_WAIT_IDLE ? '1 : '0; + +always_comb begin + state_next = STATE_IDLE; + + match = 1'b0; + + m_select_next = m_select_reg; + axi_id_next = axi_id_reg; + axi_addr_next = axi_addr_reg; + axi_addr_valid_next = axi_addr_valid_reg; + axi_len_next = axi_len_reg; + axi_size_next = axi_size_reg; + axi_burst_next = axi_burst_reg; + axi_lock_next = axi_lock_reg; + axi_cache_next = axi_cache_reg; + axi_prot_next = axi_prot_reg; + axi_qos_next = axi_qos_reg; + axi_region_next = axi_region_reg; + axi_awuser_next = axi_awuser_reg; + axi_bresp_next = axi_bresp_reg; + axi_buser_next = axi_buser_reg; + + s_axi_awready_next = '0; + s_axi_wready_next = '0; + s_axi_bvalid_next = s_axi_bvalid_reg & ~s_axi_bready; + + m_axi_awvalid_next = m_axi_awvalid_reg & ~m_axi_awready; + m_axi_bready_next = '0; + + m_axi_wdata_int = current_s_axi_wdata; + m_axi_wstrb_int = current_s_axi_wstrb; + m_axi_wlast_int = current_s_axi_wlast; + m_axi_wuser_int = current_s_axi_wuser; + m_axi_wvalid_int = '0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for arbitration + + axi_addr_valid_next = 1'b1; + axi_id_next = current_s_axi_awid; + axi_addr_next = current_s_axi_addr; + axi_len_next = current_s_axi_awlen; + axi_size_next = current_s_axi_awsize; + axi_burst_next = current_s_axi_awburst; + axi_lock_next = current_s_axi_awlock; + axi_cache_next = current_s_axi_awcache; + axi_prot_next = current_s_axi_awprot; + axi_qos_next = current_s_axi_awqos; + axi_awuser_next = current_s_axi_awuser; + + if (grant_valid) begin + s_axi_awready_next[s_select] = 1'b1; + state_next = STATE_DECODE; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DECODE: begin + // decode state; determine master interface + + match = 1'b0; + for (integer i = 0; i < M_COUNT; i = i + 1) begin + for (integer j = 0; j < M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axi_prot_reg[1]) && M_CONNECT_INT[i][s_select] && (axi_addr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin + m_select_next = CL_M_COUNT_INT'(i); + match = 1'b1; + end + end + end + + axi_bresp_next = 2'b11; + + if (match) begin + s_axi_wready_next[s_select] = m_axi_wready_int_early; + state_next = STATE_WRITE; + end else begin + // no match; return decode error + s_axi_wready_next[s_select] = 1'b1; + state_next = STATE_WRITE_DROP; + end + end + STATE_WRITE: begin + // write state; store and forward write data + s_axi_wready_next[s_select] = m_axi_wready_int_early; + + if (axi_addr_valid_reg) begin + m_axi_awvalid_next[m_select_reg] = 1'b1; + end + axi_addr_valid_next = 1'b0; + + m_axi_wdata_int = current_s_axi_wdata; + m_axi_wstrb_int = current_s_axi_wstrb; + m_axi_wlast_int = current_s_axi_wlast; + m_axi_wuser_int = current_s_axi_wuser; + + if (s_axi_wready_reg != 0 && current_s_axi_wvalid) begin + m_axi_wvalid_int[m_select_reg] = 1'b1; + + if (current_s_axi_wlast) begin + s_axi_wready_next[s_select] = 1'b0; + m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0; + state_next = STATE_WRITE_RESP; + end else begin + state_next = STATE_WRITE; + end + end else begin + state_next = STATE_WRITE; + end + end + STATE_WRITE_RESP: begin + // write response state; store and forward write response + m_axi_bready_next[m_select_reg] = s_axi_bvalid_reg == 0; + + if (m_axi_bready_reg != 0 && current_m_axi_bvalid) begin + m_axi_bready_next[m_select_reg] = 1'b0; + axi_bresp_next = current_m_axi_bresp; + s_axi_bvalid_next[s_select] = 1'b1; + state_next = STATE_WAIT_IDLE; + end else begin + state_next = STATE_WRITE_RESP; + end + end + STATE_WRITE_DROP: begin + // write drop state; drop write data + s_axi_wready_next[s_select] = 1'b1; + + axi_addr_valid_next = 1'b0; + + if (s_axi_wready_reg != 0 && current_s_axi_wvalid && current_s_axi_wlast) begin + s_axi_wready_next[s_select] = 1'b0; + s_axi_bvalid_next[s_select] = 1'b1; + state_next = STATE_WAIT_IDLE; + end else begin + state_next = STATE_WRITE_DROP; + end + end + STATE_WAIT_IDLE: begin + // wait for idle state; wait untl grant valid is deasserted + + if (grant_valid == 0 || ack != 0) begin + state_next = STATE_IDLE; + end else begin + state_next = STATE_WAIT_IDLE; + end + end + default: begin + // invalid state + state_next = STATE_IDLE; + end + endcase +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + s_axi_awready_reg <= s_axi_awready_next; + s_axi_wready_reg <= s_axi_wready_next; + s_axi_bvalid_reg <= s_axi_bvalid_next; + + m_axi_awvalid_reg <= m_axi_awvalid_next; + m_axi_bready_reg <= m_axi_bready_next; + + m_select_reg <= m_select_next; + axi_id_reg <= axi_id_next; + axi_addr_reg <= axi_addr_next; + axi_addr_valid_reg <= axi_addr_valid_next; + axi_len_reg <= axi_len_next; + axi_size_reg <= axi_size_next; + axi_burst_reg <= axi_burst_next; + axi_lock_reg <= axi_lock_next; + axi_cache_reg <= axi_cache_next; + axi_prot_reg <= axi_prot_next; + axi_qos_reg <= axi_qos_next; + axi_region_reg <= axi_region_next; + axi_awuser_reg <= axi_awuser_next; + axi_bresp_reg <= axi_bresp_next; + axi_buser_reg <= axi_buser_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_awready_reg <= '0; + s_axi_wready_reg <= '0; + s_axi_bvalid_reg <= '0; + + m_axi_awvalid_reg <= '0; + m_axi_bready_reg <= '0; + end +end + +// output datapath logic (W channel) +logic [DATA_W-1:0] m_axi_wdata_reg = '0; +logic [STRB_W-1:0] m_axi_wstrb_reg = '0; +logic m_axi_wlast_reg = 1'b0; +logic [WUSER_W-1:0] m_axi_wuser_reg = 1'b0; +logic [M_COUNT-1:0] m_axi_wvalid_reg = '0, m_axi_wvalid_next; + +logic [DATA_W-1:0] temp_m_axi_wdata_reg = '0; +logic [STRB_W-1:0] temp_m_axi_wstrb_reg = '0; +logic temp_m_axi_wlast_reg = 1'b0; +logic [WUSER_W-1:0] temp_m_axi_wuser_reg = 1'b0; +logic [M_COUNT-1:0] temp_m_axi_wvalid_reg = '0, temp_m_axi_wvalid_next; + +// datapath control +logic store_axi_w_int_to_output; +logic store_axi_w_int_to_temp; +logic store_axi_w_temp_to_output; + +wire [M_COUNT-1:0] m_axi_wready; + +for (genvar n = 0; n < M_COUNT; n = n + 1) begin + assign m_axi_wr[n].wdata = m_axi_wdata_reg; + assign m_axi_wr[n].wstrb = m_axi_wstrb_reg; + assign m_axi_wr[n].wlast = m_axi_wlast_reg; + assign m_axi_wr[n].wuser = WUSER_EN ? m_axi_wuser_reg : '0; + assign m_axi_wr[n].wvalid = m_axi_wvalid_reg[n]; + assign m_axi_wready[n] = m_axi_wr[n].wready; +end + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axi_wready_int_early = (m_axi_wready & m_axi_wvalid_reg) != 0 || (temp_m_axi_wvalid_reg == 0 && (m_axi_wvalid_reg == 0 || m_axi_wvalid_int == 0)); + +always_comb begin + // transfer sink ready state to source + m_axi_wvalid_next = m_axi_wvalid_reg; + temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg; + + store_axi_w_int_to_output = 1'b0; + store_axi_w_int_to_temp = 1'b0; + store_axi_w_temp_to_output = 1'b0; + + if (m_axi_wready_int_reg) begin + // input is ready + if ((m_axi_wready & m_axi_wvalid_reg) != 0 || m_axi_wvalid_reg == 0) begin + // output is ready or currently not valid, transfer data to output + m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_temp = 1'b1; + end + end else if ((m_axi_wready & m_axi_wvalid_reg) != 0) begin + // input is not ready, but output is ready + m_axi_wvalid_next = temp_m_axi_wvalid_reg; + temp_m_axi_wvalid_next = '0; + store_axi_w_temp_to_output = 1'b1; + end +end + +always_ff @(posedge clk) begin + m_axi_wvalid_reg <= m_axi_wvalid_next; + m_axi_wready_int_reg <= m_axi_wready_int_early; + temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next; + + // datapath + if (store_axi_w_int_to_output) begin + m_axi_wdata_reg <= m_axi_wdata_int; + m_axi_wstrb_reg <= m_axi_wstrb_int; + m_axi_wlast_reg <= m_axi_wlast_int; + m_axi_wuser_reg <= m_axi_wuser_int; + end else if (store_axi_w_temp_to_output) begin + m_axi_wdata_reg <= temp_m_axi_wdata_reg; + m_axi_wstrb_reg <= temp_m_axi_wstrb_reg; + m_axi_wlast_reg <= temp_m_axi_wlast_reg; + m_axi_wuser_reg <= temp_m_axi_wuser_reg; + end + + if (store_axi_w_int_to_temp) begin + temp_m_axi_wdata_reg <= m_axi_wdata_int; + temp_m_axi_wstrb_reg <= m_axi_wstrb_int; + temp_m_axi_wlast_reg <= m_axi_wlast_int; + temp_m_axi_wuser_reg <= m_axi_wuser_int; + end + + if (rst) begin + m_axi_wvalid_reg <= '0; + m_axi_wready_int_reg <= 1'b0; + temp_m_axi_wvalid_reg <= '0; + end +end + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axi_interconnect/Makefile b/src/axi/tb/taxi_axi_interconnect/Makefile new file mode 100644 index 0000000..af92d43 --- /dev/null +++ b/src/axi/tb/taxi_axi_interconnect/Makefile @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axi_interconnect +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +REG_TYPE ?= 1 + +# module parameters +export PARAM_DATA_W := 32 +export PARAM_ADDR_W := 32 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_S_ID_W := 8 +export PARAM_M_ID_W := $(shell expr $(PARAM_S_ID_W) + 2 ) +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 +export PARAM_M_REGIONS := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.py b/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.py new file mode 100644 index 0000000..a952c22 --- /dev/null +++ b/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.py @@ -0,0 +1,275 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiBus, AxiMaster, AxiRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axi_master = [AxiMaster(AxiBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axi] + self.axi_ram = [AxiRam(AxiBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axi] + + def set_idle_generator(self, generator=None): + if generator: + for master in self.axi_master: + master.write_if.aw_channel.set_pause_generator(generator()) + master.write_if.w_channel.set_pause_generator(generator()) + master.read_if.ar_channel.set_pause_generator(generator()) + for ram in self.axi_ram: + ram.write_if.b_channel.set_pause_generator(generator()) + ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + for master in self.axi_master: + master.write_if.b_channel.set_pause_generator(generator()) + master.read_if.r_channel.set_pause_generator(generator()) + for ram in self.axi_ram: + ram.write_if.aw_channel.set_pause_generator(generator()) + ram.write_if.w_channel.set_pause_generator(generator()) + ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0): + + tb = TB(dut) + + byte_lanes = tb.axi_master[s].write_if.byte_lanes + max_burst_size = tb.axi_master[s].write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)): + tb.log.info("length %d, offset %d, size %d", length, offset, size) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram[m].write(ram_addr-128, b'\xaa'*(length+256)) + + await tb.axi_master[s].write(addr, test_data, size=size) + + tb.log.debug("%s", tb.axi_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axi_ram[m].read(ram_addr, length) == test_data + assert tb.axi_ram[m].read(ram_addr-1, 1) == b'\xaa' + assert tb.axi_ram[m].read(ram_addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None, s=0, m=0): + + tb = TB(dut) + + byte_lanes = tb.axi_master[s].write_if.byte_lanes + max_burst_size = tb.axi_master[s].write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)): + tb.log.info("length %d, offset %d, size %d", length, offset, size) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram[m].write(ram_addr, test_data) + + data = await tb.axi_master[s].read(addr, length, size=size) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + m = random.randrange(len(tb.axi_ram)) + length = random.randint(1, min(512, aperture)) + addr = offset+random.randint(0, aperture-length) + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + s_count = len(cocotb.top.s_axi) + m_count = len(cocotb.top.m_axi) + + data_w = len(cocotb.top.s_axi[0].wdata) + byte_lanes = data_w // 8 + max_burst_size = (byte_lanes-1).bit_length() + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + # factory.add_option("size", [None]+list(range(max_burst_size))) + factory.add_option("s", range(min(s_count, 2))) + factory.add_option("m", range(min(m_count, 2))) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("data_w", [8, 16, 32]) +@pytest.mark.parametrize("m_count", [1, 4]) +@pytest.mark.parametrize("s_count", [1, 4]) +def test_taxi_axi_interconnect(request, s_count, m_count, data_w): + dut = "taxi_axi_interconnect" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['S_COUNT'] = s_count + parameters['M_COUNT'] = m_count + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 32 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['S_ID_W'] = 8 + parameters['M_ID_W'] = parameters['S_ID_W'] + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + parameters['M_REGIONS'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv b/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv new file mode 100644 index 0000000..7990092 --- /dev/null +++ b/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 interconnect testbench + */ +module test_taxi_axi_interconnect # +( + /* verilator lint_off WIDTHTRUNC */ + parameter S_COUNT = 4, + parameter M_COUNT = 4, + parameter DATA_W = 32, + parameter ADDR_W = 32, + parameter STRB_W = (DATA_W/8), + parameter S_ID_W = 8, + parameter M_ID_W = S_ID_W, + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1, + parameter M_REGIONS = 1, + parameter M_BASE_ADDR = '0, + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_SECURE = {M_COUNT{1'b0}} + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axi_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .ID_W(S_ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axi[S_COUNT](); + +taxi_axi_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .ID_W(M_ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) m_axi[M_COUNT](); + +taxi_axi_interconnect #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT_RD(M_CONNECT_RD), + .M_CONNECT_WR(M_CONNECT_WR), + .M_SECURE(M_SECURE) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_wr(s_axi), + .s_axi_rd(s_axi), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi), + .m_axi_rd(m_axi) +); + +endmodule + +`resetall