diff --git a/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile
index ed7a764..377cb3c 100644
--- a/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile
+++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K35/Makefile
@@ -24,7 +24,9 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
 
 # XDC files
-XDC_FILES = ../fpga_k35.xdc
+XDC_FILES += ../syn/K35/fpga.xdc
+XDC_FILES += ../syn/K35/gpio.xdc
+XDC_FILES += ../syn/K35/sfp.xdc
 XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
diff --git a/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile
index 5a9b746..93280e8 100644
--- a/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile
+++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile
@@ -24,7 +24,9 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
 
 # XDC files
-XDC_FILES = ../fpga_k3p.xdc
+XDC_FILES += ../syn/K3P/fpga.xdc
+XDC_FILES += ../syn/K3P/gpio.xdc
+XDC_FILES += ../syn/K3P/sfp.xdc
 XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
diff --git a/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile
index e539a05..0ed0684 100644
--- a/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile
+++ b/src/eth/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile
@@ -24,7 +24,9 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
 SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
 
 # XDC files
-XDC_FILES = ../fpga_k3p.xdc
+XDC_FILES += ../syn/K3P/fpga.xdc
+XDC_FILES += ../syn/K3P/gpio.xdc
+XDC_FILES += ../syn/K3P/sfp.xdc
 XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
diff --git a/src/eth/example/Nexus_K3P_S/fpga/fpga_k35.xdc b/src/eth/example/Nexus_K3P_S/fpga/fpga_k35.xdc
deleted file mode 100644
index 64915fc..0000000
--- a/src/eth/example/Nexus_K3P_S/fpga/fpga_k35.xdc
+++ /dev/null
@@ -1,192 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
-# part: xcku035-fbva676-2-e
-
-# General configuration
-set_property CFGBVS GND                                [current_design]
-set_property CONFIG_VOLTAGE 1.8                        [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
-set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2      [current_design]
-set_property CONFIG_MODE BPI16                         [current_design]
-set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
-
-# 100 MHz system clock
-set_property -dict {LOC D18  IOSTANDARD LVDS} [get_ports {clk_100mhz_p}]
-set_property -dict {LOC C18  IOSTANDARD LVDS} [get_ports {clk_100mhz_n}]
-create_clock -period 10 -name clk_100mhz [get_ports {clk_100mhz_p}]
-
-# LEDs
-set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
-set_property -dict {LOC A24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
-set_property -dict {LOC E23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
-set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
-set_property -dict {LOC C23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
-set_property -dict {LOC D23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
-
-set_false_path -to [get_ports {sfp_led[*][*] sma_led[*]}]
-set_output_delay 0 [get_ports {sfp_led[*][*] sma_led[*]}]
-
-# GPIO
-#set_property -dict {LOC W26  IOSTANDARD LVCMOS18} [get_ports {gpio[0]}]
-#set_property -dict {LOC Y26  IOSTANDARD LVCMOS18} [get_ports {gpio[1]}]
-#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}]
-#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}]
-
-# SMA
-#set_property -dict {LOC B17  IOSTANDARD LVCMOS18} [get_ports {sma_in}]
-#set_property -dict {LOC B16  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {sma_out}]
-#set_property -dict {LOC B19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_out_en}]
-#set_property -dict {LOC C16  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_term_en}]
-
-#set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}]
-#set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}]
-#set_false_path -from [get_ports {sma_in}]
-#set_input_delay 0 [get_ports {sma_in}]
-
-# SFP+ Interfaces
-set_property -dict {LOC D2  } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC D1  } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC E4  } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC E3  } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC C4  } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC C3  } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC D6  } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC D5  } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
-set_property -dict {LOC H6  } [get_ports {sfp_mgt_refclk_p}] ;# MGTREFCLK0P_227 from X2
-set_property -dict {LOC H5  } [get_ports {sfp_mgt_refclk_n}] ;# MGTREFCLK0N_227 from X2
-set_property -dict {LOC AA12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
-set_property -dict {LOC W14  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
-set_property -dict {LOC C24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[0]}]
-set_property -dict {LOC D24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[1]}]
-set_property -dict {LOC W13  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}]
-set_property -dict {LOC AB12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}]
-set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0]}]
-set_property -dict {LOC D25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1]}]
-#set_property -dict {LOC W11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl}]
-#set_property -dict {LOC Y11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}]
-#set_property -dict {LOC Y13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}]
-
-# 161.1328125 MHz MGT reference clock
-create_clock -period 6.206 -name sfp_mgt_refclk [get_ports {sfp_mgt_refclk_p}]
-
-set_false_path -to [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
-set_output_delay 0 [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
-set_false_path -from [get_ports {sfp_npres[*] sfp_los[*]}]
-set_input_delay 0 [get_ports {sfp_npres[*] sfp_los[*]}]
-
-#set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-
-# I2C interface
-#set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_scl}]
-#set_property -dict {LOC C26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_sda}]
-
-#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-
-# PCIe Interface
-#set_property -dict {LOC P2  } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC P1  } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC R4  } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC R3  } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC T2  } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC T1  } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC U4  } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC U3  } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC V2  } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC V1  } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC W4  } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC W3  } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC AA4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC AA3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
-#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AB6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AB5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AD6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AD5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AF6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC AF5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
-#set_property -dict {LOC T6  } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
-#set_property -dict {LOC T5  } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
-#set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
-
-# 100 MHz MGT reference clock
-#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
-
-#set_false_path -from [get_ports {pcie_reset_n}]
-#set_input_delay 0 [get_ports {pcie_reset_n}]
-
-# BPI flash
-#set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]
-#set_property -dict {LOC AC8  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[1]}]
-#set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[2]}]
-#set_property -dict {LOC AD9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[3]}]
-#set_property -dict {LOC AC11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}]
-#set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}]
-#set_property -dict {LOC AF14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}]
-#set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}]
-#set_property -dict {LOC AD14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}]
-#set_property -dict {LOC AF13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}]
-#set_property -dict {LOC AE13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}]
-#set_property -dict {LOC AD8  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}]
-#set_property -dict {LOC AC13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}]
-#set_property -dict {LOC AD13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}]
-#set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}]
-#set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}]
-#set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}]
-#set_property -dict {LOC AE11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}]
-#set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}]
-#set_property -dict {LOC AB11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}]
-#set_property -dict {LOC AB9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}]
-#set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}]
-#set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}]
-#set_property -dict {LOC AA9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}]
-#set_property -dict {LOC W10  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}]
-#set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}]
-#set_property -dict {LOC Y15  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}]
-#set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}]
-#set_property -dict {LOC V12  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}]
-#set_property -dict {LOC V11  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}]
-#set_property -dict {LOC Y12  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}]
-#set_property -dict {LOC W9   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}]
-#set_property -dict {LOC Y8   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}]
-#set_property -dict {LOC W8   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}]
-#set_property -dict {LOC W15  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}]
-#set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}]
-#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}]
-#set_property -dict {LOC AF15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}]
-#set_property -dict {LOC AE15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}]
-#set_property -dict {LOC AD15 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
-#set_property -dict {LOC AC9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_ce_n}]
-#set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}]
-#set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}]
-#set_property -dict {LOC Y10  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}]
-
-#set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
-#set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
-#set_false_path -from [get_ports {flash_dq[*]}]
-#set_input_delay 0 [get_ports {flash_dq[*]}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/fpga_k3p.xdc b/src/eth/example/Nexus_K3P_S/fpga/fpga_k3p.xdc
deleted file mode 100644
index 609b4e9..0000000
--- a/src/eth/example/Nexus_K3P_S/fpga/fpga_k3p.xdc
+++ /dev/null
@@ -1,195 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
-# part: xcku3p-ffvb676-2-e
-
-# General configuration
-set_property CFGBVS GND                                      [current_design]
-set_property CONFIG_VOLTAGE 1.8                              [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true                 [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup               [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 31.9                [current_design]
-set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8                [current_design]
-set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4           [current_design]
-set_property CONFIG_MODE BPI16                               [current_design]
-set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable        [current_design]
-
-# 10 MHz TXCO
-#set_property -dict {LOC D14  IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
-#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz]
-
-# LEDs
-set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
-set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
-set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
-set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
-set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
-set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
-
-set_false_path -to [get_ports {sfp_led[*][*] sma_led[*]}]
-set_output_delay 0 [get_ports {sfp_led[*][*] sma_led[*]}]
-
-# GPIO
-#set_property -dict {LOC F9   IOSTANDARD LVCMOS18} [get_ports {gpio[0]}]
-#set_property -dict {LOC F10  IOSTANDARD LVCMOS18} [get_ports {gpio[1]}]
-#set_property -dict {LOC G9   IOSTANDARD LVCMOS18} [get_ports {gpio[2]}]
-#set_property -dict {LOC G10  IOSTANDARD LVCMOS18} [get_ports {gpio[3]}]
-
-# SMA
-#set_property -dict {LOC A14  IOSTANDARD LVCMOS33} [get_ports {sma_in}]
-#set_property -dict {LOC A12  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {sma_out}]
-#set_property -dict {LOC A13  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_out_en}]
-#set_property -dict {LOC B12  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_term_en}]
-
-#set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}]
-#set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}]
-#set_false_path -from [get_ports {sma_in}]
-#set_input_delay 0 [get_ports {sma_in}]
-
-# Config
-#set_property -dict {LOC C14  IOSTANDARD LVCMOS33} [get_ports {ddr_npres}]
-
-# SFP28 Interfaces
-set_property -dict {LOC D2  } [get_ports {sfp_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC D1  } [get_ports {sfp_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC A4  } [get_ports {sfp_rx_p[1]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC A3  } [get_ports {sfp_rx_n[1]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC F7  } [get_ports {sfp_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC F6  } [get_ports {sfp_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC B7  } [get_ports {sfp_tx_p[1]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC B6  } [get_ports {sfp_tx_n[1]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
-set_property -dict {LOC K7  } [get_ports {sfp_mgt_refclk_p}] ;# MGTREFCLK0P_227 from X2
-set_property -dict {LOC K6  } [get_ports {sfp_mgt_refclk_n}] ;# MGTREFCLK0N_227 from X2
-set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
-set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
-set_property -dict {LOC F12  IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[0]}]
-set_property -dict {LOC F14  IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[1]}]
-set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}]
-set_property -dict {LOC Y17  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}]
-set_property -dict {LOC G14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0]}]
-set_property -dict {LOC H14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1]}]
-#set_property -dict {LOC A10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl}]
-#set_property -dict {LOC C11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}]
-#set_property -dict {LOC B11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}]
-
-# 161.1328125 MHz MGT reference clock
-create_clock -period 6.206 -name sfp_mgt_refclk [get_ports {sfp_mgt_refclk_p}]
-
-set_false_path -to [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
-set_output_delay 0 [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
-set_false_path -from [get_ports {sfp_npres[*] sfp_los[*]}]
-set_input_delay 0 [get_ports {sfp_npres[*] sfp_los[*]}]
-
-#set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-#set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
-
-# I2C interface
-#set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_scl}]
-#set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_sda}]
-
-#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
-
-# PCIe Interface
-#set_property -dict {LOC P2  } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC P1  } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC R5  } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC R4  } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC T2  } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC T1  } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC U5  } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC U4  } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC V2  } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC V1  } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC W5  } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC W4  } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
-#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
-#set_property -dict {LOC V7  } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
-#set_property -dict {LOC V6  } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
-#set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
-
-#set_false_path -from [get_ports {pcie_reset_n}]
-#set_input_delay 0 [get_ports {pcie_reset_n}]
-
-# 100 MHz MGT reference clock
-#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
-
-# BPI flash
-#set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}]
-#set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}]
-#set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}]
-#set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}]
-#set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
-#set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
-#set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
-#set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
-#set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
-#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
-#set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
-#set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
-#set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
-#set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
-#set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
-#set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
-#set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
-#set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
-#set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
-#set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
-#set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
-#set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
-#set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
-#set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
-#set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
-#set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
-#set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
-#set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
-#set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
-#set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
-#set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
-#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
-#set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
-#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
-#set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
-#set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
-#set_property -dict {LOC Y18  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
-#set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
-#set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
-#set_property -dict {LOC Y20  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
-#set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}]
-#set_property -dict {LOC Y21  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
-#set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
-#set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
-
-#set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
-#set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
-#set_false_path -from [get_ports {flash_dq[*]}]
-#set_input_delay 0 [get_ports {flash_dq[*]}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/bpi.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/bpi.xdc
new file mode 100644
index 0000000..84dd2fb
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/bpi.xdc
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# BPI flash
+set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]
+set_property -dict {LOC AC8  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[1]}]
+set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[2]}]
+set_property -dict {LOC AD9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[3]}]
+set_property -dict {LOC AC11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}]
+set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}]
+set_property -dict {LOC AF14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}]
+set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}]
+set_property -dict {LOC AD14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}]
+set_property -dict {LOC AF13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}]
+set_property -dict {LOC AE13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}]
+set_property -dict {LOC AD8  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}]
+set_property -dict {LOC AC13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}]
+set_property -dict {LOC AD13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}]
+set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}]
+set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}]
+set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}]
+set_property -dict {LOC AE11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}]
+set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}]
+set_property -dict {LOC AB11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}]
+set_property -dict {LOC AB9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}]
+set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}]
+set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}]
+set_property -dict {LOC AA9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}]
+set_property -dict {LOC W10  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}]
+set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}]
+set_property -dict {LOC Y15  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}]
+set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}]
+set_property -dict {LOC V12  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}]
+set_property -dict {LOC V11  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}]
+set_property -dict {LOC Y12  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}]
+set_property -dict {LOC W9   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}]
+set_property -dict {LOC Y8   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}]
+set_property -dict {LOC W8   IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}]
+set_property -dict {LOC W15  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}]
+set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}]
+set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}]
+set_property -dict {LOC AF15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}]
+set_property -dict {LOC AE15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}]
+set_property -dict {LOC AD15 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
+set_property -dict {LOC AC9  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_ce_n}]
+set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}]
+set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}]
+set_property -dict {LOC Y10  IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}]
+
+set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+set_false_path -from [get_ports {flash_dq[*]}]
+set_input_delay 0 [get_ports {flash_dq[*]}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/fpga.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/fpga.xdc
new file mode 100644
index 0000000..0e0e2af
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/fpga.xdc
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
+set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2      [current_design]
+set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# 100 MHz system clock
+set_property -dict {LOC D18  IOSTANDARD LVDS} [get_ports {clk_100mhz_p}]
+set_property -dict {LOC C18  IOSTANDARD LVDS} [get_ports {clk_100mhz_n}]
+create_clock -period 10 -name clk_100mhz [get_ports {clk_100mhz_p}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/gpio.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/gpio.xdc
new file mode 100644
index 0000000..959156e
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/gpio.xdc
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# LEDs
+set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
+set_property -dict {LOC A24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
+set_property -dict {LOC E23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
+set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
+set_property -dict {LOC C23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
+set_property -dict {LOC D23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
+
+set_false_path -to [get_ports {sfp_led[*][*] sma_led[*]}]
+set_output_delay 0 [get_ports {sfp_led[*][*] sma_led[*]}]
+
+# GPIO
+#set_property -dict {LOC W26  IOSTANDARD LVCMOS18} [get_ports {gpio[0]}]
+#set_property -dict {LOC Y26  IOSTANDARD LVCMOS18} [get_ports {gpio[1]}]
+#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}]
+#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}]
+
+# SMA
+#set_property -dict {LOC B17  IOSTANDARD LVCMOS18} [get_ports {sma_in}]
+#set_property -dict {LOC B16  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {sma_out}]
+#set_property -dict {LOC B19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_out_en}]
+#set_property -dict {LOC C16  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_term_en}]
+
+#set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}]
+#set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}]
+#set_false_path -from [get_ports {sma_in}]
+#set_input_delay 0 [get_ports {sma_in}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/i2c.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/i2c.xdc
new file mode 100644
index 0000000..7a14256
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/i2c.xdc
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# I2C interface
+set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_scl}]
+set_property -dict {LOC C26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_sda}]
+
+set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/pcie.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/pcie.xdc
new file mode 100644
index 0000000..5d869f6
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/pcie.xdc
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# PCIe Interface
+set_property -dict {LOC P2  } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC P1  } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC R4  } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC R3  } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC T2  } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC T1  } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC U4  } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC U3  } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC V2  } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC V1  } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC W4  } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC W3  } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC AA4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC AA3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AB6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AB5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AD6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AD5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AF6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC AF5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+set_property -dict {LOC T6  } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
+set_property -dict {LOC T5  } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
+set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+create_clock -period 10.000 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
+
+set_false_path -from [get_ports {pcie_reset_n}]
+set_input_delay 0 [get_ports {pcie_reset_n}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K35/sfp.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/sfp.xdc
new file mode 100644
index 0000000..8f8e917
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K35/sfp.xdc
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K35-S / ExaNIC X10
+# part: xcku035-fbva676-2-e
+
+# SFP+ Interfaces
+set_property -dict {LOC D2  } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC D1  } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC E4  } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC E3  } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC C4  } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC C3  } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC D6  } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC D5  } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC H6  } [get_ports {sfp_mgt_refclk_p}] ;# MGTREFCLK0P_227 from X2
+set_property -dict {LOC H5  } [get_ports {sfp_mgt_refclk_n}] ;# MGTREFCLK0N_227 from X2
+set_property -dict {LOC AA12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
+set_property -dict {LOC W14  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
+set_property -dict {LOC C24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[0]}]
+set_property -dict {LOC D24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[1]}]
+set_property -dict {LOC W13  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}]
+set_property -dict {LOC AB12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}]
+set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0]}]
+set_property -dict {LOC D25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1]}]
+#set_property -dict {LOC W11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl}]
+#set_property -dict {LOC Y11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}]
+#set_property -dict {LOC Y13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}]
+
+# 161.1328125 MHz MGT reference clock
+create_clock -period 6.206 -name sfp_mgt_refclk [get_ports {sfp_mgt_refclk_p}]
+
+set_false_path -to [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
+set_output_delay 0 [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
+set_false_path -from [get_ports {sfp_npres[*] sfp_los[*]}]
+set_input_delay 0 [get_ports {sfp_npres[*] sfp_los[*]}]
+
+#set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/bpi.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/bpi.xdc
new file mode 100644
index 0000000..812e5eb
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/bpi.xdc
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# BPI flash
+set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}]
+set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}]
+set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}]
+set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}]
+set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
+set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
+set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
+set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
+set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
+set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
+set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
+set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
+set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
+set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
+set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
+set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
+set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
+set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
+set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
+set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
+set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
+set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
+set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
+set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
+set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
+set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
+set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
+set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
+set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
+set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
+set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
+set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
+set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
+set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
+set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
+set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
+set_property -dict {LOC Y18  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
+set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
+set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
+set_property -dict {LOC Y20  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
+set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}]
+set_property -dict {LOC Y21  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
+set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
+set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
+
+set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+set_false_path -from [get_ports {flash_dq[*]}]
+set_input_delay 0 [get_ports {flash_dq[*]}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/fpga.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/fpga.xdc
new file mode 100644
index 0000000..60cb21e
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/fpga.xdc
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# General configuration
+set_property CFGBVS GND                                      [current_design]
+set_property CONFIG_VOLTAGE 1.8                              [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true                 [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup               [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 31.9                [current_design]
+set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8                [current_design]
+set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4           [current_design]
+set_property CONFIG_MODE BPI16                               [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable        [current_design]
+
+# 10 MHz TXCO
+#set_property -dict {LOC D14  IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
+#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/gpio.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/gpio.xdc
new file mode 100644
index 0000000..116d4a2
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/gpio.xdc
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# LEDs
+set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
+set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
+set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
+set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
+set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
+set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
+
+set_false_path -to [get_ports {sfp_led[*][*] sma_led[*]}]
+set_output_delay 0 [get_ports {sfp_led[*][*] sma_led[*]}]
+
+# GPIO
+#set_property -dict {LOC F9   IOSTANDARD LVCMOS18} [get_ports {gpio[0]}]
+#set_property -dict {LOC F10  IOSTANDARD LVCMOS18} [get_ports {gpio[1]}]
+#set_property -dict {LOC G9   IOSTANDARD LVCMOS18} [get_ports {gpio[2]}]
+#set_property -dict {LOC G10  IOSTANDARD LVCMOS18} [get_ports {gpio[3]}]
+
+# SMA
+#set_property -dict {LOC A14  IOSTANDARD LVCMOS33} [get_ports {sma_in}]
+#set_property -dict {LOC A12  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {sma_out}]
+#set_property -dict {LOC A13  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_out_en}]
+#set_property -dict {LOC B12  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_term_en}]
+
+#set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}]
+#set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}]
+#set_false_path -from [get_ports {sma_in}]
+#set_input_delay 0 [get_ports {sma_in}]
+
+# Config
+#set_property -dict {LOC C14  IOSTANDARD LVCMOS33} [get_ports {ddr_npres}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/i2c.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/i2c.xdc
new file mode 100644
index 0000000..26b7599
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/i2c.xdc
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# I2C interface
+set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_scl}]
+set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {eeprom_i2c_sda}]
+
+set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/pcie.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/pcie.xdc
new file mode 100644
index 0000000..26ae1a4
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/pcie.xdc
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# PCIe Interface
+set_property -dict {LOC P2  } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC P1  } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC R5  } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC R4  } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC T2  } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC T1  } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC U5  } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC U4  } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC V2  } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC V1  } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC W5  } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC W4  } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC V7  } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
+set_property -dict {LOC V6  } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
+set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+create_clock -period 10.000 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+set_false_path -from [get_ports {pcie_reset_n}]
+set_input_delay 0 [get_ports {pcie_reset_n}]
diff --git a/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/sfp.xdc b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/sfp.xdc
new file mode 100644
index 0000000..25b9cd3
--- /dev/null
+++ b/src/eth/example/Nexus_K3P_S/fpga/syn/K3P/sfp.xdc
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Cisco Nexus K3P-S / ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# SFP28 Interfaces
+set_property -dict {LOC D2  } [get_ports {sfp_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC D1  } [get_ports {sfp_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC A4  } [get_ports {sfp_rx_p[1]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC A3  } [get_ports {sfp_rx_n[1]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC F7  } [get_ports {sfp_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC F6  } [get_ports {sfp_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC B7  } [get_ports {sfp_tx_p[1]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC B6  } [get_ports {sfp_tx_n[1]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC K7  } [get_ports {sfp_mgt_refclk_p}] ;# MGTREFCLK0P_227 from X2
+set_property -dict {LOC K6  } [get_ports {sfp_mgt_refclk_n}] ;# MGTREFCLK0N_227 from X2
+set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
+set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
+set_property -dict {LOC F12  IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[0]}]
+set_property -dict {LOC F14  IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[1]}]
+set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}]
+set_property -dict {LOC Y17  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}]
+set_property -dict {LOC G14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0]}]
+set_property -dict {LOC H14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1]}]
+#set_property -dict {LOC A10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl}]
+#set_property -dict {LOC C11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}]
+#set_property -dict {LOC B11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}]
+
+# 161.1328125 MHz MGT reference clock
+create_clock -period 6.206 -name sfp_mgt_refclk [get_ports {sfp_mgt_refclk_p}]
+
+set_false_path -to [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
+set_output_delay 0 [get_ports {sfp_tx_disable[*] sfp_rs[*]}]
+set_false_path -from [get_ports {sfp_npres[*] sfp_los[*]}]
+set_input_delay 0 [get_ports {sfp_npres[*] sfp_los[*]}]
+
+#set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]